Patents Examined by Mark W Tornow
  • Patent number: 12087889
    Abstract: Chlorophyll a absorbs violet (high-energy; max. 372 nm) and orange light (low-energy; max. 642 nm) the most; the mid-point being 507 nm. Chlorophyll b absorbs mostly blue (high energy; max. 392 nm) and yellow (low-energy; max. 626 nm) light; the mid-point being 509 nm. They both also absorb light of other wavelengths with less intensity. Both mid-points are nearly identical to the mid-point between energy and entropy maximum of scattered sunlight. The claimed microelectronic device provides radiation for artificial lighting applications from ruthenium vapor in the blue and deep red region. The entropy (heat) generated by inefficiencies in p-n junction recombination and luminescent materials' Stokes shift is transferred to the thermodynamic heats of evaporation and sublimation of rubidium atoms. The microelectronic device eliminates the need for external cooling of indoor greenhouse environments used for growth of crops under continuous artificial lighting.
    Type: Grant
    Filed: March 8, 2024
    Date of Patent: September 10, 2024
    Inventor: Bruce H Baretz
  • Patent number: 12087806
    Abstract: A display device includes a first substrate including a display area comprising pixels, and a non-display area surrounding the display area, a thin film transistor layer disposed on the first substrate and comprising a thin film transistor, a second substrate disposed on the thin film transistor layer and facing the first substrate, a sealing part disposed between the first substrate and the second substrate in the non-display area, and bonding the first and second substrates, a metal line disposed in the non-display area on the thin film transistor layer and overlapping the sealing part, and an antistatic member comprising a support supported by the metal line, a first receiver protruding from a top portion of the support to an exterior of the sealing part, and a second receiver protruding from a bottom portion of the support toward the exterior of the sealing part and facing the first receiver.
    Type: Grant
    Filed: September 23, 2021
    Date of Patent: September 10, 2024
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Ki Yeup Lee, Sang Yong No, Ji Yeon Choi, Tae Ho Kang, Hwa Rang Lee
  • Patent number: 12074252
    Abstract: An optoelectronic semiconductor device includes a substrate, a first type semiconductor structure, a second type semiconductor structure, an active structure and a contact structure. The first type semiconductor structure is located on the substrate and has a first protrusion part with a first thickness and a platform part with a second thickness. The second type semiconductor structure is located on the first type semiconductor structure. The active structure is between the first type semiconductor structure and the second type semiconductor structure. The contact structure is disposed between the first type semiconductor structure and the substrate. The second thickness of the platform part is in a range of 0.01 ?m to 1 ?m.
    Type: Grant
    Filed: September 19, 2022
    Date of Patent: August 27, 2024
    Assignee: EPISTAR CORPORATION
    Inventors: Chung-Hao Wang, Yu-Chi Wang, Yi-Ming Chen, Yi-Yang Chiu, Chun-Yu Lin
  • Patent number: 12075662
    Abstract: A display panel includes a substrate, a transistor on the substrate, a storage capacitor on the substrate and electrically connected to the transistor, a metal layer between the substrate and the transistor, a first insulating layer on the metal layer and having a first contact hole, and a wiring connected to the metal layer through the first contact hole, wherein the first insulating layer having a first hole apart from the transistor.
    Type: Grant
    Filed: April 17, 2023
    Date of Patent: August 27, 2024
    Assignee: Samsung Display Co., Ltd.
    Inventors: Injun Bae, Donghwi Kim, Chulho Kim, Woori Seo, Jin Jeon
  • Patent number: 12055801
    Abstract: A device for modulating the amplitude of an incident laser radiation of wavelength ?i is provided.
    Type: Grant
    Filed: March 27, 2020
    Date of Patent: August 6, 2024
    Assignees: CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE, UNIVERSITE PARIS SACLAY
    Inventors: Raffaele Colombelli, Stefano Pirotta, Ngoc Linh Tran
  • Patent number: 12052865
    Abstract: Embodiments of three-dimensional (3D) memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate and a channel structure extending vertically above the substrate and having a plum blossom shape including a plurality of petals in a plan view. The channel structure includes, in each of the plurality of petals, a charge trapping layer, a tunneling layer, a semiconductor channel, and a channel plug. The channel plug is above and in contact with the charge trapping layer, the tunneling layer, and the semiconductor channel.
    Type: Grant
    Filed: December 4, 2020
    Date of Patent: July 30, 2024
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventors: Tingting Gao, Lei Xue, Xiaoxin Liu, Wanbo Geng
  • Patent number: 12051677
    Abstract: A front-mounted high-voltage LED light source for supplementing light to plants includes a substrate, a high-voltage LED chip set, a first layer of glue powder and a second layer of glue powder. By controlling a weight ratio of the transparent adhesive medium and the red fluorescent particles in the first layer of glue powder, as well as thickness of the first layer of glue powder; and, by controlling a weight ratio of the transparent adhesive medium and the yellow fluorescent particles in the second layer of glue powder, as well as the thickness of the second layer of glue powder, a ratio range of photon number of red light, blue light to green light emitted by the front-mounted high-voltage LED light source for supplementing light to plants per a unit time is (65-95):(5-30):(5-25).
    Type: Grant
    Filed: November 1, 2019
    Date of Patent: July 30, 2024
    Assignee: HANGZHOU HANHUI OPTOELECTRONIC TECHNOLOGY CO., LTD.
    Inventors: Xiang Pan, Xuke Li
  • Patent number: 12046633
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to airgap structures in a doped region under one or more transistors and methods of manufacture. The structure includes: a semiconductor material comprising a doped region; one or more sealed airgap structures breaking up the doped region of the semiconductor material; and a field effect transistor over the one or more sealed airgap structures and the semiconductor material.
    Type: Grant
    Filed: January 25, 2021
    Date of Patent: July 23, 2024
    Assignee: GLOBALFOUNDRIES U.S. Inc.
    Inventors: Mark D. Levy, Siva P. Adusumilli, Johnatan A. Kantarovsky, Vibhor Jain
  • Patent number: 12040346
    Abstract: A full-color display module with an ultra-wide color gamut (UWCG) is based on a specific type of pixel applicable for display. The full-color display module is based on a red-green-cyan-blue-pixel (RGCB-pixel) and thus, includes at least one red-light source, at least one green-light source, at least one cyan-light source, and at least one blue-light source. The full-color display module comprises a substrate that establishes an electrical base for the at least one red-light source, at least one green-light source, at least one cyan-light source, and at least one blue-light source. The full-color display module can display all colors in the color gamut of UWCG, has excellent luminous efficiency and durability, and is advantageous in realizing high resolution by improving the degree of integration of the light source array itself.
    Type: Grant
    Filed: August 24, 2021
    Date of Patent: July 16, 2024
    Inventors: Yung Ryel Ryu, Ui Kyu Bang
  • Patent number: 12027647
    Abstract: A semiconductor light-emitting element according to the present invention includes an n-type semiconductor layer, an active layer, a p-type semiconductor layer, and a p-electrode. The n-type semiconductor layer has a composition of AlGaN or AlInGaN. The active layer is formed on the n-type semiconductor layer. The active layer contains an AlGaN semiconductor or an AlInGaN semiconductor. The p-type semiconductor layer is formed on the active layer. The p-type semiconductor layer has a composition of AlN, AlGaN, or AlInGaN. The p-electrode is formed on the p-type semiconductor layer. The p-type semiconductor layer includes a contact layer formed on the p-electrode. The contact layer includes an AlGaN layer or an AlInGaN layer in which a band gap decreases toward an interface with the p-electrode. The contact layer includes a tunneling contact layer in contact with the p-electrode. The tunneling contact layer is connected to the p-electrode by a tunnel junction.
    Type: Grant
    Filed: October 7, 2019
    Date of Patent: July 2, 2024
    Assignee: STANLEY ELECTRIC CO., LTD.
    Inventors: Toshiyuki Obata, Yasuhiro Hashimoto
  • Patent number: 12015102
    Abstract: A top emitting quantum dot light emitting diode (QLED) apparatus for an emissive display device sub-pixel, with at least one bank defining an emissive region of the emissive display device sub-pixel, includes an emissive layer deposited in the emissive region between a first electrode and a second electrode. The first electrode comprising a reflective metal, and the second electrode has a transparent conductive electrode and an auxiliary electrode. The bank has a sloped portion adjacent the emissive region. The auxiliary electrode includes a reflective conductive metal and is configured to cover the sloped portion, and the sloped portion is configured at an angle, such that the auxiliary electrode reflects internally reflected light out of the sub-pixel in a viewing direction and a first area of the transparent conductive electrode covering the sloped portion is thinner than a second area of the transparent conductive electrode in the emissive region.
    Type: Grant
    Filed: April 30, 2021
    Date of Patent: June 18, 2024
    Assignee: SHARP KABUSHIKI KAISHA
    Inventor: Hywel Hopkin
  • Patent number: 12016198
    Abstract: A display panel and a manufacture method thereof, and a display apparatus are provided. The display panel has a display region and a border region that surrounds the display region and includes a peripheral circuit region and a peripheral region; the peripheral circuit region is between the display region and the peripheral region. At least a part of a barrier structure of the display panel is in the peripheral circuit region, and the barrier structure includes an organic barrier layer including an opening passing through the organic barrier layer and an inorganic barrier layer covering the organic barrier layer and filling the opening; an extension direction of the opening is same as that of an edge, close to the opening, of the display panel; the peripheral circuit is in the peripheral circuit region.
    Type: Grant
    Filed: January 18, 2023
    Date of Patent: June 18, 2024
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Xinwei Gao, Kaihong Ma, Dacheng Zhang, Lang Liu, Chen Xu
  • Patent number: 12009457
    Abstract: A nitride semiconductor light-emitting element outputs ultraviolet light. The nitride semiconductor light-emitting element includes an active layer including a quantum well structure that generates the ultraviolet light, a dislocation suppression structure-containing layer being formed on the active layer and including a dislocation suppression structure that stops or bends a dislocation from the active layer; and a p-type contact layer being formed on the dislocation suppression structure-containing layer and having a thickness of not less than 10 nm and not more than 30 nm.
    Type: Grant
    Filed: October 15, 2021
    Date of Patent: June 11, 2024
    Assignee: Nikkiso Co., Ltd.
    Inventors: Yusuke Matsukura, Cyril Pernot
  • Patent number: 12009454
    Abstract: A light-emitting device includes an n-side semiconductor layer comprising an n-type contact layer and an intermediate layer located on the n-type contact layer; an active layer located on the intermediate layer; and a p-side semiconductor layer located on the active layer. The intermediate layer includes at least one stacked portion comprising a first layer and a second layer. The first layer is an n-type nitride semiconductor layer comprising an n-type impurity, Al, and Ga. The second layer is a nitride semiconductor layer that includes Al and Ga, has a lower n-type impurity concentration than the first layer, and has a larger thickness than the first layer. An Al composition ratio of the first layer is higher than an Al composition ratio of the second layer.
    Type: Grant
    Filed: October 21, 2021
    Date of Patent: June 11, 2024
    Assignee: NICHIA CORPORATION
    Inventor: Takuya Okada
  • Patent number: 12009335
    Abstract: A method of manufacturing a semiconductor device structure includes forming a bond or joint between a first device and a second device. The first device comprises an integrated passive device (IPD) and a first contact pad disposed over the IPD. The second device comprises a second contact pad. The first contact pad has a first surface with first lateral extents. The second contact pad has a second surface with second lateral extents. The width of the second lateral extents is less than the width of the first lateral extents. The joint structure includes the first contact pad, the second contact pad, and a solder layer interposed therebetween. The solder layer has tapered sidewalls extending in a direction away from the first surface of the first contact pad to the second surface of the second contact pad. At least one of the first surface or the second surface is substantially planar.
    Type: Grant
    Filed: June 6, 2022
    Date of Patent: June 11, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ying-Ju Chen, An-Jhih Su, Hsien-Wei Chen, Der-Chyang Yeh, Chi-Hsi Wu, Chen-Hua Yu
  • Patent number: 12009352
    Abstract: Provided herein include various examples of a method for manufacturing aspects of an apparatus, a sensor system. The method may include obtaining a first carrier bonded to an upper surface of the silicon wafer. This wafer includes through silicon vias (TSVs) extended through openings in a passivation stack, with electrical contacts coupled to portions of the TSVs exposed through these openings. The method may include de-bonding the first carrier from the upper surface of the silicon wafer. The method may include dicing the silicon wafer into subsections comprising dies.
    Type: Grant
    Filed: September 16, 2020
    Date of Patent: June 11, 2024
    Assignee: Illumina, Inc.
    Inventors: Arvin Emadi, Jon Aday, Ali Agah, Arnaud Rival
  • Patent number: 12002843
    Abstract: Disclosed are a display panel and a display device. The display panel includes a display region, multiple pixels and a substrate. The display region includes an optical component region and a first display region. The multiple pixels include a first pixel and a second pixel, the first pixel includes a first light-emitting element located in the optical component region, and the second pixel includes a second light-emitting element located in the first display region. The optical component region includes an anode connecting line segment, the first light-emitting element includes a first anode, and the anode connecting line segment is electrically connected to the first anode; and in a direction perpendicular to a plane where the substrate is located, an area of the first anode is S1 and an electrical connection area of the first anode and the anode connecting line segment is S2, where 5%<S2/S1?100%.
    Type: Grant
    Filed: July 16, 2021
    Date of Patent: June 4, 2024
    Assignee: Wuhan Tianma Micro-Electronics Co., Ltd.
    Inventors: Meihong Wang, Yangzhao Ma
  • Patent number: 11990564
    Abstract: A semiconductor light-emitting element according to the present invention includes an n-type semiconductor layer, an active layer, a p-type semiconductor layer, and a p-electrode. The n-type semiconductor layer has a composition of AlGaN or AlInGaN. The active layer is formed on the n-type semiconductor layer. The active layer contains an AlGaN semiconductor or an AlInGaN semiconductor. The p-type semiconductor layer is formed on the active layer. The p-type semiconductor layer has a composition of AlN, AlGaN, or AlInGaN. The p-electrode is formed on the p-type semiconductor layer. The p-type semiconductor layer includes a contact layer formed on the p-electrode. The contact layer includes an AlGaN layer or an AlInGaN layer in which a band gap decreases toward an interface with the p-electrode. The contact layer includes a tunneling contact layer in contact with the p-electrode. The tunneling contact layer is connected to the p-electrode by a tunnel junction.
    Type: Grant
    Filed: October 7, 2019
    Date of Patent: May 21, 2024
    Assignee: STANLEY ELECTRIC CO., LTD.
    Inventors: Toshiyuki Obata, Yasuhiro Hashimoto
  • Patent number: 11990474
    Abstract: A method of fabricating a semiconductor device includes forming a gate structure, a first edge structure and a second edge structure on a semiconductor strip. The method further includes forming a first source/drain feature between the gate structure and the first edge structure. The method further includes forming a second source/drain feature between the gate structure and the second edge structure, wherein a distance between the gate structure and the first source/drain feature is different from a distance between the gate structure and the second source/drain feature. The method further includes implanting a buried channel in the semiconductor strip, wherein the buried channel is entirely below a top-most surface of the semiconductor strip, a maximum depth of the buried channel is less than a maximum depth of the first source/drain feature, and a dopant concentration of the buried channel is highest under the gate structure.
    Type: Grant
    Filed: January 9, 2023
    Date of Patent: May 21, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shu Fang Fu, Chi-Feng Huang, Chia-Chung Chen, Victor Chiang Liang, Fu-Huan Tsai
  • Patent number: 11984531
    Abstract: Provided is a light emitting device. A light emitting device includes a first n-type semiconductor layer, a first light emitting layer disposed on the first n-type semiconductor layer, a first p-type semiconductor layer disposed on the first light emitting layer, a second p-type semiconductor layer disposed on the first p-type semiconductor layer, a bonding layer disposed between the first p-type semiconductor layer and the second p-type semiconductor layer, a second light emitting layer disposed on the second p-type semiconductor layer, a second n-type semiconductor layer disposed on the second light emitting layer, a p-type electrode disposed on the second p-type semiconductor layer, a first n-type electrode disposed on the first n-type semiconductor layer, and a second n-type electrode disposed on the second n-type semiconductor layer.
    Type: Grant
    Filed: June 22, 2021
    Date of Patent: May 14, 2024
    Assignee: LG DISPLAY CO., LTD.
    Inventors: KooHwa Lee, WooNam Jeong, HyeonHo Son