Abstract: A semiconductor device which includes either a single semiconductor chip bearing an integrated circuit (IC) or two or more electrically interconnected semiconductor chips, is disclosed. This device includes interconnects between device components (on the same chip and/or on different chips), at least one of which includes a region of superconducting material, e.g., a region of copper oxide superconductor having a T.sub.c greater than about 77K. Significantly, to avoid undesirable interactions, at high processing temperatures, between the superconducting material and underlying, silicon-containing material (which, among other things, results in the superconducting material reverting to its non-superconducting state), the interconnect also includes a combination of material regions which prevents such interactions.

Abstract: A semiconductor device comprises a first superlattice layer consisting of a first semiconductor layer that contains impurities and a second semiconductor layer that contains impurities at a low concentration, said first superlattice layer being formed on a semiconductor substrate; and a second superlattice layer that covers that exposed side walls of said first superlattice layer. A disordered region is formed in the vicinity of the first semiconductor layer of the second superlattice layer in order to realize quantum wires with the conventional manufacturing process. This makes it possible to easily fabricate a laser device, a light-emitting diode and a transistor having quantum wires to enhance their performance.

Abstract: A semiconductor apparatus is disclosed, in which the entire or part of an electron active region is formed by a superlattice structure semiconductor layer in which a plurality of different semiconductor layers, less than 8 monolayers, and containing a fraction or a binary compound semiconductor layers are alternately and epitaxially grown and a main current direction is selected to be in the direction perpendicular to the laminae of said superlattice layers.

Abstract: This disclosure is a integrated circuit reference diode having improved manufacturability and electrical characteristics. The improved diode results from a structure and process which both reduces the subsurface breakdown and enhances the surface breakdown.

Abstract: An electron emission device comprises a P-type semiconductor layer which emits electron injected into the P-type semiconductor layer by utilizing the negative electron affinity state. At least one of said N-type semiconductor layer and the P-type semiconductor layer is made to have a super-lattice structure.

Abstract: A P-type epitaxial silicon layer is formed between an N-type epitaxial layer and a P.sup.+ -type semiconductor substrate. An impurity concentration profile is formed in at least one region of the P-type epitaxial silicon layer to decrease with an increase in distance from the substrate and toward the N-type epitaxial layer. A depletion layer is formed as a function region (P-N junction) between the P-type epitaxial silicon layer and the N-type epitaxial layer. Carriers are generated when light is incident on the depletion layer. Carriers are also generated in a region of the P-type layer deeper than the depletion layer. A self-electric field is formed in the P-type epitaxial silicon layer by the impurity concentration profile, which is lowest at the junction. The carriers generated in this manner are accelerated by the self-electric field and flow rapidly into the function region. As a result, an optical semiconductor device according to the present invention has good response characteristics.

Abstract: Junction field effect transistors are described with unusually short gates and a self-aligned structure which permits close approach of the source and drain electrodes to the p-n junction. Such devices have high speed, high gain and are usefully combined with other field effect transistors in integrated circuits.

Abstract: An improved compound semiconductor hot electron transistor (HET) having room temperature current gain .beta.>10 is disclosed. Disclosed are also means by which improved HET performance can be obtained. Among these means is choice of the base layer material such that the hot electrons injected into the base have k.sub.i,2 /k.sub.i,1 >0.2, where k.sub.i,1 and k.sub.i,2 are the components of the electron wave vector respectively normal and parallel to the emitter/base interface. A further means is choice of collector material such that the hot electron velocity component normal to the base/collector interface remains relatively unchanged upon passage of the hot electron through the base/collector interface. For instance, an appropriate superlattice in the collector region may be used to achieve such matching. Causing quantization of the ambient charge carrier states in the base can reduce hot electron scattering in the base.

Abstract: A power transistor according to the present invention improves breakdown resistance, in a monolithic structure for connecting a first-stage transistor and a second-stage transistor in Darlington connection, by constructing the same such that no parasitic transistor is substantially formed in the area for connecting the first-stage and second-stage transistors.

Abstract: A semiconductor resin package structure formed according to the flip-chip connection method and permitting to cool the rear surface of semiconductor chips, comprising semiconductor chip and carrier substrate which is soldered on one surface thereof to electrodes of the semiconductor chip according to the flip-chip connection method, the gap between the semiconductor chip and the carrier substrate being filled with resin having a thermal expansion coefficient, which is approximately equal to that of used solder, the electrodes of the semiconductor chip being electrically connected with terminals on the other surface of the carrier substrate through the soldered portions and a through-hole conductor disposed on the carrier substrate, the thermal expansion coefficient of the carrier substrate being approximately equal to that of a multi-layer substrate, with which the substrate is connected by soldering with the terminals.

Abstract: A bipolar transistor in which the base region includes a heterostructure and a doped layer of semiconductor material with the heterostructure functioning as a two-dimensional hole gas. The doped layer is sufficiently thin to prevent occurrence of a charge-neutral region of holes. In operation the transistor can switch quickly since minority charge storage in the base region does not present a problem. The device lends itself to downscaling in size in a VLSI circuit.

Abstract: A semiconductor diode includes a semiconductor body having a first region (1) of one conductivity type, a second region (2) of the opposite conductivity type meeting only a given surface (4) of the body and surrounded by the first region (1) so as to form with the first region (1) a first pn junction (3) which, when reverse-biassed in operation of the diode by a voltage applied across the diode, gives the diode a blocking characteristic, and a third region (15) of the one conductivity type more highly doped than the first region (1) provided within the first region (1) for triggering conduction of the diode when a predetermined voltage less than that at which the main pn junction (3) would have broken down in the absence of the third region (15) is applied across the diode to reverse bias the first pn junction. The third region (15) meets only the given surface (4) and a passivating layer (9) on the given surface covers the third region (15).

Abstract: A compound semiconductor device having a channel layer which is fabricated by alternately laminating an In.sub.x Ga.sub.1-x As compound semiconductor layer (0.7.ltoreq.x.ltoreq.1.0) with thickness of 16 atomic planes or less, and an In.sub.y Ga.sub.1-y As compound semiconductor layer (0.ltoreq.y.ltoreq.0.3) with thickness of 14 atomic planes or less, so that the thickness of the former is greater than that of the latter, in which n-type impurities are doped only in the In.sub.y Ga.sub.1-y As layer (0.ltoreq.y.ltoreq.0.3) side, and a ratio In/Ga on the whole is set at 1.1 or higher.

Abstract: Extension directions of source electrode layer and a drain electrode are parallel to rows or columns of an array of alternately arranged source regions and drain regions, thereby forming widths of source and drain electrode layers wider than those of a conventional transistor to obtain a large mutual conductance.

Abstract: A device for protecting semiconductor devices during excess energy events. The device uses p-MOS field effect transistors in a common n-well with a common gate configuration. An input is coupled to the source of a first p-type transistor and to the n-well. The first transistor is coupled through a series resistor to a second p-MOS transistor. The drains of each transistor are coupled to ground and gate aided breakdown reduces the voltage at which breakdown occurs.

Abstract: A hybrid thick film chip device comprising two or more electrical components mounted in parallel on a single substrate and having common terminals for electrical interconnection to other devices or to circuit boards or the like. In one embodiment, the components comprise a resistor and a capacitor disposed on one surface of the substrate. In another embodiment the resistor is on one surface of the substrate and the capacitor is on the opposite surface. The device is particularly advantageous in forming networks.

Abstract: An MOSFET provided with a gate insulating film formed on a semiconductor surface between a source region and a drain region, a gate electrode formed on the gate insulating film, and a channel region sandwiched between the source region and the drain region and made up of a first layer and a second layer is disclosed in which the first layer lies beneath the gate insulating film and is opposite in conductivity type to the source and drain regions, the second layer lies beneath the first layer and has the same conductivity type as the source and drain regions, and the length of the second layer between the source region and the drain region is greater than the length of the first layer between the source region and the drain region.

Abstract: A novel method which enables a quaternary III-V group crystal to be readily formed on a III-V group crystal so that the former crystal lattice-matches with the latter crystal. More specifically, it is easy to produce a superlattice structure on a III-V group crystal substrate, the superlattice structure consisting of a first III-V group (hereinafter referred to as "III.sup.1 -V.sup.1 ") binary crystal layer which lattice-matches with the substrate, and a III-V group (III.sup.1 -III.sup.2 -V.sup.2) ternary crystal layer which similarly lattice-matches with the substrate. It is possible to obtain an even more stable superlattice layer by selecting the ratio between the film thickness of the (III.sup.1 -V.sup.1) crystal and the film thickness of the (III.sup.1 -III.sup.2 -V.sup.2) crystal so that, when the superlattice structure is mixed-crystallized spontaneously or by means of impurity doping, the mixed-crystallized composition lattice-matches with the previous crystal.

Abstract: In a semiconductor device having mainly vertical semiconductor elements, a plurality of semiconductor elements are formed in spaced relationship from each other on an insulation layer formed on a substrate and therefore completed isolated electrically from each other. A plurality of semiconductor intermetallic compound layers used as electrodes are formed independently in the same spaced relationship as the semiconductor elements for the respective semiconductor elements, making it possible to determine the potential for each semiconductor element as desired. Both N-type DMOS and P-type DMOS or the like can thus be formed on a single seminconductor single crystal substrate.

Abstract: A junction field effect semiconductor device is provided with p-type source and drain semiconductor regions separately formed in an n-type expitaxial layer grown on a substrate, a p-type channel layer, a highly doped n.sup.+ -type gate region surrounding the source and drain regions and the channel layer, and a highly doped n.sup.+ -type top gate layer formed on the channel layer. The channel layer is formed only in an area bounded between the source and drain regions, so that it is possible to make a drain current proportional to a channel width to length ratio.