Patents Examined by Marvin Payen
  • Patent number: 10446598
    Abstract: A method of manufacturing a semiconductor device includes: forming, on a cover glass, a film having a predetermined specific gravity and configured to shield an alpha ray that arises from the cover glass; and bonding the cover glass on which the film is formed and an image pickup device, by filling a transparent resin between the cover glass and the image pickup device.
    Type: Grant
    Filed: August 27, 2018
    Date of Patent: October 15, 2019
    Assignee: Sony Corporation
    Inventors: Satoru Wakiyama, Taizo Takachi
  • Patent number: 10446534
    Abstract: In one embodiment, a capacitor includes a first row including a first capacitor element and a second capacitor element coupled in parallel, and a second row including a third capacitor element and a fourth capacitor element coupled in parallel. The first row is coupled in series with the second row. In a metallization level over a workpiece, the second capacitor element is disposed between the first capacitor element and the third capacitor element. In the metallization level, the third capacitor element is disposed between the second capacitor element and the fourth capacitor element. The first, the second, the third, and the fourth capacitor elements are disposed in the metallization level.
    Type: Grant
    Filed: October 15, 2016
    Date of Patent: October 15, 2019
    Assignee: Infineon Technologies AG
    Inventors: Michael Roehner, Stefano Aresu
  • Patent number: 10439097
    Abstract: A method for manufacturing a light emitting device includes: preparing an LED die having a laminated structure including a light emitting surface, an electrode forming surface, and a side surface, and at least one electrode placed on the electrode forming surface; preparing a wavelength conversion member having an upper surface defining a recess, the recess having an opening diameter greater than a diameter of the light emitting surface in a plan view; placing a light-transmissive member within the recess; mounting the LED die on an upper surface of the light-transmissive member white the light emitting surface faces the upper surface of the light-transmissive member and pressing the LED die so that at least a portion of the light-transmissive member is placed on the side surface of the laminated structure; and placing a light reflecting member to cover the LED die, the light-transmissive member, and the wavelength conversion member.
    Type: Grant
    Filed: September 11, 2018
    Date of Patent: October 8, 2019
    Assignee: NICHIA CORPORATION
    Inventor: Daisuke Kasai
  • Patent number: 10438857
    Abstract: A method of manufacturing a semiconductor device is provided as follows. A fin and an isolation surrounding a lower portion of the fin are formed on a substrate. A plurality of sacrificial gate electrodes is formed on the fin and the isolation. A plurality of recessed upper surfaces of the fin is formed from an upper surface of the fin. An upper surface of the isolation is protected until the plurality of recessed upper surfaces of the fin is formed from the upper surface of the fin. A plurality of source/drains is formed on the plurality of recessed upper surfaces of the fin.
    Type: Grant
    Filed: September 7, 2017
    Date of Patent: October 8, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Hyun Seung Song
  • Patent number: 10424732
    Abstract: A method of fabricating a fin selector with a gated RRAM and the resulting device are disclosed. Embodiments include forming a bottom electrode layer and a hardmask on a semiconductor substrate; etching the hardmask, bottom electrode layer, and semiconductor substrate to form a fin-like structure; forming first and second dummy gate stacks on first and second side surfaces of the fin-like structure, respectively; forming spacers on vertical surfaces of the first and second dummy gate stacks; forming an ILD surrounding the spacers; removing the first and second dummy gate stacks, forming first and second cavities on first and second sides of the fin-like structure; forming an RRAM layer on the first and second side surfaces of the fin-like structure in the first and second cavities, respectively; and filling each of the first and second cavities with a top electrode.
    Type: Grant
    Filed: October 10, 2017
    Date of Patent: September 24, 2019
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Eng Huat Toh, Elgin Quek, Shyue Seng Tan
  • Patent number: 10418308
    Abstract: A system includes a heat sink, a semiconductor device, a layer of thermal interface material (TIM) disposed between the heat sink and the semiconductor device, and a fastener system that couples the semiconductor device, the layer of TIM, and the heat sink together. The TIM may facilitate dissipation of heat generated by the semiconductor device via the heat sink during operation of the semiconductor device. The fastener system includes a first Belleville-type washer configured to cooperate with the TIM, which flows when heated beyond a threshold temperature, to maintain a substantially constant coupling force between the semiconductor device and the heat sink during operation of the semiconductor device.
    Type: Grant
    Filed: January 31, 2017
    Date of Patent: September 17, 2019
    Assignee: Rockwell Automation Technologies, Inc.
    Inventors: Paul Jerome Grosskreuz, Rui Zhou, Kelly James Bronk, Jeremiah John Kopiness
  • Patent number: 10403766
    Abstract: Disclosed is a method of manufacturing flash memory with a vertical cell stack structure. The method includes forming source lines in a cell area of a substrate having an ion-implanted well and forming an alignment mark relative to the source lines. The alignment mark is formed in the substrate outside the cell area of the substrate. After formation of the source lines, cell stacking layers are formed. After forming the cell stacking layers, cell pillars in the cell stacking layers are formed at locations relative to the previously formed source lines using the alignment mark to correctly locate the cell pillars.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: September 3, 2019
    Assignee: Conversant Intellectual Property Management Inc.
    Inventor: Hyoung Seub Rhie
  • Patent number: 10388541
    Abstract: A wafer coating system includes a wafer chuck, a flowing insulating material sprayer and a wafer tilting lifting pin. The wafer chuck has a carrier part and a rotating part, which the carrier part is mounted on the rotating part to carry a wafer, and the rotating part is configured to rotate with a predetermined axis. The flowing insulating material sprayer is above the wafer chuck and configured to spray a flowing insulating material to the wafer, and the wafer tilting lifting pin is configured to form a first acute angle between the wafer and direction of gravity.
    Type: Grant
    Filed: April 13, 2016
    Date of Patent: August 20, 2019
    Assignee: XINTEC INC.
    Inventors: Yu-Tung Chen, Quan-Qun Su, Chuan-Jin Shiu, Chien-Hui Chen, Hsiao-Lan Yeh, Yen-Shih Ho
  • Patent number: 10381349
    Abstract: A semiconductor device comprises a substrate, a first source/drain region on the substrate, a first channel region extending vertically with respect to the substrate from the first source/drain region, a second source/drain region on the first channel region, a third source/drain region on the second source/drain region, a second channel region extending vertically with respect to the substrate from the third source/drain region, a fourth source/drain region on the second channel region, a first gate region formed around from the first channel region, and a second gate region formed around the second channel region.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: August 13, 2019
    Assignee: International Business Machines Corporation
    Inventors: Karthik Balakrishnan, Bahman Hekmatshoartabari, Alexander Reznicek, Jeng-Bang Yau
  • Patent number: 10381398
    Abstract: The present disclosure relates to the field of semiconductor technologies, and discloses a method for manufacturing a semiconductor apparatus. The method includes: forming a water film on a bottom surface of a top wafer and a top surface of a bottom wafer; after the water film is formed, attaching the bottom surface of the top wafer to the top surface of the bottom wafer; disposing the attached top wafer and bottom wafer in a vacuum environment; and performing a thermal annealing process, so that the bottom surface of the top wafer is fusion-bonded to the top surface of the bottom wafer. The disclosed methods can reduce bubble voids existing between the bonded wafers.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: August 13, 2019
    Assignees: SEMICONDUCTOR MANUFACTURING INTL. (SHANGHAI) Corp., SEMICONDUCTOR MANUFACTURING INTL. (BEIJING) Corp.
    Inventors: Linbo Shi, Fucheng Chen
  • Patent number: 10372036
    Abstract: A edge electrode mold according to an embodiment includes a base having a first main surface and one or more protruding structures disposed on the first main surface. The protruding structures include a protrusion projecting from the first main surface of the base, an edge electrode disposed at the protrusion, and an electrolytic hydrophobic film having electrolytic property and hydrophobicity disposed on the upper end surface of a protruding shape including the protrusion and the edge electrode.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: August 6, 2019
    Assignees: Kabushiki Kaisha Toshiba, The University of Tokyo
    Inventors: Yongfang Li, Hiroyuki Fujita
  • Patent number: 10361132
    Abstract: The disclosure relates to semiconductor structures and, more particularly, to structures with thinned dielectric material and methods of manufacture. The method includes depositing a high-k dielectric on a substrate. The method further includes depositing a titanium nitride film directly on the high-k while simultaneously etching the high-k dielectric.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: July 23, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Ruqiang Bao, Takashi Ando, Aritra Dasgupta, Kai Zhao, Unoh Kwon, Siddarth A. Krishnan
  • Patent number: 10361131
    Abstract: A semiconductor device includes a plurality of stacked gate regions spaced apart from each other on a substrate, a plurality of first epitaxial source/drain regions between the plurality of stacked gate regions, wherein the first epitaxial source/drain regions extend from sides of the plurality of stacked gate regions in a first doped region, a plurality of second epitaxial source/drain regions between the plurality of stacked gate regions and positioned over the first epitaxial source/drain regions, wherein the second epitaxial source/drain regions extend from sides of the plurality of stacked gate regions in a second doped region, and a contact region extending through a second epitaxial source/drain region of the plurality of second epitaxial source/drain regions to a first epitaxial source/drain region of the plurality of first epitaxial source/drain regions.
    Type: Grant
    Filed: December 12, 2018
    Date of Patent: July 23, 2019
    Assignee: International Business Machines Corporation
    Inventors: Takashi Ando, Pouya Hashemi, Choonghyun Lee, Alexander Reznicek, Jingyun Zhang
  • Patent number: 10355062
    Abstract: An organic light emitting display is disclosed. In the disclosure, only one switching TFT among TFTs constituting a pixel is implemented as an NMOS type TFT, and at least some of a driving TFT and the remaining switching TFTs are implemented as a PMOS type TFT. Therefore, the disclosure simplifies TFT process steps and provides an organic light emitting display suitable for realizing a high resolution pixel implementation.
    Type: Grant
    Filed: August 16, 2017
    Date of Patent: July 16, 2019
    Assignee: LG Display Co., Ltd.
    Inventor: Jaesung Yu
  • Patent number: 10354707
    Abstract: A seed layer stack with a smooth top surface having a peak to peak film thickness variation of about 0.5 nm is formed by sputter depositing a second seed layer on a first seed layer that is Mg, MgN, or an alloy thereof where the second seed layer has a bond energy substantially greater than that of the first seed layer. The second seed layer may be Ta or NiCr. In some embodiments, an uppermost seed layer that is one or both of Ru and Cu is deposited on the second seed layer. Higher coercivity (Hc) and perpendicular magnetic anisotropy (Hk) is observed in an overlying ferromagnetic layer than when a prior art seed layer stack is employed. The first seed layer has a thickness from 2 to 20 Angstroms and has a resputtering rate about 2 to 40 times that of the second seed layer.
    Type: Grant
    Filed: April 14, 2016
    Date of Patent: July 16, 2019
    Assignee: Headway Technologies, Inc.
    Inventors: Kunliang Zhang, Ruhang Ding, Min Li, Wenyu Chen
  • Patent number: 10347640
    Abstract: The invention provides a manufacturing method of a semiconductor device. First, a substrate is provided. A first recess and a second recess are formed in the substrate, a width of the first recess is smaller than a width of the second recess. Then, a first spin-on dielectric (SOD) layer is formed to fill the first recess and partially fill in the second recess, and then a first processing step is performed to transfer the first SOD layer into a first silicon oxide layer, a silicon nitride layer is subsequently formed on the first silicon oxide layer in the second recess, and then a second spin-on dielectric (SOD) layer is formed on the silicon nitride layer in the second recess, and a second processing step is performed to transfer the second SOD layer into a second silicon oxide layer.
    Type: Grant
    Filed: August 1, 2018
    Date of Patent: July 9, 2019
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Ya-Ying Tsai, Keng-Jen Lin
  • Patent number: 10347749
    Abstract: A first layer of a first material is deposited on a first structure and a second structure, a surface of the first structure being disposed substantially parallelly to a surface of the second structure in at least one direction. A selectively removable material is deposited over the first layer and removed up to a height of a first step. The first material is removed from a portion of the first layer that is exposed from removing the selectively removable material up to the height of the first step. A remainder of the selectively removable material is removed to expose a second portion of the first layer, the second portion of the first layer forming the first step. A second layer of a second material is deposited on the first structure, the second structure, and the second portion of the first layer, causing a formation of a stepped structure.
    Type: Grant
    Filed: March 24, 2017
    Date of Patent: July 9, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Balasubramanian S. Pranatharthiharan, Pietro Montanini, John R. Sporre, Ruilong Xie
  • Patent number: 10347579
    Abstract: Aspects for reducing tip-to-tip distance between end portions of metal lines formed in an interconnect layer of an integrated circuit (IC) are provided. In one aspect, a method includes exposing a photoresist layer disposed over a hardmask layer to a light to form a metal line pattern on the photoresist layer. The metal line pattern includes metal line templates corresponding to tracks substantially parallel to an axis. The sections of the photoresist layer corresponding to the metal line pattern are removed to expose the hardmask layer according to the metal line pattern. The exposed portions of the hardmask layer are etched such that trenches are formed corresponding to the metal line pattern. The hardmask layer is directionally etched such that at least one trench is extended in a first direction along the axis. This allows the trenches to be spaced with a reduced pitch and reduced tip-to-tip distance.
    Type: Grant
    Filed: November 29, 2017
    Date of Patent: July 9, 2019
    Assignee: QUALCOMM Incorporated
    Inventor: Jeffrey Junhao Xu
  • Patent number: 10319838
    Abstract: A method comprises providing a structure defined by a silicon material on a buried oxide layer of a substrate; causing a nucleation of a III-V material in a sidewall of the structure defined by the silicon material; adjusting a growth condition to facilitate a first growth rate of the III-V material in directions along a surface of the sidewall and a second growth rate of the III-V material in a direction laterally from the surface of the sidewall, wherein the second growth rate is less than the first growth rate; and processing the silicon material and the III-V material to form a fin.
    Type: Grant
    Filed: October 7, 2015
    Date of Patent: June 11, 2019
    Assignee: International Business Machines Corporation
    Inventors: Sanghoon Lee, Brent A. Wacaser, Devendra K. Sadana, Effendi Leobandung
  • Patent number: 10319807
    Abstract: A wafer group facilitates securing uniformity of products manufactured from the wafer group whose composition varies among wafers. A technique excludes uncertain factors in forming OF, forming OF with extremely high probability and extremely high accuracy, the wafer group being constituted by a plurality of wafers obtained from the same ingot, with all wafers having an orientation flat (OF), wherein the wafer group is constituted by 70 or more wafers, and in the OF orientation accuracy of the wafer group represented by an angle, the OF orientation accuracy in each wafer is within ±0.010°.
    Type: Grant
    Filed: December 9, 2015
    Date of Patent: June 11, 2019
    Assignee: DOWA ELECTRONICS MATERIALS CO., LTD.
    Inventors: Shinya Shoji, Makoto Ishii, Kazuyuki Umetsu, Junji Sugiura