Abstract: A variable resistance memory device includes a variable resistance layer and a first conductive element and a second conductive element which are spaced apart from each other on the variable resistance layer. The variable resistance layer may include a first layer and a second layer on the first layer. The first layer includes a ternary or more metal oxide containing two or more metal materials having different valences. The second layer may include silicon oxide. The variable resistance memory device may have a wide range of resistance variation due to the metal oxide in which oxygen vacancies are easily formed. The first conductive element and the second conductive element, in response to an applied voltage, may be configured to form a current path in a direction perpendicular to a direction in which the first layer and the second direction are stacked.

Abstract: Provided are a chalcogen compound having ovonic threshold switching characteristics, and a switching device, a semiconductor device, and/or a semiconductor apparatus which include the chalcogen compound. The chalcogen compound includes five or more elements and may have stable switching characteristics with a low off-current value (leakage current value). The chalcogen compound includes: selenium (Se) and tellurium (Te); a first element comprising at least one of indium (In), aluminum (Al), strontium (Sr), and calcium (Ca); and a second element including germanium (Ge) and/or tin (Sn), and may further include at least one of arsenic (As), antimony (Sb), and bismuth (Bi).

Abstract: A semiconductor package and a method of manufacturing a semiconductor package. As a non-limiting example, various aspects of this disclosure provide a semiconductor package, and method of manufacturing thereof, that comprises shielding on multiple sides thereof.

Abstract: What disclosed are structures and methods for repairing emissive display systems. Various repairing techniques embodiments in accordance with the structures and methods are provided to conquer and mitigate the defected pixels and to increase the yield and reduce the cost of emissive displays systems.

Abstract: An electronic device includes a multilevel lamination structure having a core layer, dielectric layers and conductive features formed in metal layers on or between respective ones or pairs of the dielectric layers. The core layer and the dielectric layers extend in respective planes of orthogonal first and second directions and are stacked along an orthogonal third direction. The conductive features include a first patterned conductive feature having multiple conductive turns in each of a first pair of the metal layers to form a first winding having a first turn and a final turn adjacent to one another in the same metal layer of the first pair, and a second patterned conductive feature having multiple conductive turns in a second pair of the metal layers to form a second winding having a first turn and a final turn.

Abstract: A method of improving electrical interconnections between two electrical elements is made available by providing a meta-material overlay in conjunction with the electrical interconnection. The meta-material overlay is designed to make the electrical signal propagating via the electrical interconnection to act as though the permittivity and permeability of the dielectric medium within which the electrical interconnection is formed are different than the real component permittivity and permeability of the dielectric medium surrounding the electrical interconnection. In some instances the permittivity and permeability resulting from the meta-material cause the signal to propagate as if the permittivity and permeability have negative values. Accordingly the method provides for electrical interconnections possessing enhanced control and stability of impedance, reduced noise, and reduced loss.

Abstract: In one embodiment, a method of manufacturing a semiconductor device includes forming a first layer including a metal element on a substrate, and processing the first layer by dry etching. The method further includes removing a second layer formed on a lateral face of the first layer by wet etching, after processing the first layer, and forming a first film on the lateral face of the first layer by processing the lateral face of the first layer with a liquid, after removing the second layer. Furthermore, the substrate is not exposed to ambient air, after removing the second layer and before forming the first film.

Abstract: The present disclosure relates to a semiconductor structure. The semiconductor structure includes a dielectric layer having a first dielectric surface and a second dielectric surface opposite to the first dielectric surface. The dielectric layer defines a recess in the first dielectric surface, and the recess includes a sidewall of the dielectric layer. A first conductive layer contacts a bottom surface of the dielectric layer. The sidewall of the dielectric layer is directly over the first conductive layer. A second conductive layer contacts the first conductive layer and the dielectric layer. The second conductive layer vertically extends from the first conductive layer to above the dielectric layer. A third conductive layer contacts the second conductive layer. The third conductive layer is laterally separated from a sidewall of the second conductive layer that faces the third conductive layer by a non-zero distance.

Abstract: A microelectronic assembly having a first side and a second side opposite therefrom is disclosed. The microelectronic assembly may include a microelectronic element having a first face, a second face opposite the first face, a plurality of sidewalls each extending between the first and second faces, and a plurality of element contacts. The microelectronic assembly may also include an encapsulation adjacent the sidewalls of the microelectronic element. The microelectronic assembly may include electrically conductive connector elements each having a first end, a second end remote from the first end, and an edge surface extending between the first and second ends, wherein one of the first end or the second end of each connector element is adjacent the first side of the package. The microelectronic assembly may include a redistribution structure having terminals, the redistribution structure adjacent the second side of the package, the terminals being electrically coupled with the connector elements.

Abstract: A method for fabricating a semiconductor device having a substantially undoped channel region includes forming a plurality of fins extending from a substrate. In various embodiments, each of the plurality of fins includes a portion of a substrate, a portion of a first epitaxial layer on the portion of the substrate, and a portion of a second epitaxial layer on the portion of the first epitaxial layer. The portion of the first epitaxial layer of each of the plurality of fins is oxidized, and a liner layer is formed over each of the plurality of fins. Recessed isolation regions are then formed adjacent to the liner layer. The liner layer may then be etched to expose a residual material portion (e.g., Ge residue) adjacent to a bottom surface of the portion of the second epitaxial layer of each of the plurality of fins, and the residual material portion is removed.

Abstract: A certain embodiment includes: first wiring layers extended in a first direction and arranged in a second direction; second wiring layers provided above the first wiring layer of a third direction and arranged in the first direction and extended in the second direction; first stacked structures comprising a first memory cell disposed between the second and first wiring layers at a crossing portion between the second and first wiring layers; first conductive layers provided in the same layer as the first wiring layers, adjacent to the first wiring layer in the second direction, and not connected to other than the second wiring layer; second stacked structures disposed at crossing portions between the second wiring layers and the first conductive layers; and an insulation layer provided between the first stacked structures and between the second stacked structures having a Young's modulus larger than that of the insulation layer.

Abstract: The present disclosure relates to an integrated circuit. The integrated circuit has a plurality of bit-line stacks disposed over a substrate and respectively including a plurality of bit-lines stacked onto one another. A data storage structure is over the plurality of bit-line stacks and a selector is over the data storage structure. A word-line is over the selector. The selector is configured to selectively allow current to pass between the plurality of bit-lines and the word-line. The plurality of bit-line stacks include a first bit-line stack, a second bit-line stack, and a third bit-line stack. The first and third bit-line stacks are closest bit-line stacks to opposing sides of the second bit-line stack. The second bit-line stack is separated from the first bit-line stack by a first distance and is further separated from the third bit-line stack by a second distance larger than the first distance.

Abstract: A method of fabrication of a multi-gate semiconductor device that includes providing a fin having a plurality of a first type of epitaxial layers and a plurality of a second type of epitaxial layers. The plurality of the second type of epitaxial layers is oxidized in the source/drain region. A first portion of a first layer of the second type of epitaxial layers is removed in a channel region of the fin to form an opening between a first layer of the first type of epitaxial layer and a second layer of the first type of epitaxial layer. A portion of a gate structure is then formed in the opening.

Abstract: A memory cell includes a memory device, a connecting structure, an insulating layer and a selector. The connecting structure is disposed on and electrically connected to the memory device. The insulating layer covers the memory device and the connecting structure. The selector is located on and electrically connected to the memory device, where the selector is disposed on the insulating layer and connected to the connecting structure by penetrating through the insulating layer.

Abstract: In an embodiment, a method includes: forming a fin extending from a substrate, the fin having a first width and a first height after the forming; forming a dummy gate stack over a channel region of the fin; growing an epitaxial source/drain in the fin adjacent the channel region; and after growing the epitaxial source/drain, replacing the dummy gate stack with a metal gate stack, the channel region of the fin having the first width and the first height before the replacing, the channel region of the fin having a second width and a second height after the replacing, the second width being less than the first width, the second height being less than the first height.

Abstract: A method of manufacturing a storage device for storing information, apparatus for storing information, an optical memristor device and a memory cell are disclosed. A method comprises providing at least one first electrode and at least one further electrode and providing each of at least one region of a first material between, and in electrical connection with, a respective first electrode and a further electrode whereby said step of providing at least one region comprises providing in the first material, a plurality of changeable particles that have charge storage capacity and at least one electrical property that is reversibly changeable responsive to absorption of incident electromagnetic radiation.

Abstract: A memory device, a memory integrated circuit and a manufacturing method of the memory device are provided. The memory device includes a composite bottom electrode, a top electrode and a resistance variable layer disposed between the composite bottom electrode and the top electrode. The composite bottom electrode includes a first bottom electrode and a second bottom electrode disposed over the first bottom electrode. A sidewall of the second bottom electrode is laterally recessed from sidewalls of the first bottom electrode layer and the resistance variable layer.

Abstract: A method of forming the semiconductor device is provided. The method includes following steps. A memory structure is formed over a first conductive line over a substrate and is electrically connected to the first conductive line. A sacrificial layer is formed on the memory structure. A spacer layer is formed to cover the memory structure and the sacrificial layer. A first dielectric layer is formed to cover the spacer layer. A planarization process is performed to remove a portion of the first dielectric layer. A second dielectric layer is formed on the spacer layer and the first dielectric layer. A patterning process is performed to form an opening exposing a portion of the top surface of the sacrificial layer. The sacrificial layer is removed to form a recess. A second conductive line is formed in the opening and the recess to be electrically coupled to the memory structure.

Abstract: Methods for depositing a molybdenum metal film over a dielectric surface of a substrate by a cyclical deposition process are disclosed. The methods may include: providing a substrate comprising a dielectric surface into a reaction chamber; depositing a nucleation film directly on the dielectric surface; and depositing a molybdenum metal film directly on the nucleation film, wherein depositing the molybdenum metal film includes: contacting the substrate with a first vapor phase reactant comprising a molybdenum halide precursor; and contacting the substrate with a second vapor phase reactant comprising a reducing agent precursor. Semiconductor device structures including a molybdenum metal film disposed over a surface of a dielectric material with an intermediate nucleation film are also disclosed.

Abstract: A variable resistance memory device includes memory cell structures on a substrate and spaced apart from each other in first and second directions, the first and second directions being parallel to a top surface of the substrate and intersecting each other, and a dummy cell structure surrounding each of the memory cell structures, as viewed in a plan view, the dummy cell structure being a single body structure extending continuously between all the memory cell structures, wherein each of the memory cell structures includes first conductive line on and intersecting second conductive lines, and memory cells between the first and second conductive lines, and wherein the dummy cell structure includes first dummy conductive lines on and intersecting second dummy conductive lines, and dummy memory cells between the first and second dummy conductive lines.