Abstract: Disclosed herein are selector devices and related devices and techniques. For example, in some embodiments, a selector device may include a first electrode, a second electrode, and a selector material stack between the first electrode and the second electrode. The selector material stack may include a dielectric material layer between a first conductive material layer and a second conductive material layer. A first material layer may be present between the first electrode and the first conductive material layer, and a second material layer may be present between the first conductive material layer and the dielectric layer. The first material layer and the second material layer may be diffusion barriers, and the second material layer may be a weaker diffusion barrier than the first material layer.

Abstract: Structures for a resistive memory element and methods of forming a structure for a resistive memory element. The resistive memory element includes a first switching layer, a second switching layer, a conductive spacer, a first electrode, and a second electrode. The first switching layer includes a portion positioned between the first electrode and the conductive spacer, the second switching layer includes a portion positioned between the second electrode and the conductive spacer, and the conductive spacer is positioned between the portion of the first switching layer and the portion of the second switching layer.

Abstract: A multi-gate semiconductor device having a fin element, a gate structure over the fin element, an epitaxial source/drain feature adjacent the fin element; a dielectric spacer interposing the gate structure and the epitaxial source/drain feature.

Abstract: A deposition mask includes: a plurality of sub-masks through which deposition material passes to a base layer to form a deposition layer defining a hole therein, each of the sub-masks including: an aperture through which the deposition material passes to the base layer, a total planar area of the aperture corresponding to less than a total planar area of the deposition layer, and a masking surface at which the deposition material does not pass through the sub-mask, the masking surface including a hole-forming portion of which a total planar area thereof corresponds to a total planar area of the hole defined in the deposition layer. The hole-forming portions of the sub-masks have a same shape and planar area as each other, and within each sub-mask, the shape of the hole-forming portion is nested within a shape of the aperture.

Abstract: A method for fabricating a semiconductor device having a substantially undoped channel region includes forming a plurality of fins extending from a substrate. In various embodiments, each of the plurality of fins includes a portion of a substrate, a portion of a first epitaxial layer on the portion of the substrate, and a portion of a second epitaxial layer on the portion of the first epitaxial layer. The portion of the first epitaxial layer of each of the plurality of fins is oxidized, and a liner layer is formed over each of the plurality of fins. Recessed isolation regions are then formed adjacent to the liner layer. The liner layer may then be etched to expose a residual material portion (e.g., Ge residue) adjacent to a bottom surface of the portion of the second epitaxial layer of each of the plurality of fins, and the residual material portion is removed.

Abstract: In an embodiment, a method includes: forming a fin extending from a substrate, the fin having a first width and a first height after the forming; forming a dummy gate stack over a channel region of the fin; growing an epitaxial source/drain in the fin adjacent the channel region; and after growing the epitaxial source/drain, replacing the dummy gate stack with a metal gate stack, the channel region of the fin having the first width and the first height before the replacing, the channel region of the fin having a second width and a second height after the replacing, the second width being less than the first width, the second height being less than the first height.

Abstract: The present disclosure generally relates to memory devices and methods of forming the same. More particularly, the present disclosure relates to resistive random-access (ReRAM) memory devices. The present disclosure provides a memory device including a dielectric layer having an opening, sidewalls along the opening, a first electrode in the opening, a resistive layer disposed upon the first electrode, an oxygen scavenging layer disposed upon the resistive layer, and a second electrode in contact with the oxygen scavenging layer. The oxygen scavenging layer includes a material that is different from the resistive layer and partially covers the resistive layer. The first electrode is electrically linked to the second electrode by the oxygen scavenging layer and the resistive layer.

Abstract: The present disclosure relates to an integrated circuit. The integrated circuit includes a plurality of interconnects within a dielectric structure over a substrate. A passivation structure is arranged over the dielectric structure. The passivation structure has sidewalls connected to one or more upper surfaces of the passivation structure. A bond pad is arranged directly between the sidewalls of the passivation structure. An upper passivation layer is disposed over the passivation structure and the bond pad. The upper passivation layer extends from over an upper surface of the bond pad to within a recess in the upper surface of the bond pad.

Abstract: The present disclosure provides a display panel and a manufacturing method for the display panel. The display panel includes a substrate, a switch assembly disposed on the substrate, and a light-sensing assembly disposed on a side of the switch assembly. The switch assembly comprises an indium gallium zinc oxide (IGZO) layer.

Abstract: A system and method for manufacturing a lattice structure of ionized particles on a substrate, wherein the process may be improved by controlling the number of ionized particles that are ejected from an ionizer and directed to a substrate, and wherein the ionized particles are disposed on the substrate, thereby enabling the creation of a lattice structure that may be as thin as a single layer of ionized particles.

Abstract: A semiconductor body is disclosed. In an embodiment a semiconductor body includes an n-doped region comprising a first layer sequence comprising pairs of alternating layers, wherein a first layer and a second layer of each pair differ in their doping concentration, and wherein the first and second layers of each pair have the same material composition except for their doping and a second layer sequence comprising pairs of alternating layers, wherein a first layer and a second layer of each pair differ in their material composition, an active region, wherein the second layer sequence is disposed between the first layer sequence and the active region and a p-doped region, wherein the active region is disposed between the n-doped region and the p-doped region.

Abstract: Provided are a resistive random access memory and a manufacturing method thereof. The resistive random access memory includes first, second, and third electrodes, a variable resistance layer, a selection layer, and first and second bit lines. The second electrode and the third electrode are on the first electrode. The second and third electrodes are separated from each other and overlapped with the sidewall and the top surface of the first electrode. The variable resistance layer is between the first and second electrodes and between the first and third electrodes. The selection layer is between the variable resistance layer and the first electrode. The first bit line is on the second electrode and electrically connected to the second electrode via a first contact. The second bit line is on the third electrode and electrically connected to the third electrode via a second contact.

Abstract: What disclosed are structures and methods for repairing emissive display systems. Various repairing techniques embodiments in accordance with the structures and methods are provided to conquer and mitigate the defected pixels and to increase the yield and reduce the cost of emissive displays systems.

Abstract: A semiconductor structure includes: a base substrate; two first fin structures formed on the base substrate; an isolation structure formed on the base substrate, wherein a top surface of the isolation structure is lower than top surfaces of the two first fin structures, the isolation structure covers a portion of sidewall surfaces of the two first fin structures, the isolation structure includes a first region, located between the two first fin structures, and two second regions, and the top surface of the isolation structure formed in the first region adjacent to the two first fin structures is higher than the top surface of the isolation structure formed in the two second regions; and a plurality of source/drain openings formed in the first fin structures and having a bottom surface lower than the top surface of the isolation structure formed in the two second regions.

Abstract: Methods for depositing a molybdenum metal film over a dielectric surface of a substrate by a cyclical deposition process are disclosed. The methods may include: providing a substrate comprising a dielectric surface into a reaction chamber; depositing a nucleation film directly on the dielectric surface; and depositing a molybdenum metal film directly on the nucleation film, wherein depositing the molybdenum metal film includes: contacting the substrate with a first vapor phase reactant comprising a molybdenum halide precursor; and contacting the substrate with a second vapor phase reactant comprising a reducing agent precursor. Semiconductor device structures including a molybdenum metal film disposed over a surface of a dielectric material with an intermediate nucleation film are also disclosed.

Abstract: The present disclosure provides a method that includes providing a semiconductor substrate having a first region and a second region; forming a first gate within the first region and a second gate within the second region on the semiconductor substrate; forming first source/drain features of a first semiconductor material with an n-type dopant in the semiconductor substrate within the first region; forming second source/drain features of a second semiconductor material with a p-type dopant in the semiconductor substrate within the second region. The second semiconductor material is different from the first semiconductor material in composition. The method further includes forming first silicide features to the first source/drain features and second silicide features to the second source/drain features; and performing an ion implantation process of a species to both the first and second regions, thereby introducing the species to first silicide features and the second source/drain features.

Abstract: By controlling the optical thickness of the upper stacked structure disposed on the display panel, it is possible to periodically control the tristimulus value of Xr and the tristimulus value of Yg emitted from the electronic device. The optical thickness is determined by the thickness and refractive index of the upper stacked structure. This control may reduce the tristimulus value of Xr periodically or increase the tristimulus value of Yg periodically. The tristimulus value of Xr may be periodically decreased and the tristimulus value of Yg may be periodically increased at the same time.

Abstract: Imaging apparatus (2000, 2100, 2200) includes a photosensitive medium (2004, 2204) and an array of pixel circuits (302), which are arranged in a regular grid on a semiconductor substrate (2002) and define respective pixels (2006, 2106) of the apparatus. Pixel electrodes (2012, 2112, 2212) are connected respectively to the pixel circuits in the array and coupled to read out photocharge from respective areas of the photosensitive medium to the pixel circuits. The pixel electrodes in a peripheral region of the array are spatially offset, relative to the regular grid, in respective directions away from a center of the array.

Abstract: A semiconductor device comprises a substrate, a first source/drain region on the substrate, a first channel region extending vertically with respect to the substrate from the first source/drain region, a second source/drain region on the first channel region, a third source/drain region on the second source/drain region, a second channel region extending vertically with respect to the substrate from the third source/drain region, a fourth source/drain region on the second channel region, a first gate region formed around from the first channel region, and a second gate region formed around the second channel region.

Abstract: A resistive random access memory (RRAM) structure includes a resistive memory element formed on a semiconductor substrate. The resistive element includes a top electrode, a bottom electrode, and a resistive material layer positioned between the top electrode and the bottom electrode. The RRAM structure further includes a field effect transistor (FET) formed on the semiconductor substrate, the FET having a source and a drain. The drain has a zero-tilt doping profile and the source has a tilted doping profile. The resistive memory element is coupled with the drain via a portion of an interconnect structure.