Patents Examined by Marwan Ayash
  • Patent number: 10564871
    Abstract: A memory system has a first memory to store first-granularity data having a granularity smaller than second-granularity data, the first memory having a memory capacity smaller than a memory capacity of a second memory storing the second-granularity data, a controller to read third-granularity data having a granularity equal to or greater than the first-granularity from the data stored in the second memory, and a data extractor to extract the first-granularity data from the third-granularity data read by the controller and to store the extracted data in the first memory.
    Type: Grant
    Filed: March 8, 2017
    Date of Patent: February 18, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Susumu Takeda, Shinobu Fujita
  • Patent number: 10545834
    Abstract: Techniques for archiving data over a local area network, including methods, systems, that apparatus that include machine-readable media for storing executable instructions. In some implementations, an apparatus includes a touch screen, one or more processors, a battery, non-volatile data storage device, and machine-readable media including executable instructions for performing data archiving operations. Communication with a network device connected to a local area network is established. Configuration data is obtained from the network device. The configuration data identifies one or more source devices connected to the network device over a local area network, and characteristics of the one or more source devices. A set of backup parameters are determined. An instruction is generated. The instruction specifies one or more archiving operations that, when received by the network device, cause the network device to extract data from the one or more source devices over the local area network.
    Type: Grant
    Filed: March 2, 2018
    Date of Patent: January 28, 2020
    Inventor: June B. Smith
  • Patent number: 10529374
    Abstract: A shingled magnetic recording (SMR) hard disk drive (HDD) receives a read command for data associated with a range of logical block addresses (LBAs). In situations where a first portion of valid data associated with the range of LBAs is stored in an SMR region of the HDD and a second portion of valid data associated with the range of LBAs is stored in a non-SMR region of the HDD, the first portion is read from the SMR region in a single disk access and copied to a first buffer of the HDD, and the second portion is read from the non-SMR region in one or more disk accesses and copied to a second buffer of the HDD. The valid data associated with the range of LBAs stored in the second buffer are copied to the first buffer to be combined with valid data associated with the range of LBAs stored in the first buffer, and the combined valid data is then transferred to the host to complete execution of the read command.
    Type: Grant
    Filed: March 7, 2017
    Date of Patent: January 7, 2020
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventor: Andre C. Hall
  • Patent number: 10503642
    Abstract: A data processing method includes allocating a tag entry in a tag array for a data block; allocating a data entry in a data array for the data block when the data block is actively shared; and de-allocating the data entry when the data block is temporarily private or gets evicted in the data array.
    Type: Grant
    Filed: August 25, 2017
    Date of Patent: December 10, 2019
    Assignees: Huawei Technologies Co., Ltd., National University of Singapore
    Inventors: Yuan Yao, Tulika Mitra, Zhiguo Ge, Naxin Zhang
  • Patent number: 10481822
    Abstract: A system includes one or more memory devices storing instructions, and one or more processors configured to execute the instructions to perform steps of a method for providing customer data access during a migration process. The system may initiate a transfer of customer data from a source data server to a system platform and transfer a subset of the customer data to a temporary data storage. The system may modify the temporary copy of customer data and generate an instruction to modify the permanent copy of customer data. In response to the completion of the transfer of customer data from the source data server to the system mainframe, the system may then transfer and execute the instruction to modify the permanent copy of customer data.
    Type: Grant
    Filed: July 31, 2017
    Date of Patent: November 19, 2019
    Assignee: CAPITAL ONE SERVICES, LLC
    Inventors: Faizan Ahmad, Shahnawaz Ali
  • Patent number: 10430328
    Abstract: Systems and methods for configuring, controlling and operating a non-volatile cache are disclosed. A host system may poll a memory system as to the memory system's configuration of its non-volatile cache. Further, the host system may configure the non-volatile cache on the memory system, such as the size of the non-volatile cache and the type of programming for the non-volatile cache (e.g., whether the non-volatile cache is programmed according to SLC or the type of TRIM used to program cells in the non-volatile cache). Moreover, responsive to a command from the host to size the non-volatile cache, the memory system may over or under provision the cache. Further, the host may control operation of the non-volatile cache, such as by sending selective flush commands.
    Type: Grant
    Filed: September 16, 2014
    Date of Patent: October 1, 2019
    Assignee: SanDisk Technologies LLC
    Inventors: Rotem Sela, Miki Sapir, Amir Shaharabany, Hadas Oshinsky, Rafi Abraham, Elad Baram
  • Patent number: 10423536
    Abstract: A memory system has a first memory to be accessed per first data size, a second memory to be accessed per second data size smaller than the first data size, the second memory being accessible at a higher speed than the first memory; and a third memory to store address conversion information that converts an address for accessing the second memory into an address for accessing the first memory. The first and third memories are non-volatile memories.
    Type: Grant
    Filed: March 10, 2017
    Date of Patent: September 24, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Hiroki Noguchi, Shinobu Fujita
  • Patent number: 10365842
    Abstract: Systems and methods for reducing problems and disadvantages associated with power consumption in memory devices are disclosed. In accordance with one embodiment of the present disclosure, a method for improving performance and reducing power consumption in memory may include tracking whether individual units of a memory system are active or inactive. The method may also include placing inactive individual units of the memory system in a self-refresh mode, such that the inactive individual units self-refresh their contents. The method may further include placing active individual units of the memory system in a command-based refresh mode, such that the active individual units are refreshed in response to a received command to refresh their contents.
    Type: Grant
    Filed: August 12, 2016
    Date of Patent: July 30, 2019
    Assignee: DELL PRODUCTS L.P.
    Inventors: William Sauber, Stuart Allen Berke
  • Patent number: 10360151
    Abstract: A cache memory system has a first cache memory, a second cache memory which comprises a nonvolatile memory capable of generating a plurality of regions having different access speeds and has access priority lower than the first cache memory, and a cache controller which carries out a control where data to be stored in the second cache memory is sorted to the plurality of regions and stored thereto in accordance with access conditions with respect to the first cache memory.
    Type: Grant
    Filed: September 12, 2016
    Date of Patent: July 23, 2019
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroki Noguchi, Shinobu Fujita
  • Patent number: 10296357
    Abstract: A terminal device according to the present application includes an acceptance unit, a detection unit, and a storage unit. The acceptance unit accepts a specifying operation for specifying a piece of content related to a first application. The detection unit detects a predetermined executing operation after the acceptance unit accepts the specifying operation. Upon detection of the executing operation by the detection unit, the storage unit stores the piece of content specified by the specifying operation in a storage region used by a second application.
    Type: Grant
    Filed: September 16, 2014
    Date of Patent: May 21, 2019
    Assignee: YAHOO JAPAN CORPORATION
    Inventors: Koichi Sawada, Ayaka Hirano, Shinya Kato
  • Patent number: 10248511
    Abstract: A primary storage system is equipped with a local storage subsystem having a mirror volume of a volume in a primary storage subsystem, and a remote storage subsystem having a mirror volume of the volume in the primary storage subsystem at a secondary site. When storing a write data from a host to a volume, the primary storage subsystem determines an SEQ# to be stored in a journal corresponding to the write request, creates a journal including the relevant SEQ# and a replica of the write data, and transmits the relevant SEQ# to the local storage subsystem, which creates a journal including the relevant SEQ# and stores it in its own journal volume. But when creation of the journal including the relevant SEQ# is stopped, the local storage subsystem creates a dummy journal including the relevant SEQ# but not including the write data.
    Type: Grant
    Filed: November 26, 2014
    Date of Patent: April 2, 2019
    Assignee: Hitachi, Ltd.
    Inventors: Ryunosuke Kamimoto, Hideo Saito, Azusa Jin, Keishi Tamura, Takahiko Takeda, Takashi Sakaguchi, Hiroyuki Morimoto
  • Patent number: 10236032
    Abstract: A mass data storage system, which comprises: a controller for issuing and receiving signals to carry out memory operations; a motherboard comprising at least one first connector and providing signal pathways for establish a ring from the controller via each of the at least one first connector and back to the controller; and at least one non-volatile memory module comprising a second connector electrically connected to a chain of non-volatile memory devices, wherein mating of the second connector with a given one of the at least one first connector causes the chain of non-volatile memory devices to be inserted into the ring, thereby to allow the controller to carry out the memory operations on the non-volatile memory devices in the chain.
    Type: Grant
    Filed: September 18, 2008
    Date of Patent: March 19, 2019
    Assignee: Novachips Canada Inc.
    Inventors: HakJune Oh, Jin-Ki Kim
  • Patent number: 10235145
    Abstract: In one aspect, a method includes intercepting write I/Os going to a volume on a storage array and sending the write I/Os to targets on a plurality of source-side data protection appliances based on a load balancing scheme. In another aspect, an article includes a non-transitory machine-readable medium that stores executable instructions. The instructions cause a machine to intercept write I/Os going to a volume on a storage array and send the write I/Os to targets on a plurality of source-side data protection appliances based on a load balancing scheme. In a further aspect, an apparatus includes circuitry configured to intercept write I/Os going to a volume on a storage array and send the write I/Os to targets on a plurality of source-side data protection appliances based on a load balancing scheme.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: March 19, 2019
    Assignee: EMC International Company
    Inventors: Assaf Natanzon, Lev Ayzenberg
  • Patent number: 10223291
    Abstract: A computing device comprises: a memory; a processor; an interpreter; and a Memory Management Unit. The interpreter is for controlling the processor to execute a program comprising at least one first instruction in a format that is not native to the processor and at least one second instruction in machine code that is native to the processor. The Memory Management Unit is adapted to control access by the processor to the memory and possibly also to peripherals when the at least one second instruction is executed.
    Type: Grant
    Filed: May 15, 2010
    Date of Patent: March 5, 2019
    Assignee: NXP B.V.
    Inventors: Ernst Haselsteiner, Christian Kirchstaetter
  • Patent number: 10210100
    Abstract: A system and method are disclosed for an event lock storage device. The storage device includes a user partition and an event partition (which may be associated with an event). The storage device receives data from a host device, and stores the data in the user partition. In response to receiving an indication of an event, the storage device may designate the data as part of the event partition. The event partition may include a set of access rules that is different from the user partition, such as more restrictive rules for modification or deletion of a file containing the data.
    Type: Grant
    Filed: April 14, 2015
    Date of Patent: February 19, 2019
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Filip Verhaeghe, Bsa Chung, Samuel Yu, Michael Lavrentiev
  • Patent number: 10200472
    Abstract: Generally, this disclosure provides systems, devices, methods and computer readable media for improved coordination between sender and receiver nodes in a one-sided memory access to a PGAS in a distributed computing environment. The system may include a transceiver module configured to receive a message over a network, the message comprising a data portion and a data size indicator and an offset handler module configured to calculate a destination address from a base address of a memory buffer and an offset counter. The transceiver module may further be configured to write the data portion to the memory buffer at the destination address; and the offset handler module may further be configured to update the offset counter based on the data size indicator.
    Type: Grant
    Filed: December 24, 2014
    Date of Patent: February 5, 2019
    Assignee: Intel Corporation
    Inventors: Mario Flajslik, James Dinan
  • Patent number: 10191775
    Abstract: The present invention discloses a method for optimizing the throughput of hardware accelerators (HWAs) in a computerized abstraction system, by utilizing the maximal data input bandwidth to the said HWAs. The method is comprised of the following steps: dynamically obtaining the quantities and properties of HWAs and storage units within the computerized abstraction system dynamically allocating cache memory space per each of the HWAs, according to the said obtained quantities and properties, to minimize the time required for reading data from storage instances to the said HWA dynamically allocating spoolers per each of the HWAs, according to the said obtained quantities and properties, to buffer the input data and ensure a continuous flow of input data, in the target HWA's maximal input bandwidth.
    Type: Grant
    Filed: December 20, 2016
    Date of Patent: January 29, 2019
    Assignee: SQREAM TECHNOLOGIES LTD.
    Inventors: Ori Brostovsky, Omid Vahdaty, Eli Klatis, Tal Zelig, Jake Wheat, Razi Shoshani
  • Patent number: 10157002
    Abstract: A method begins by a processing module determining a priority access level of an encoded data slice stored on a memory device. The method continues with the processing module determining an end-of-life memory level for the memory device. The method continues with the processing module determining whether to migrate the encoded data slice from the memory device based on the priority access level and the end-of-life memory level. The method continues with the processing module identifying another memory device. The method continues with the processing module facilitating migration of the encoded data slice to another memory device.
    Type: Grant
    Filed: August 5, 2011
    Date of Patent: December 18, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Gary W. Grube, Jason K. Resch, Timothy W. Markison, Ilya Volvovski, Manish Motwani
  • Patent number: 10114562
    Abstract: In a multi-plane non-volatile memory, good blocks of different planes are linked for parallel operation for storing long host writes. Where bad blocks in one or more planes result in unlinked blocks, the unlinked blocks are configured for individual operation to store short host writes and/or memory system management data. Unlinked blocks may be configured as Single Level Cell (SLC) blocks while linked blocks may be configured as SLC blocks or Multi Level Cell (MLC) blocks.
    Type: Grant
    Filed: September 16, 2014
    Date of Patent: October 30, 2018
    Assignee: SanDisk Technologies LLC
    Inventors: Narendhiran Chinnaanangur Ravimohan, Muralitharan Jayaraman, Abhijeet Manohar, Alan Bennett
  • Patent number: 10108507
    Abstract: A method, system, and computer program product for receiving a request to roll an image to a point in time by reading data from a journal, applying data from the journal to create a asynchronous copy on write image at the requested point in time, creating a virtual image data structure, and allowing writes to be cached in a journal based replication appliance.
    Type: Grant
    Filed: March 31, 2011
    Date of Patent: October 23, 2018
    Assignee: EMC IP Holding Company
    Inventor: Assaf Natanzon