Patents Examined by Marwan Ayash
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Patent number: 11073993Abstract: A method begins by a processing module determining a priority access level of an encoded data slice stored on a memory device. The method continues by determining a memory status for the memory device, wherein the memory status includes a plurality of discrete usability levels with a highest usability level representing a maximum amount of usable memory, a second usability level representing a lower usability level than the highest usability level and a lowest usability level representing an unusable level when the usable memory is below a threshold. The method continues with the processing module determining whether to migrate the encoded data slice from the memory device based on the priority access level and the memory status. The method continues with the processing module identifying another memory device. The method continues with the processing module facilitating migration of the encoded data slice to another memory device.Type: GrantFiled: May 28, 2020Date of Patent: July 27, 2021Assignee: PURE STORAGE, INC.Inventors: Gary W. Grube, Jason K. Resch, Timothy W. Markison, Ilya Volvovski, Manish Motwani
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Patent number: 11030118Abstract: In a memory module, encryption information is received from an external source and stored exclusively within a non-persistent storage element such that the encryption information is expunged from the memory module upon power loss. Write data is received and encrypted using the encryption information stored within the non-persistent storage element to produce encrypted data which is stored, in turn, within a nonvolatile storage of the memory module.Type: GrantFiled: December 20, 2017Date of Patent: June 8, 2021Assignee: Rambus Inc.Inventors: Aws Shallal, Larry Grant Giddens, Sarvagya Kochak
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Patent number: 10990523Abstract: A memory controller configured to control a memory device including a plurality of banks. The memory controller may determine whether a number of write commands enqueued in a command queue of the memory controller exceeds a reference value, calculate a level of write power to be consumed by the memory device in response to at least some of the write commands from among the enqueued write commands when the number of enqueued write commands exceeds the reference value, and schedule, based on the calculated level of write power, interleaving commands executing an interleaving operation of the memory device, from among the enqueued write commands.Type: GrantFiled: June 18, 2019Date of Patent: April 27, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jeong-ho Lee, Young-sik Kim, Eun-chu Oh, Young-kwang Yoo, Young-geun Lee
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Patent number: 10963386Abstract: Provided are a computer program product, system, and method for determining tracks to prestage into cache from a storage. Information is provided related to determining tracks to prestage from the storage to the cache in a stage group of sequential tracks including a trigger track comprising a track number in the stage group at which to start prestaging tracks and Input/Output (I/O) activity information to a machine learning module. A new trigger track in the stage group at which to start prestaging tracks is received from the machine learning module having processed the provided information. The trigger track is set to the new trigger track. Tracks are prestaged in response to processing an access request to the trigger track in the stage group.Type: GrantFiled: September 28, 2018Date of Patent: March 30, 2021Assignee: International Business Machines CorporationInventors: Lokesh M. Gupta, Kyler A. Anderson, Matthew G. Borlick, Kevin J. Ash
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Patent number: 10963394Abstract: A controller of a data storage device includes: a host interface providing an interface to a host computer; a flash translation layer (FTL) translating a logical block address (LBA) to a physical block address (PBA) associated with an input/output (I/O) request; a flash interface providing an interface to flash media to access data stored on the flash media; and one or more deep neural network (DNN) modules for predicting an I/O access pattern of the host computer. The one or more DNN modules provide one or more prediction outputs to the FTL that are associated with one or more past I/O requests and a current I/O request received from the host computer, and the one or more prediction outputs include at least one predicted I/O request following the current I/O request. The FTL prefetches data stored in the flash media that is associated with the at least one predicted I/O request.Type: GrantFiled: June 19, 2018Date of Patent: March 30, 2021Inventors: Ramdas P. Kachare, Sompong Paul Olarig, Vikas Sinha, Zvika Guz
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Patent number: 10942856Abstract: A system, apparatus and method for secure functions and manipulating cache line data. The method includes generating cache block addresses from a subset of bits, i.e. tag bits, of a cache address and hashing the cache block addresses with one or more secure functions that use keys to generate secure indexes.Type: GrantFiled: April 26, 2019Date of Patent: March 9, 2021Assignee: Arm LimitedInventors: Andreas Lars Sandberg, Prakash S. Ramrakhyani
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Patent number: 10921991Abstract: Notice of migration of a portion of a data volume from a first location to a second location is received by a first computer system from a second computer system, where the data volume is separated over a network from the first computer system. A third computer system, separated over a network from the first computer system, is caused to invalidate a mapping between the portion and the first location. An indication that the third computer system seeks access to the portion is identified. A third computer system is enabled, by providing a mapping between the portion and the second location, to access portion at the second location.Type: GrantFiled: December 20, 2016Date of Patent: February 16, 2021Assignee: Amazon Technologies, Inc.Inventors: Marc Stephen Olson, Christopher Magee Greenwood, Anthony Nicholas Liguori, James Michael Thompson, Surya Prakash Dhoolam, Marc John Brooker, Danny Wei
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Patent number: 10908818Abstract: According to some embodiment, a backup storage system receives a request from a client to read a data segment associated with a file object stored in a storage system. In response to the request, the system performs a lookup operation in a first index stored in a memory to identify a first index entry based on a fingerprint of the requested data segment to obtain a first write-evict unit (WEU) identifier (ID) identifying a first WEU storing the requested data segment. The system accesses a solid state device (SSD) operating as a cache memory device to retrieve the data segment from the first WEU. The system extracts and decompresses a compressed data segment retrieved from the first WEU and returns the decompressed data segment to the client without accessing a storage unit for retrieving the same data segment.Type: GrantFiled: April 17, 2017Date of Patent: February 2, 2021Assignee: EMC IP HOLDING COMPANY LLCInventors: Satish Visvanathan, Rahul B. Ugale, Yamini Allu, Vrushali A. Kulkarni
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Patent number: 10909005Abstract: The Object-Level Metadata-Preserving Cross Heterogeneous Operating Systems Backup And Restore Apparatuses, Methods And Systems (“MPBR”) transforms pairing request, backup request, restore request inputs via MPBR components into pairing response, backup response, restore response outputs. A device pairing request associated with a source share at a source device is obtained. A simulated block device backup volume for the source share is created on a backup device and formatted using a file system driver executable by the backup device's operating system. A backup request associated with the source share is obtained. A connection is established between the backup device and the source device using a file sharing protocol driver configured such that files metadata is presented to the backup device in a compatible metadata format. Files from the source share are synchronized. Changed synchronized files are determined. Metadata associated with the changed files is updated. A snapshot of the volume is generated.Type: GrantFiled: February 25, 2019Date of Patent: February 2, 2021Assignee: Datto, Inc.Inventors: Giovanni Roberto Carvelli, Chad A. Kosie
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Patent number: 10896062Abstract: A memory allocator assigns temporary memory limits to each of a plurality of processes requiring memory. Thereafter, at least one assigned temporary memory limit is changed during execution of a corresponding process. Related apparatus, systems, techniques and articles are also described.Type: GrantFiled: November 7, 2011Date of Patent: January 19, 2021Assignee: SAP SEInventors: Ivan Schreter, Daniel Booss
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Patent number: 10884941Abstract: Various embodiments are generally directed to techniques to store data for critical chunk operations, such as by utilizing a spare lane, for instance. Some embodiments are particularly directed to a memory controller that stores a portion of a critical chunk in a spare lane to enable the entire critical chunk to be stored in a half of the cache line.Type: GrantFiled: September 29, 2017Date of Patent: January 5, 2021Assignee: INTEL CORPORATIONInventor: Bill Nale
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Patent number: 10872652Abstract: A method and apparatus for optimizing calibrations of a memory subsystem is disclosed. A memory controller of a memory subsystem includes a memory interface suitable for coupling to a DRAM having a plurality of banks. The memory controller includes a state machine the state machine may initiate calibration of circuitry within the memory controller. Responsive to initiating the calibration, the state machine also causes a refresh command to be transmitted to the DRAM. The calibration is then performed concurrent with the refresh of the DRAM. Subsequent to transmitting the refresh command, the state machine causes the memory interface to be placed into a low power state.Type: GrantFiled: June 19, 2018Date of Patent: December 22, 2020Assignee: Apple Inc.Inventors: Rakesh L. Notani, Lakshmi Narasimha Murthy Nukala, Kai Lun Hsiung, Sukalpa Biswas, Yanzhe Liu
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Patent number: 10802753Abstract: Implementations disclosed herein include a storage system including a plurality of storage devices, wherein each of the plurality of storage devices includes compute resources, memory resources, and a storage device controller configured to perform application-specific data management operations using the compute resources and the memory resources of the storage device, and a storage system controller configured to distribute a workload across the plurality of storage devices based on a capability of each of the plurality of storage devices during an IDLE state. The capability of each of the plurality of storage devices may be specifications, current availability, and performance history of each of the plurality of storage devices. In some implementations, each of the plurality of storage devices communicate with each other via a peer-to-peer networking communications protocol (e.g., NVme, NVMof, PCIe, Ethernet, etc.).Type: GrantFiled: February 15, 2018Date of Patent: October 13, 2020Assignee: Seagate Technology LLCInventors: Nitin Kabra, Manish Sharma, Rajesh Bhagwat, Sneha Wagh, Nilesh Govande
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Patent number: 10768819Abstract: A method for non-disruptive upgrade of a storage system is provided. The method includes disabling, by an interlock, access by one or more processors of the storage system to the first memory, responsive to a request. The method includes persisting configuration information in the first memory to the solid-state memory, with the access to the first memory disabled by the interlock, wherein the persisting, the first memory and the solid-state memory are supported by an energy reserve. The method includes enabling, by the interlock, access by the one or more processors to the first memory, responsive to completing the persisting, and writing, by the one or more processors of the storage system, to the first memory, to perform the upgrade with further configuration information, with the access enabled by the interlock and wherein at least the persisting is accomplished without power cycling.Type: GrantFiled: October 27, 2016Date of Patent: September 8, 2020Assignee: Pure Storage, Inc.Inventors: Hari Kannan, Robert Lee
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Patent number: 10747678Abstract: A data storage device includes a storage tier and a storage controller operably coupled to the storage tier and configured to be communicatively coupled to a host device. The storage controller includes a first memory operably coupled to the storage controller and configured to store a superseding data structure. The storage controller further includes a second memory operably coupled to the storage controller and configured to store a forward map configured to map a plurality of logical block addresses to physical locations on the storage tier. The storage controller further includes a sifting module configured to sift the forward map based on data contained in the superseding data structure. The storage controller further includes a compression module configured to compress the forward map to generate a compressed forward map.Type: GrantFiled: October 27, 2016Date of Patent: August 18, 2020Assignee: SEAGATE TECHNOLOGY LLCInventors: Brian T. Edgar, Mark A. Gaertner, John Livdahl
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Patent number: 10732843Abstract: The method, computer program product, and computer system may include a computing device which may generate a list of data to be copied from a plurality of source media to a target medium. The computing device may identify a first type of data in the generated list of data with the first type of data being pre-migrated data. The computing device may reclaim the first type of data from a primary storage tier to the target medium with the target medium being associated with the first drive. The computing device may identify a second type of data in the generated list of data, the second type of data being migrated data, and reclaim the second type of data from at least one secondary source medium to the target medium using the first drive and a second drive. The secondary source medium may be associated with the second drive.Type: GrantFiled: June 20, 2018Date of Patent: August 4, 2020Assignee: International Business Machines CorporationInventors: Sosuke Matsui, Tohru Hasegawa, Tsuyoshi Miyamura, Noriko Yamamoto, Shinsuke Mitsuma, Hiroshi Itagaki
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Patent number: 10725909Abstract: According one embodiment, a memory device controlling method includes: receiving, by a first semiconductor memory, a read command transmitted from a controller; receiving, by a second semiconductor memory, a write command transmitted from the controller; reading, by the first semiconductor, data from the first semiconductor memory based on the read command, and transmitting, from the first semiconductor memory to the second semiconductor memory, the data and a control signal indicating that the data is output; and receiving, by the second semiconductor memory, the data at a timing based on the control signal transmitted from the first semiconductor memory without intermediation of the controller based on the write command and writing the received data into the second semiconductor memory.Type: GrantFiled: August 28, 2017Date of Patent: July 28, 2020Assignee: Toshiba Memory CorporationInventors: Kosuke Yanagidaira, Shouichi Ozaki
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Patent number: 10713046Abstract: Methods and System for use on a memory controller are disclosed which provides atomic compute operations of any size using an asynchronous, pipelined message passing interface between clients and the memory controller.Type: GrantFiled: December 20, 2017Date of Patent: July 14, 2020Assignee: EXTEN TECHNOLOGIES, INC.Inventors: Daniel B. Reents, Michael Enz, Ashwin Kamath
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Patent number: 10698826Abstract: The disclosure is related to storage devices employing file-aware drivers. In one example, a device may comprise a driver configured to retrieve file system information related to an input/output (I/O) command, determine storage attributes based on the file system information, and store selected data in a preferred region of a data storage medium based on the storage attributes. Another embodiment may be a method comprising inspecting characteristics of an I/O request for a file, setting storage attributes for the file based on if the file is preferred, and storing the file on a data storage medium based on the storage attributes.Type: GrantFiled: April 5, 2012Date of Patent: June 30, 2020Assignee: SEAGATE TECHNOLOGY LLCInventors: Daniel Robert McLeran, Steven Scott Williams
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Patent number: 10678450Abstract: A method begins by a processing module determining a priority access level of an encoded data slice stored on a memory device. The method continues by determining a soft failure level for the memory device, wherein the soft failure level includes a plurality of discrete usability levels with a highest usability level representing a maximum amount of usable memory, a second usability level representing a lower usability level than the highest usability level and a lowest usability level representing an unusable level when the usable memory is below a threshold. The method continues with the processing module determining whether to migrate the encoded data slice from the memory device based on the priority access level and the end-of-life memory level. The method continues with the processing module identifying another memory device. The method continues with the processing module facilitating migration of the encoded data slice to another memory device.Type: GrantFiled: October 30, 2018Date of Patent: June 9, 2020Assignee: PURE STORAGE, INC.Inventors: Gary W. Grube, Jason K. Resch, Timothy W. Markison, Ilya Volvovski, Manish Motwani