Abstract: The present disclosure provides a semiconductor device comprising: a block separator including a semiconductor film and a multi-layered insulating film, wherein the multi-layered insulating film surrounds the semiconductor film; memory block stacks divided from each other by the block separator, each memory block stack including interlayer insulating films and conductive patterns alternately stacked, wherein the conductive patterns are coupled to memory cells; and channel structures passing through the memory block stacks and electrically coupled to the memory cells.

Abstract: A semiconductor device includes: at least one gate structure comprising a gate electrode over a substrate, the gate electrode comprising a conductive material; and a first dielectric layer disposed along one or more side wall of the at least one gate structure, the first dielectric layer comprising fluorine doped silicon oxycarbonitride or fluorine doped silicon oxycarbide.

Abstract: A display device includes: a substrate having thereon a first subpixel, a second subpixel, and a third subpixel; a first electrode in each of the first to third subpixels on the substrate; a first bank between the first electrodes; a second bank on the first bank and having a width less than that of the first bank; a light emitting layer on the first electrodes, the first bank, and the second bank; and a second electrode on the light emitting layer. The light emitting layer provided on the second bank and the light emitting layer provided on the first bank are spaced apart from each other.

Abstract: A substrate bonding apparatus includes a first bonding chuck configured to support a first substrate and a second bonding chuck configured to support a second substrate such that the second substrate faces the first substrate. The first bonding chuck includes a first base, a first deformable plate on the first base and configured to support the first substrate and configured to be deformed such that a distance between the first base and the first deformable plate is varied, and a first piezoelectric sheet on the first deformable plate and configured to be deformed in response to power applied thereto to deform the first deformable plate.

Abstract: An integrated multilayer structure, includes a substrate film having a first side and an opposite second side. The substrate film includes electrically substantially insulating material, a circuit design including a number of electrically conductive areas of electrically conductive material on the first and/or second sides of the substrate film, and a connector including a number of electrically conductive contact elements. The connector is provided to the substrate film so that it extends to both the first and second sides of the substrate film and the number of electrically conductive contact elements connect to one or more of the conductive areas of the circuit design while being further configured to electrically couple to an external connecting element responsive to mating the external connecting element with the connector on the first or second side of or adjacent to the substrate film.

Abstract: A trench MOSFET and a manufacturing method of the same are provided. The trench MOSFET includes a substrate, an epitaxial layer having a first conductive type, a gate in a trench in the epitaxial layer, a gate oxide layer, a source region having the first conductive type, and a body region and an anti-punch through region having a second conductive type. The anti-punch through region is located at an interface between the source region and the body region, and a doping concentration thereof is higher than that of the body region. The epitaxial layer has a first pn junction near the source region and a second pn junction near the substrate. N regions are divided into N equal portions between the two pn junctions, and N is an integer greater than 1. The closer the N regions are to the first pn junction, the greater the doping concentration thereof is.

Abstract: An integrated circuit device includes a substrate including first and second fin-type active areas, a gate structure on the first and second fin-type active areas, first and second source/drain regions on the first and second fin-type active areas, respectively, a first source/drain contact on the first source/drain region and comprising first and second portions, a second source/drain contact on the second source/drain region and comprising first and second portions, the second portion having an upper surface at a lower level than an upper surface of the first portion, a first stressor layer on the upper surface of the second portion of the first source/drain contact, and a second stressor layer on the upper surface of the second portion of the second source/drain contact, the second stressor layer including a material different from a material included in the first stressor layer.

Abstract: An organic light-emitting display comprises a substrate having a plurality of subpixels arranged in a row direction and a column direction crossing the row direction; a plurality of first electrodes respectively allocated to the plurality of subpixels and comprising a first sub-electrode arranged in a (3n?2) column, a second sub-electrode arranged in a (3n?1) column, and a third sub-electrode arranged in a 3n column (where n is a natural number of 1 or more); and a bank having an opening exposing the plurality of first electrodes, wherein the first sub-electrode has a convex part protruded toward the third sub-electrode that has a concave part corresponding to the convex part.

Abstract: A semiconductor device and its fabrication method are provided in the present disclosure. The method includes providing a substrate; forming a plurality of fins spaced apart on the substrate; forming a dummy gate structure across the plurality of fins and on the substrate; forming a first sidewall spacer on a sidewall of the dummy gate structure; forming an interlayer dielectric layer on the substrate and the fins, and on a portion of a sidewall of the first sidewall spacer, where a top of the interlayer dielectric layer is lower than a top of the first sidewall spacer; and forming a second sidewall spacer on the interlayer dielectric layer and on a sidewall of the first sidewall spacer.

Abstract: A semiconductor device has a first area in which first and third semiconductor elements are formed, a second area in which second and fourth semiconductor elements are formed, and a third area located between the first and second areas. On the first to fourth semiconductor elements, a multilayer wiring layer including first and second inductors is formed. A through hole penetrating the semiconductor substrate is formed in the third area, and a first element isolation portion protruding from a front surface side of the semiconductor substrate toward a back surface side of the semiconductor substrate is formed in the through hole. Further, on the back surface side of the semiconductor substrate, the semiconductor substrate in the first area is mounted on the first die pad, and the semiconductor substrate in the second area is mounted on the second die pad.

Abstract: Light emitting devices and components having excellent chemical resistance and related methods are disclosed. In one embodiment, a component of a light emitting device can include a silver (Ag) portion, which can be silver on a substrate, and a protective layer disposed over the Ag portion. The protective layer can at least partially include an inorganic material for increasing the chemical resistance of the Ag portion.

Abstract: A semiconductor wafer is preheated with a halogen lamp, and then is heated by irradiation with a flash of light emitted from a flash lamp. The preheating with the halogen lamp is continued for a short time even after the flash lamp turns off. A radiation thermometer measures a front surface temperature and a back surface temperature of the semiconductor wafer. A temperature integrated value is calculated by integration of temperatures of the semiconductor wafer measured during a period from a start of the flash irradiation to an end of the heating of the semiconductor wafer. It is determined that the semiconductor wafer is cracked at the time of flash irradiation when the calculated temperature integrated value deviates from a preset range between an upper limit value and a lower limit value.

Abstract: A memory device including a base chip and a memory cube mounted on and connected with the base chip is described. The memory cube includes multiple stacked tiers, and each tier of the multiple stacked tiers includes semiconductor chips laterally wrapped by an encapsulant and a redistribution structure. The semiconductor chips of the multiple stacked tiers are electrically connected with the base chip through the redistribution structures in the multiple stacked tiers. The memory cube includes a thermal path structure extending through the multiple stacked tiers and connected to the base chip. The thermal path structure has a thermal conductivity larger than that of the encapsulant. The thermal path structure is electrically isolated from the semiconductor chips in the multiple stacked tiers and the base chip.

Abstract: An organic compound and a manufacturing method thereof, and an organic light emitting diode electroluminescent device are provided. The organic compound has a suitable HOMO energy level and a high hole mobility. Compared with traditional hole transport materials, when the organic compound is applied in a hole transport layer of the organic light emitting diode electroluminescent device, the organic light emitting diode electroluminescent device has enhanced maximum current efficiency, maximum external quantum efficiency, and service lifespans.

Abstract: An integrated circuit includes a substrate layer and a resistor bank in a polysilicon layer disposed on the substrate layer. The resistor bank includes a plurality of resistor elements having a body portion extending in a longitudinal direction. A metal line is disposed in a metal layer above the polysilicon layer to extend transverse to the longitudinal direction and across the body portion of a group of the plurality of resistor elements, thereby forming a first region of the resistor bank and a second region of the resistor bank. The first region is separated from the second region by the metal line. A resistor device having a predetermined resistance includes a subset of the resistor elements in the group electrically coupled together in the second region. The resistor device also includes first and second terminals located in the same first or second region of the resistor bank.

Abstract: A semiconductor memory device includes a stack of word lines and insulating patterns. Cell pillars extend vertically through the stack of word lines and insulating patterns with memory cells being formed at the junctions of the cell pillars and the word lines. A ratio of the thickness of the word lines to the thickness of immediately neighboring insulating patterns is different at different locations along one or more of the cell pillars. Related methods of manufacturing and systems are also disclosed.

Abstract: Enhanced thermal energy transfer systems for semiconductor packages are provided. A thermally conductive member is disposed in the interstitial space between an upper surface of a semiconductor package and a lower surface of a thermal member. The thermally conductive member is disposed above a first portion of the upper surface of the semiconductor package having a relatively higher thermal energy output when the semiconductor package is operating. A thermal interface material is disposed in the interstitial space and a force applied to the thermal member. The thermally conductive member forms a relatively higher pressure region above the first portion of the semiconductor package and a relatively lower pressure region in other portions of the semiconductor package remote from the thermally conductive member. The increased pressure region proximate the thermally conductive member beneficially enhances the flow of thermal energy from the first portion of the semiconductor package to the thermal member.

Abstract: The present application discloses an OTP memory. A cell structure includes a first active region and a second active region that intersect vertically; an EDNMOS is formed in the first active region, and a PMOS is formed in the second active region; a body portion of a channel region of the PMOS is formed a drift region of the EDNMOS, a first polysilicon gate of the EDNMOS serves as a control gate, and a second polysilicon gate of the PMOS serves as a floating gate; and the PMOS is programmed by means of hot carriers generated in the drift region of the EDNMOS. The present application further discloses a method for manufacturing an OTP memory. In the present application, high-speed writing can be implemented.

Abstract: The present disclosure relates to a display structure, a display panel including the display structure, and a display device including the display panel and an image acquisition device. The display structure includes a plurality of pixels disposed in a first region of the display structure, wherein each pixel of the plurality of pixels includes a plurality of sub-pixels of N number of colors, and each sub-pixel of the plurality of sub-pixels includes an organic light emitting diode; and N number of driving circuits disposed in a second region of the display structure, wherein an ith driving circuit of the N number of driving circuits is configured to drive each sub-pixel of an ith color of the plurality of sub-pixels, wherein 1?i?N and N is an integer greater than 1.

Abstract: A display substrate, a manufacturing method thereof, and a display device are disclosed. The display substrate includes a base substrate; a pixel defining layer on the base substrate, the pixel defining layer includes a plurality of openings, the pixel defining layer includes a first pixel defining layer, a conductive layer, and a second pixel defining layer which are stacked, in the pixel defining layer in at least a peripheral region of the display substrate, an orthographic projection of the conductive layer on the base substrate completely falls within an orthographic projection of the second pixel defining layer on the base substrate; and an electroluminescent unit including a transparent electrode the transparent electrode is electrically connected with the conductive layer in the pixel defining layer in at least the peripheral region of the display substrate.