Abstract: A carrier structure for transducers. The semiconductor carrier structure mounts as a single unit to a force-impacted substrate and includes multiple piezoelectric elements integrally formed with the carrier structure, such that the elements are located in a space defining a window of the structure while maintaining their electrical contact and their precise position relative to the structure by use of thin-film, electrically conductive, metallic flexures attached to both the structure and the elements.

Abstract: A high frequency bypass capacitor (36, 36') is built into a thin-film portion (16, 16') of a polymer carrier substrate (15) of a PBGA (10). The carrier substrate (15) has both a stiffener (18) and a thin-film portion (16, 16') which has multiple metal layers (24, 28, 30, 32). The power supply planes (28, 30) of these metal layers are used to form built-in bypass capacitors (36, 36'), wherein the power supply planes are specifically designed to be adjacent and parallel layers. An ultra thin film laminate construction provides thin dielectric films (26) between the metal layers to allow the bypass capacitor to be placed very dose to the attached semiconductor die (12) to further reduce parasitic inductance and resistance between die connections (14) and the bypass capacitor. The built-in feature minimizes inherent parasitic series inductance and resistance, thus enabling the filtering of unwanted low pulse width glitches on a power plane connected to VLSI devices at operating frequencies at or above 100 MHz.

Abstract: An electronic package which includes a thermally conductive, e.g., copper, member having a thin layer of dielectric material, e.g., polyimide, on at least one surface thereof. On the polyimide is provided the desired high density circuit pattern which is electrically connected, e.g., using solder or wirebonds, to the respective contact sites of a semiconductor chip. If wirebonds are used, the copper member preferably includes an indentation therein and the chip is secured, e.g., using adhesive, within this indentation. If solder is used to couple the chip, a plurality of small diameter solder elements are connected to respective contact sites of the chip and to respective ones of the pads and/or lines of the provided circuit pattern. Significantly, the pattern possesses lines and/or pads in one portion which are of high density and lines and/or pads in another portion which are of lesser density.