Patents Examined by Masud K Khan
  • Patent number: 11768779
    Abstract: Systems, apparatuses, and methods for cache management based on access type priority are disclosed. A system includes at least a processor and a cache. During a program execution phase, certain access types are more likely to cause demand hits in the cache than others. Demand hits are load and store hits to the cache. A run-time profiling mechanism is employed to find which access types are more likely to cause demand hits. Based on the profiling results, the cache lines that will likely be accessed in the future are retained based on their most recent access type. The goal is to increase demand hits and thereby improve system performance. An efficient cache replacement policy can potentially reduce redundant data movement, thereby improving system performance and reducing energy consumption.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: September 26, 2023
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Jieming Yin, Yasuko Eckert, Subhash Sethumurugan
  • Patent number: 11768635
    Abstract: Scaling storage resources in a storage volume, including: monitoring a usage of a volume in a storage pool that includes one or more cloud-based storage systems; determining that the usage of the volume exceeds a threshold usage; and based on the determination, expanding the resources that are included in the storage pool for servicing the volume, including: instantiating one or more new virtual drives that are included in the one or more cloud-based storage systems; and adding the one or more new virtual drives to the storage pool.
    Type: Grant
    Filed: April 25, 2022
    Date of Patent: September 26, 2023
    Assignee: PURE STORAGE, INC.
    Inventors: Taher Vohra, Par Botes, Naveen Neelakantam, Ivan Jibaja
  • Patent number: 11755494
    Abstract: Techniques for performing cache operations are provided. The techniques include for a memory access class, detecting a threshold number of instances in which cache lines in an exclusive state in a cache are changed to an invalid state or a shared state without being in a modified state; in response to the detecting, treating first coherence state agnostic requests for cache lines for the memory access class as requests for cache lines in a shared state; detecting a reset event for the memory access class; and in response to detecting the reset event, treating second coherence state agnostic requests for cache lines for the memory class as coherence state agnostic requests.
    Type: Grant
    Filed: October 29, 2021
    Date of Patent: September 12, 2023
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Paul J. Moyer
  • Patent number: 11747987
    Abstract: An electronic device includes a data storage device and a host device. The host device is coupled to the data storage device via a predetermined interface and includes a processor. The processor dynamically adjusts a data transfer speed of the predetermined interface according to a data processing speed required by data to be read from or written to the data storage device.
    Type: Grant
    Filed: January 11, 2018
    Date of Patent: September 5, 2023
    Assignee: Silicon Motion, Inc.
    Inventors: Fu-Jen Shih, Chia-Ching Huang
  • Patent number: 11748018
    Abstract: Embodiments include systems and methods for mass data optimization. Embodiments include receiving user data from a user server which is being continuously collected locally by the user server and storing the user data on a storage device of a storage module, deduplicating the user data on the storage device, performed by the storage module, compressing the user data on the storage device, performed by the storage module, transparently intercepting the user data by a data intercept module, rerouting the transparently intercepted data to a data communication optimization module for optimization and intelligent routing, optimizing communication by the data communication optimization module so that the intercepted user data is configured differently for data communication to a remote centralized datacenter or server, and transmitting the differently configured data to a centralized datacenter or server.
    Type: Grant
    Filed: September 30, 2021
    Date of Patent: September 5, 2023
    Inventor: Roux Visser
  • Patent number: 11748266
    Abstract: Embodiments are for special tracking pool enhancement for core L1 address invalidates. An invalidate request is designated to fill an entry in a queue in a local cache of a processor core, the queue including a first allocation associated with processing any type of invalidate request and a second allocation associated with processing an invalidate request not requiring a response in order for a controller to be made available, the entry being in the second allocation. Responsive to designating the invalidate request to fill the entry in the queue in the local cache, a state of the controller that made the invalidate request is changed to available based at least in part on the entry being in the second allocation.
    Type: Grant
    Filed: March 4, 2022
    Date of Patent: September 5, 2023
    Assignee: International Business Machines Corporation
    Inventors: Deanna Postles Dunn Berger, Gregory William Alexander, Richard Joseph Branciforte, Aaron Tsai, Markus Kaltenbach
  • Patent number: 11733903
    Abstract: Data units can be relocated in scale-out storage systems. For example, a computing device can receive, at a first node of a scale-out storage system, a request for a data unit. The first node can include a metadata entry associated with the data unit. The computing device can determine, based on the metadata entry, that a second node of the scale-out storage system includes the data unit. The computing device can determine, from the metadata entry, that a number of versions of the data unit in the scale-out storage system meets or exceeds a threshold. The computing device can output a command to cause the data unit to be relocated to the first node with the metadata entry.
    Type: Grant
    Filed: June 8, 2021
    Date of Patent: August 22, 2023
    Assignee: RED HAT, INC.
    Inventors: Joshua Durgin, Gabriel Zvi BenHanokh
  • Patent number: 11734183
    Abstract: A method for controlling the data flow in the storage device is applied to a host, and includes obtaining a cache input and output parameter, determining whether the cache input and output parameter meets an overload condition, when the cache input and output parameter meets the overload condition, obtaining a first bandwidth value, where the first bandwidth value is less than a current flushing bandwidth value of the cache, determining a quantity of tokens based on the first bandwidth value, and controlling the data flow in the storage device.
    Type: Grant
    Filed: September 15, 2020
    Date of Patent: August 22, 2023
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Yonghui Huang, Fuquan Yang, Wei Zeng, Chunhua Tan
  • Patent number: 11714741
    Abstract: An apparatus comprises at least one processing device that includes a processor coupled to a memory. The processing device is configured to receive, by a trace filter system, a trace chunk from a trace buffer associated with a processor core in a processing device, where the trace buffer is comprised of a plurality of trace chunks, to filter, by the trace filter system, the trace chunk, and to store the filtered trace chunk in the trace buffer.
    Type: Grant
    Filed: June 17, 2021
    Date of Patent: August 1, 2023
    Assignee: EMC IP Holding Company LLC
    Inventors: Xiangping Chen, David Meiri
  • Patent number: 11709776
    Abstract: N-way associative cache pools can be implemented in an N-way associative cache. Different cache pools can be indicated by pool values. Different processes running on a computer can use different cache pools. An N-way associative cache circuit can be configured to have one or more stripe mode cache pools that are N-way associative. A cache control circuit can receive a physical address for a memory location and can interpret the physical address as fields including a tag field that contains a tag value and a set field that contains a set value. The physical address can also be used to determine a pool value that identifies one of the stripe mode cache pools. A set of N cache entries in the one of the stripe mode cache pools can be concurrently searched for the tag value. The set of N cache entries is determined using the set value.
    Type: Grant
    Filed: March 29, 2021
    Date of Patent: July 25, 2023
    Assignee: Pensando Systems Inc.
    Inventor: Changqi Yang
  • Patent number: 11709780
    Abstract: Methods, non-transitory machine readable media, and computing devices that manage resources between multiple hosts coupled to dual-port solid-state disks (SSDs) are disclosed. With this technology, in-core conventional namespace (CNS) and zoned namespace (ZNS) mapping tables are synchronized by a host flash translation layer with on-disk CNS and ZNS mapping tables, respectively. An entry in one of the in-core CNS or ZNS mapping tables is identified based on whether a received storage operation is directed to a CNS or a ZNS of the dual-port SSD. The entry is further identified based on a logical address extracted from the storage operation. The storage operation is serviced using a translation in the identified entry for the logical address, when the storage operation is directed to the CNS, or a zone identifier in the identified entry for a zone of the ZNS, when the storage operation is directed to the ZNS.
    Type: Grant
    Filed: May 31, 2022
    Date of Patent: July 25, 2023
    Assignee: NETAPP, INC.
    Inventors: Abhijeet Gole, Ratnesh Gupta, Douglas Doucette
  • Patent number: 11704066
    Abstract: A method of using flash storage devices with different sized erase blocks is provided. The method includes allocating a plurality of erase blocks of heterogeneous erase block sizes to a RAID stripe, to form a tile pattern having the heterogeneous erase block sizes in the RAID stripe. The method includes writing the RAID stripe across the flash storage devices in accordance with the allocating, and stopping the writing the RAID stripe, responsive to contents of the RAID stripe reaching a threshold.
    Type: Grant
    Filed: June 15, 2021
    Date of Patent: July 18, 2023
    Assignee: PURE STORAGE, INC.
    Inventors: Eric D. Seppanen, Andrew R. Bernat, Timothy W. Brennan, Mark L. McAuliffe, Neil Buda Vachharajani
  • Patent number: 11704235
    Abstract: A memory system of an embodiment includes a nonvolatile memory, a primary cache memory, a secondary cache memory, and a processor. The processor performs address conversion by using logical-to-physical address conversion information relating to data to be addressed in the nonvolatile memory. Based on whether first processing is performed on the nonvolatile memory or second processing is performed on the nonvolatile memory, the processor controls to store whether the logical-to-physical address conversion information relating to the first processing to be in the primary cache memory as cache data or logical-to-physical address conversion information relating to the second processing to be in the secondary cache memory as cache data.
    Type: Grant
    Filed: June 1, 2021
    Date of Patent: July 18, 2023
    Assignee: Kioxia Corporation
    Inventors: Shogo Ochiai, Nobuaki Tojo
  • Patent number: 11698728
    Abstract: A storage system includes a management node and a plurality of storage nodes forming a redundant array of independent disks (RAID). When the management node determines that not all data in an entire stripe is updated based on a received write request, the management node sends an update data chunk obtained from to-be-written data to a corresponding storage node. The storage node does not directly update, based on the received update data chunk, a data block stored in a storage device of the storage node, but store the update data chunk into a non-volatile memories (NVM) cache of the storage node and send the update data chunk to another storage node for backup. According to the data updating method, write amplification problems caused in a stripe update process can be reduced, thereby improving update performance of the storage system.
    Type: Grant
    Filed: July 13, 2022
    Date of Patent: July 11, 2023
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Qun Yu, Jun Xu, Yuangang Wang
  • Patent number: 11698863
    Abstract: Disclosed is a data set and node cache-based scheduling method, which includes: obtaining storage resource information of each host node; in response to receiving a training task, obtaining operation information of the training task, and according to the operation information and the storage resource information, screening host nodes that satisfy a space required by the training task; in response to no host node satisfying the space required by the training task, scoring each host node according to the storage resource information; according to scoring results, selecting, from among all of the host nodes, a host node to be executed that is used to execute the training task; and obtaining and deleting an obsolete data set cache in the host node to be executed, and executing the training task in the host node to be executed.
    Type: Grant
    Filed: July 30, 2021
    Date of Patent: July 11, 2023
    Assignee: INSPUR SUZHOU INTELLIGENT TECHNOLOGY CO., LTD.
    Inventors: Dekui Wang, Pei Chen
  • Patent number: 11687458
    Abstract: A multi-resolution cache includes a first, second and third cache segments the first segment having a first resolution and the second and third segments having a second resolution, the second resolution less than the first resolution, the first and third cache segments communicatively coupled to an off-chip memory, the first and third cache segments configured to each receive a cache line of data having the first and second resolutions, a fourth and fifth cache segments having the second resolution, a first downscaler communicatively coupled to the first and fourth cache segments configured to reduce the resolution when a first resolution cached data is shifted from the first cache segment to the fourth cache segment, a first upscaler communicatively coupled to the all cache segments that have the second resolution, and is configured to increase the reduced resolution cached data to the first resolution and output it.
    Type: Grant
    Filed: December 2, 2021
    Date of Patent: June 27, 2023
    Assignee: V-Silicon Semiconductor (Hefei) Co., Ltd
    Inventors: Bahman Zafarifar, Jeroen Maria Kettenis
  • Patent number: 11681454
    Abstract: A cloud server determines that a size of a first cloud storage element object is at least below a first threshold. In response to the first determination, a client-side component is requested to store additional data in the cloud storage element object including by having the client-side component update the first cloud storage element with an updated version that includes previously existing data of the first cloud storage element and the additional data. The first cloud storage element object is added to a set of one or more cloud storage element objects available for update. The client-side component is configured to generate an updated version of the first cloud storage element object that has a size that is greater than or equal to the first threshold.
    Type: Grant
    Filed: August 13, 2021
    Date of Patent: June 20, 2023
    Assignee: Cohesity, Inc.
    Inventors: Anubhav Gupta, Praveen Kumar Yarlagadda, Venkata Ranga Radhanikanth Guturi, Zhihuan Qiu, Sarthak Agarwal
  • Patent number: 11681455
    Abstract: A smart network interface card in an information handling system monitors a local host memory associated with a computer resource for an update to a memory page in the local host memory. After the update to the memory page, the smart network interface card copies the memory page to its memory. The smart network interface card sets a watchdog timer to detect a failure in an the information handling system that hosts the computer resource and if the failure is detected, then the smart network interface card migrates the computer resource from its to another information handling system.
    Type: Grant
    Filed: July 22, 2021
    Date of Patent: June 20, 2023
    Assignee: Dell Products L.P.
    Inventors: Gaurav Chawla, William P. Dawkins, Hendrich Hernandez
  • Patent number: 11669467
    Abstract: Processing circuitry performs processing operations specified by program instructions, and a decoder decodes memory access instructions to generate control signals to control the processing circuitry to perform memory access operations. The memory access instructions have respective encodings specifying protected memory access instructions corresponding to protected memory access operations and less-protected memory access instructions corresponding to less-protected memory access operations. The less-protected memory access operations are associated with less restrictive memory access conditions than the protected memory access operations.
    Type: Grant
    Filed: September 6, 2016
    Date of Patent: June 6, 2023
    Assignee: Arm Limited
    Inventors: Jason Parker, Richard Roy Grisenthwaite
  • Patent number: 11662949
    Abstract: A storage server and a method of driving the storage server are provided. The storage server includes a processor configured to: generate a plurality of flush write commands based on a write command of first data provided from a host, provide a replication command corresponding to the write command to an external storage server, and receive an operation completion signal of the replication command from the external storage server; a memory storing a program of a log file to which the plurality of flush write commands are logged; and a storage device configured to receive a multi-offset write command including one or more flush write commands logged to the log file, and perform a flush operation on the multi-offset write command. The processor is further configured to provide the multi-offset write command to the storage device based on the log file after receiving the operation completion signal.
    Type: Grant
    Filed: June 21, 2021
    Date of Patent: May 30, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Myoung Won Oh, Ji Woong Park, Sung Kyu Park, Kyu Ho Son