Patents Examined by Masud K Khan
  • Patent number: 11568313
    Abstract: An object of the present disclosure is to provide a control apparatus that controls a plurality of communication systems so that the plurality of communication systems can perform analysis with high accuracy. The control apparatus (30) according to the present disclosure includes a communication unit (31) and a determination unit (32). The communication unit (31) receives, from an analysis apparatus (10) configured to perform machine learning using communication logs collected from a communication apparatus in order to generate a learning model, statistical information about each of the communication logs and information about the learning model. The determination unit (32) determines an analysis apparatus (20) to which the information about the learning model is applied based on the statistical information.
    Type: Grant
    Filed: December 4, 2018
    Date of Patent: January 31, 2023
    Assignee: NEC CORPORATION
    Inventors: Daisuke Yokoi, Tadashi Ishikawa, Takuya Itou, Ichirou Akimoto
  • Patent number: 11561900
    Abstract: A data processing system includes system memory and a plurality of processor cores each supported by a respective one of a plurality of vertical cache hierarchies. A first vertical cache hierarchy records information indicating communication of cache lines between the first vertical cache hierarchy and others of the plurality of vertical cache hierarchies. Based on selection of a victim cache line for eviction, the first vertical cache hierarchy determines, based on the recorded information, whether to perform a lateral castout of the victim cache line to another of the plurality of vertical cache hierarchies rather than to system memory and selects, based on the recorded information, a second vertical cache hierarchy among the plurality of vertical cache hierarchies as a recipient of the victim cache line via a lateral castout. Based on the determination, the first vertical cache hierarchy performs a castout of the victim cache line.
    Type: Grant
    Filed: August 4, 2021
    Date of Patent: January 24, 2023
    Assignee: International Business Machines Corporation
    Inventors: Bernard C. Drerup, Guy L. Guthrie, Jeffrey A. Stuecheli, Alexander Michael Taft, Derek E. Williams
  • Patent number: 11556281
    Abstract: A semiconductor memory device includes a memory cell array, a peripheral circuit, and control logic. The memory cell array includes a plurality of memory cells. The peripheral circuit is configured to perform a first operation, corresponding to a first command, on the memory cell array. The control logic is configured to control the first operation of the peripheral circuit. The control logic is configured to control the peripheral circuit to suspend the performance of the first operation and perform a second operation corresponding to a second command, in response to the second command being received while the first operation is being performed.
    Type: Grant
    Filed: June 10, 2020
    Date of Patent: January 17, 2023
    Assignee: SK hynix Inc.
    Inventor: Byoung Young Kim
  • Patent number: 11556430
    Abstract: An apparatus comprises a processing device configured to receive a request to restore one or more applications, the request specifying one of a set of remote copies of storage volumes that store data of the applications. The processing device is also configured to analyze the applications to identify (i) the storage volumes storing data for the applications and (ii) groups comprising the identified storage volumes. The processing device is also configured, responsive to determining that the identified groups are part of a group replication session, to select one of a set of different types of restore processes for performing the restore of the applications to the specified remote copy based at least in part on whether the identified groups comprise additional storage volumes other than the identified storage volumes and to perform the restore of the applications to the specified remote copy utilizing the selected restore process.
    Type: Grant
    Filed: February 11, 2021
    Date of Patent: January 17, 2023
    Assignee: EMC IP Holding Company LLC
    Inventors: Shivasharan Dalasanur Narayana Gowda, Sunil Kumar, Prashant Pokharna
  • Patent number: 11550725
    Abstract: Exemplary methods, apparatuses, and systems include detecting an operation to write dirty data to a cache. The cache is divided into a plurality of channels. In response to the operation, the dirty data is written to a first cache line in the cache, the first cache line being accessed via a first channel. Additionally, a redundant copy of the dirty data is written to a second cache line in the cache. The second cache line serves as a redundant write buffer and is accessed via a second channel, the first and second channels differing from one another. A metadata entry for the second cache line is updated to reference a location of the dirty data in the first cache line.
    Type: Grant
    Filed: May 18, 2020
    Date of Patent: January 10, 2023
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Cagdas Dirik, Robert M. Walker
  • Patent number: 11544147
    Abstract: Techniques for using erasure coding across multiple regions to reduce the likelihood of losing objects in a cloud object storage platform are provided. In one set of embodiments, a computer system can upload each of a plurality of data objects to each of a plurality of regions of the cloud object storage platform. The computer system can further compute a parity object based on the plurality of data objects, where the parity object encodes parity information for the plurality of data objects. The computer system can then upload the parity object to another region of the cloud object storage platform different from the plurality of regions.
    Type: Grant
    Filed: May 22, 2020
    Date of Patent: January 3, 2023
    Assignee: VMWARE, INC.
    Inventors: Wenguang Wang, Junlong Gao, Vamsi Gunturu
  • Patent number: 11544151
    Abstract: A system, method, and computer program product for a block-based backing up a storage device to an object storage service is provided. This includes the generation of a data object that encapsulates a data of a data extent. The data extent covers a block address range of the storage device. The data object is named with a base name that represents a logical block address (LBA) of the data extent. The base name is appended with an identifier that deterministically identifies a recovery point that the data object is associated with. The base name combined with the identifier represents a data object name for the data object. The named data object is then transmitted to the object storage service for backup of the data extent. At an initial backup, the full storage device is copied. In incremental backups afterwards, only those data extents that changed are backed up.
    Type: Grant
    Filed: August 20, 2021
    Date of Patent: January 3, 2023
    Assignee: NETAPP, INC.
    Inventors: William Hetrick, Dennis James Hahn, Russell Winkler
  • Patent number: 11526405
    Abstract: Performing disaster recovery in a cloud-based storage system, including: creating, by a storage system a snapshot of a dataset; uploading, from the storage system to a cloud computing environment, the snapshot; storing, by the cloud computing environment, the snapshot; detecting, by the cloud computing environment, that the dataset is not available on the storage system; and creating, by the cloud computing environment using the snapshot that is stored within the cloud computing environment, a cloud-based storage system that includes the dataset.
    Type: Grant
    Filed: April 17, 2019
    Date of Patent: December 13, 2022
    Assignee: PURE STORAGE, INC.
    Inventors: James Fisher, Naveen Neelakantam, Yuval Frandzel
  • Patent number: 11526286
    Abstract: A storage manager implements adaptive snapshot chunk sizing, wherein snapshot chunks are sized differently based on an access pattern for volume data to be included in the respective snapshot chunks. For example, sequentially accessed sectors of a volume may be grouped into snapshot chunks of varying sizes and individually accessed sectors may be snapshotted as individual snapshot chunks. When a volume is populated from the snapshot chunks, the volume data is re-mapped into standard sized volume blocks. In some embodiments, an optimized manifest is generated indicting an order in which the snapshot chunks are to be used to populate a volume to perform a launch process using the volume. In some embodiments, adaptively sized snapshot chunks and a corresponding optimized manifest are used to accelerate performing a launch using a volume populated from a snapshot, such as launching an operating system, an application, a database, a machine image, etc.
    Type: Grant
    Filed: June 29, 2021
    Date of Patent: December 13, 2022
    Assignee: Amazon Technologies, Inc.
    Inventors: Xuan Li, Marcin Piotr Kowalski, Anna Clara Nagy
  • Patent number: 11513948
    Abstract: A memory system includes a first memory device including a plurality of first physical blocks; a second memory device including a plurality of second physical blocks; a first core suitable for managing a plurality of first super blocks that store data associated with a first logical address, the plurality of first super blocks being mapped to the plurality of first physical blocks; a second core suitable for managing a plurality of second super blocks that store data associated with a second logical address, the plurality of second super blocks being mapped to the plurality of second physical blocks; a global wear-leveling manager suitable for changing mapping between the first physical blocks, which are mapped to one among the first super blocks, and the second physical blocks, which are mapped to one among the second super blocks based on degrees of wear of the first and second super blocks.
    Type: Grant
    Filed: September 11, 2020
    Date of Patent: November 29, 2022
    Assignee: SK hynix Inc.
    Inventors: Yong Seok Oh, Youngho Ahn, Joon Ho Lee, Chang Eun Choi
  • Patent number: 11513947
    Abstract: Embodiments of the present disclosure relate to establishing and verifying an index file. The method for establishing an index file includes: in response to receiving a data block to be stored, determining first verification information for verifying the data block and a first storage address for storing the data block. This method further includes: based on the first verification information, determining an index entry for the data block and a second storage address for storing the index entry, wherein the index entry includes the first verification information and the first storage address, and the index entry will be included in the index file. This method further includes: based on the index entry and the second storage address, determining second verification information. This method further includes: based on the second verification information and historical verification information for the index file, determining third verification information for verifying the index file.
    Type: Grant
    Filed: May 31, 2020
    Date of Patent: November 29, 2022
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventors: Haitao Li, Jie Liu, Jian Wen, Chao Lin
  • Patent number: 11513835
    Abstract: An example memory sub-system includes a memory device and a processing device, operatively coupled to the memory device. The processing device is configured to receive a reset signal from a host computer system in communication with the memory system; identify, by decoding the reset signal, a host event specified by the reset signal; and process the identified host event.
    Type: Grant
    Filed: June 1, 2020
    Date of Patent: November 29, 2022
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Qing Liang, Jonathan S. Parry, Kulachet Tanpairoj, Stephen Hanna
  • Patent number: 11513949
    Abstract: The memory system comprises nonvolatile memory devices each including plural superblocks and a controller. The controller is configured to select a victim superblock including a smaller number of valid pages than any among remaining superblocks, exchange a greater-valid-pages block with a smaller-valid-pages block, and control the memory device to perform a garbage collection operation on the victim superblock, wherein the greater-valid-pages block is included in the victim superblock and the smaller-valid-pages block is included in one among the remaining superblocks, and wherein the smaller-valid-pages block has a smaller number of valid pages than the greater-valid-pages block.
    Type: Grant
    Filed: March 24, 2021
    Date of Patent: November 29, 2022
    Assignee: SK hynix Inc.
    Inventors: Ching-Chung Lai, Lian-Chun Lee, Chun-Shu Chen
  • Patent number: 11513932
    Abstract: A method includes obtaining a first memory log, where the first memory log includes log information of a plurality of garbage collections, and log information of each garbage collection includes a garbage collection time, and includes at least one of a downtime, memory usage after garbage collection, and memory usage before garbage collection, obtaining, based on log information in a first detection time window, first statistical information corresponding to the first detection time window, and determining, based on the first statistical information corresponding to the first detection time window, an anomaly degree corresponding to the log information in the first detection time window.
    Type: Grant
    Filed: January 22, 2020
    Date of Patent: November 29, 2022
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Xin Xiao, Kang Cheng, Liang Zhang, Jian Li, Jiyu Pan
  • Patent number: 11507290
    Abstract: A method for provided use in a storage device having a controller, the method comprising: identifying, by the controller, a plurality of logical regions in the storage device; obtaining, by the controller, a respective usage metric for each of the logical regions; updating, by the controller, a translation data structure of the storage device, the translation data structure being updated to map any of the logical regions of the storage device to a respective physical portion of the storage device, the respective physical portion being selected based on the respective usage metric of the logical region, wherein the translation data structure is part of a flash translation layer of the storage device, and the translation data structure is configured to store mapping information between a logical address space of the storage device and a physical address space of the storage device.
    Type: Grant
    Filed: March 26, 2020
    Date of Patent: November 22, 2022
    Assignee: EMC IP Holding Company LLC
    Inventors: Nickolay Dalmatov, Assaf Natanzon
  • Patent number: 11500581
    Abstract: The present disclosure generally relates to efficient transfer layer packet (TLP) fragmentation in a data storage device. For an unaligned read from host flow, an amount of data sufficient to be aligned is transferred to the memory device from the host while the remainder of the data is stored in cache of the data storage device to be delivered to memory device at a later time. For an unaligned write to host flow, the unaligned data is written to cache and at a later time the cache will be flushed to the host device. In both cases, while the total data would be unaligned, a portion of the data is placed in cache so that the data not placed in cache is aligned. The data in cache is delivered at a later point in time.
    Type: Grant
    Filed: February 23, 2021
    Date of Patent: November 15, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Shay Benisty, Amir Segev
  • Patent number: 11500774
    Abstract: A system and method of handling access demands in a virtual cache comprising, by a processing system, checking if a virtual cache access demand missed because of a synonym tagged in the virtual cache; in response to the virtual cache access demand missing because of a synonym tagged in the virtual cache, updating the virtual address tag in the virtual cache to a new virtual address tag; searching for additional synonyms tagged in the virtual cache; and in response to finding additional synonyms tagged in the virtual cache, updating the virtual address tag of the additional synonyms to the new virtual address tag.
    Type: Grant
    Filed: March 9, 2021
    Date of Patent: November 15, 2022
    Assignee: International Business Machines Corporation
    Inventors: David Campbell, Bryan Lloyd
  • Patent number: 11487616
    Abstract: In described examples, a processor system includes a processor core that generates memory write requests, and a cache memory with a memory controller having a memory pipeline. The cache memory has cache lines of length L. The cache memory has a minimum write length that is less than a cache line length of the cache memory. The memory pipeline determines whether the data payload includes a first chunk and ECC syndrome that correspond to a partial write and are writable by a first cache write operation, and a second chunk and ECC syndrome that correspond to a full write operation that can be performed separately from the first cache write operation. The memory pipeline performs an RMW operation to store the first chunk and ECC syndrome in the cache memory, and performs the full write operation to store the second chunk and ECC syndrome in the cache memory.
    Type: Grant
    Filed: May 14, 2020
    Date of Patent: November 1, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Abhijeet Ashok Chachad, Timothy David Anderson, David Matthew Thompson, Daniel Brad Wu
  • Patent number: 11481125
    Abstract: A storage device includes a first interface, an operation circuit, and a nonvolatile memory. The first interface receives a first data chunk from a host device. The operation circuit generates first processed data by processing the first data chunk and generates a first signal indicating a size of the first processed data. The nonvolatile memory stores the first processed data in a storage location, when the storage location at which the first processed data are to be stored is designated to the storage device based on the first signal. The first interface outputs the first signal to the host device.
    Type: Grant
    Filed: September 14, 2020
    Date of Patent: October 25, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yohan Ko, Dong-Uk Kim, Insoon Jo, Jooyoung Hwang
  • Patent number: 11461044
    Abstract: According to one embodiment, a nonvolatile memory device includes a memory cell array, first and second storage units, and control unit. The memory cell array includes erase unit areas. The first storage units correspond respectively to the erase unit areas and store items of first information indicating whether a first usage restriction is to be imposed on the corresponding erase unit areas. The second storage units correspond respectively to the erase unit areas and store items of second information indicating whether a second usage restriction is to be imposed on the corresponding erase unit areas. The control unit executes switching control on whether the first usage restriction is to be imposed or not and whether the second usage restriction is to be imposed or not on the memory cell array based on the first and second information.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: October 4, 2022
    Assignee: Kioxia Corporation
    Inventor: Tomoya Hiraishi