Abstract: A master-slave processor interface protocol transfers a plurality of instructions from a master processor to a slave processor. Each instruction has an opcode and a set of operands. The interface includes a micro-engine which sends the opcode for each of the instructions to be executed to the slave processor and stores the opcode in a first buffer in the slave processor. A second micro-engine operates the master processor to fetch and process the set of operands for each of the instructions to be executed by the slave processor in the order of the opcode delivery to the first buffer. A third micro-engine delivers a signal to the slave processor when the master processor is ready to deliver the operands for an instruction. The opcode associated with the operands ready to be delivered is then moved from the first buffer to a second buffer upon receiving the signal from the master processor. The processed set of operands are then sent to the second buffer and the instruction is executed.

Abstract: A method of memory access for sharing a memory between multiple processors. The memory comprises a plurality of sections and each section is connected to each processor by a memory path. Each section includes a plurality of subsections and each subsection includes a plurality of banks which includes a plurality of individually addressable memory locations. Memory references attempting to access the individually addressable memory locations are generated by the processors. Subsection conflicts between the memory references generated by a plurality of ports of each processor are resolved so that only one of the memory references from each processor is allowed to access one of the plurality of subsections at a time. Section conflicts between the memory references generated by the plurality of ports of each processor are resolved so that only one of the plurality of ports of each processor connects by the memory path for each processor to one of the plurality of the sections at a time.

Abstract: Method and apparatus for sequentially executing a plurality of pipelined instruction words of a program in which each instruction has independently selectable execution cycle count latencies. After the occurrence of an exception, instructions are identified which began after the instruction that caused the exception, and which have completed execution before execution of the exception provoking instruction was inhibited. Detection of an exception causes the processor to inhibit further execution of the exception provoking instruction. Pending instructions, which have yet to complete their execution prior to the inhibition of the exception provoking instruction, are similarly inhibited from further execution. Subsequently, the exception is serviced and the exception inducing instruction is restarted for re-execution in the processor.

Abstract: A computer program to be compiled is optimized prior to carrying out the final compilation. Subgraphs within the program are identified and examined for optimization beginning with the entire program as the largest subgraph. The number of entities in each subgraph which are relevant to each dimension of arrays used to represent data flow equations is determined. Next, the amount of memory required to contain the arrays is determined. If that memory requirement is within a predefined memory usage limit for the compilation, then a specified procedure of the compilation process is applied. If the memory requirement to contain the arrays exceeds the predefined memory usage limit for the compilation, the process is repeated for successively smaller subgraphs within the program in an attempt to find a subgraph to which the memory limits allow application of the specified procedure.

Abstract: Apparatus for enabling a first processor to cause a second processor to effect a transfer of data between the processors in accordance with data transfer commands sent from the first processor to the second processor is described. The processors each have a program instruction memory for enabling the processors to operate independently and simultaneously when no data transfer is occurring between them, and the apparatus includes data transfer circuitry connected between the processors for enabling the data to be transferred, a program instruction decoder associated with the second processor for normally decoding and executing instructions stored in the program instruction memory of the second processor when no data transfer is occurring, and routing circuitry for carrying the data transfer commands from the first processor to the program instruction decoder for decoding to provide signals to the data transfer circuitry to effect a transfer of data.

Abstract: In a multitasking, multiuser computer system, a server process temporarily impersonates the characteristics of a client process when the client process preforms a remote procedure call on the server process. Each process has an identifier list with a plurality of identifiers that characterize the process. The server process generates a new identifier list which is either the same as the client process's list, or is the union of the server's and the client's lists. Each object in the system can have an access control list which defines the identifiers that a process must have in order to access the object. The operation system has access checking software for enabling a selected process access to a specified object when the identifers for the process match the list of identifiers in the access control list of the specified object. The server can therefore access all objects accessible to the client while the server is working for the client.

Abstract: An assembler system translates a source program having a plurality of source code modules. The source code modules are evaluated in order to identify which source code module is the first source code module for which:(1) an object code module has not been assembled,(2) the source code module production time is later than the corresponding object code module production time, or(3) the source code module is positioned differently than it is in a recorded order.This first identified source code module, and the source code modules succeeding it, are assembled in accordance with the current assemble order.

Abstract: A system has a shared resource, such as a bus or memory, with which various devices may communicate upon a request being granted by an arbiter. In order to reduce the arbitration time, the arbiter is comprised of a state machine and latch which run asynchronously. Consequently, once one request has been granted and acted upon, the state machine will commence arbitration for any remaining requests.

Abstract: A data control system includes an external memory unit for storing data, a volatile memory for storing at-least-once accessed data from the external memory unit, a nonvolatile memory for storing frequently-accessed pieces of data among the data stored in the volatile memory, and a memory control unit for controlling the external memory unit and the nonvolatile memory. The frequently-accessed data is stored in the nonvolatile memory, so that when the system is powered down, the nonvolatile memory does not lose the frequently-accessed data. When the power is on, the frequently-accessed data can be again accessed rapidly.

Abstract: A clock pulse generator for a one-chip microprocessor permits the microprocessor to be operated on two different power sources by effectively using a single source of clock pulses, a clock pulse divider and gate circuits to gate a specific sequence of pulses to the microprocessor. The period of a slowest clock pulse signal after division is integrally related to the periods of the faster clock pulse signals so that the pulse signals are synchronously provided.

Abstract: A process controls the routing of an arriving job in a job stream through a switch to one of a plurality of processing stations. At predetermined time intervals, occupancy factors associated with the stations are computed as determined by station configuration information and job stream information. Upon the arrival of an incoming job, the occupancy factors corresponding to the current processing status of the stations are used to compute station utilization values. The station having the minimum utilization value is selected to receive and process the incoming job provided this minimum value is less than a preselected threshold; otherwise, the incoming job is denied processing permission.

Abstract: An architecture for a dynamic video random access memory on a single integrated circuit chip having internal circuitry for performing drawing or replacement rule logical operations on an addressed line of stored video information in the RAM and further having the write masking circuitry for modifying selected portions of the line of stored video information between selected START and STOP bit locations within the line.

Abstract: A data input device for an electronic data processing device such as a personal computer includes an input keyboard, which has a key field, a casing and a plug-in receptacle for a keyboard plug on a circuit connector; and a connector, such as a junction cable, which has a keyboard plug which fits into the receptacle on the keyboard, a circuit connector which is a connection wire, a plug at the end of the connection wire connecting with the electronic data processing device, and programmable encoder electronics for encoding unique signals corresponding to each key in the key field on the keyboard. A portion of the encoder electronics, in which the program relating the keyboard to the electronic data processing device is encoded, is located within the keyboard plug and not within the keyboard itself.

Abstract: A computer system shares memory between multiple processors by dividing the memory into a plurality of sections, subsections, and banks, and by providing a memory path between each processor and each section of memory. Each processor may generate references to the memory from any one of four ports, which are multiplexed to the memory paths and onto the sections of memory. The system provides that each processor has an associated register in each subsection of memory and that each processor can make no more than one reference to a subsection at a time. Reference conflict resolution means are provided at the processor level to arbitrate conflicts between ports in the processors attempting to reference the same section or subsection in the memory. Reference conflict resolution means are provided at the subsection level of the memory to arbitrate conflicts between different processors attempting to reference the same banks of memory.

Abstract: The method allows for the loading of operating systems between computers over a network, thereby drastically decreasing the amount of time required to download an operating system or update an operating system. A root directory is created and a subset of the operating system is loaded into the memory of the computer which is to receive the operating system, thereby eliminating the need to access or use the disk during the operating system download process. The subset of the operating system contains the basic commands for file creation and manipulation, directory creation and network communication. The computer system is then started using the subset of the operating system located in memory and connected to the network. Once the computer is connected to the network, the files comprising the operating system to be downloaded are copied and transferred from a remote computer over the network and stored on the disk drive of the receiving computer.

Abstract: A method of monitoring patient data generates an optimal overview. The patient data is sensed by appropriate sensors and displayed as parameter values assigned to individual organ systems. A data field contains a plurality of parameter values and overview graphic images referring to organ systems are formed from this data field with the aid of a network switch and are displayed in response to a retrieval command.

Abstract: A least-recently-used (LRU) circuit determines a replaceable term needed for storing data newly loaded from cache memory for example. The circuit comprises a recently-used information storing means relating to the top priority order or the subordinative order among plural terms, and a least-recently-used determining means for determining which is the top priority term or the subordinative term in accordance with information stored in the recently-used information storing means. High speed processing is thus possible by simplified logical construction. Also, the circuit is provided with control means which directly or indirectly select the predetermined replaceable term, in situations where the determining means cannot properly determine the top-priority replaceable term. Therefore, even when the top-priority replaceable term is selected directly or indirectly, the cache memory can be securely prevented from discontinuing its own functional operation.

Abstract: A computer interconnect coupler has channel transmitters and channel receivers and logic circuitry for the routing of messages from the channel receivers which are addressed to the channel transmitters. When a message is received by a channel receiver, the channel receiver stores the beginning portion of the message in a first-in-first-out buffer, and sends a route message request to central switch logic. If the destination transmitter or receiver is busy, the central logic places the message request on a destination queue and returns a signal to the requesting source transmitter to turn on a flow control signal which is transmitted back to the data processing device having originated the message. Any message addressed to this data processing device, however, is inserted into the flow control carrier with pauses both before and after the message, and provisions are also made to allow the data processing device to return an acknowledgment responsive to the incoming message.

Abstract: A control method for processing elements (PE) in a parallel processing system, such as an array processor, in which data processing is carried out with data transfer between the PEs, and wherein the data transfer between the PEs is performed simultaneously with the data operations in the PEs to improve the processing speed of the parallel processing system. Three buffer memories are respectively connected to a data input path from one data procesing apparatus, a data output path to another data processing apparatus, and data paths for transmitting data from or to the data operation unit in the data processing apparatus itself having these three buffer memories.

Abstract: A distributed office automation system includes workstations and support stations which are interconnected via a network and which make use of the functionality of one another by subcontracting tasks. Various function modules are available in the system for numerous tasks and the system provides a distributed organization structure in which it is always clear what function module is required to perform a specifc task. Each of the stations is provided with a coordination unit which is continually aware of the state of the total system and which designates the required function module.