Patents Examined by Matthew C Landau
  • Patent number: 11682747
    Abstract: An embodiment discloses an ultraviolet light emitting element including: a light emitting structure including a first conductive semiconductor layer, a second conductive semiconductor layer, an active layer disposed between the first conductive semiconductor layer and the second conductive semiconductor layer, and an etched region in which the first conductive semiconductor layer is exposed; a first insulating layer disposed on the light emitting structure and including a first hole which exposes a portion of the etched region; a first electrode electrically connected to the first conductive semiconductor layer; and a second electrode electrically connected to the second conductive semiconductor layer, wherein the light emitting structure includes an intermediate layer regrown on the first conductive semiconductor layer exposed in the first hole, the first electrode is disposed on the intermediate layer, the etched region includes a first etched region disposed at an inner side and a second etched region disp
    Type: Grant
    Filed: February 18, 2021
    Date of Patent: June 20, 2023
    Assignee: Photon Wave Co.. Ltd.
    Inventors: Youn Joon Sung, Seung Kyu Oh, Jae Bong So, Gil Jun Lee, Won Ho Kim, Tae Wan Kwon, Eric Oh, Il Gyun Choi, Jin Young Jung
  • Patent number: 11658231
    Abstract: A semiconductor device having a semiconductor module. The semiconductor module includes first and second conductor layers facing each other, a first semiconductor element provided between the first and second conductor layers, positive and negative electrode terminals respectively provided on edge portions of the first and second conductor layers at a first side of the semiconductor module in a top view of the semiconductor module, control wiring that is electrically connected to the first control electrode, and that extends out of the first and second conductor layers at a second side of the semiconductor module that is opposite to the first side in the top view, and a control terminal that is electrically connected to the control wiring, that is positioned outside the first and second conductor layers in the top view, and that has an end portion that is aligned with the positive and negative electrode terminals.
    Type: Grant
    Filed: October 30, 2020
    Date of Patent: May 23, 2023
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Motohito Hori, Yoshinari Ikeda, Akira Hirao, Tsunehiro Nakajima
  • Patent number: 11658194
    Abstract: An image sensor may include a semiconductor substrate having a light receiving surface thereon and a plurality of spaced-apart semiconductor photoelectric conversion regions at adjacent locations therein. A grating structure is provided on the light receiving surface. This grating structure extends opposite each of the plurality of spaced-apart photoelectric conversion regions. An optically-transparent layer is provided on the grating structure. This grating structure includes a plurality of spaced-apart grating patterns, which can have the same height and the same width. In addition, the grating patterns may be spaced apart from each other by a uniform distance. The grating structure is configured to selectively produce ±1 or higher order diffraction lights to the photoelectric conversion regions, in response to light incident thereon.
    Type: Grant
    Filed: February 27, 2019
    Date of Patent: May 23, 2023
    Inventors: Wook Lee, Euiyoung Song, Kwanghee Lee, Uihui Kwon, Jae Ho Kim, Jungchak Ahn
  • Patent number: 11658261
    Abstract: A method of manufacturing a nitride semiconductor device includes: forming a first semiconductor layer containing Al, Ga, and N and having a first thickness by doping a p-type impurity; forming a second semiconductor layer over the first semiconductor layer without doping an n-type impurity and without doping a p-type impurity, the second semiconductor layer containing Al and N and having a second thickness; and heat treating the first semiconductor layer and the second semiconductor layer. The second thickness is less than the first thickness. T band gap energy of the second semiconductor layer is greater than a band gap energy of the first semiconductor layer. After the heat treating of the first semiconductor layer and the second semiconductor layer, the second semiconductor layer contains the p-type impurity by diffusion of the p-type impurity from the first semiconductor layer.
    Type: Grant
    Filed: December 15, 2020
    Date of Patent: May 23, 2023
    Assignee: NICHIA CORPORATION
    Inventors: Masahiro Noguchi, Hideyuki Gono
  • Patent number: 11652134
    Abstract: A first component with a first sidewall and a second component with a second sidewall may be mounted onto an expandable film such that an original distance X is the distance between the first sidewall and the second sidewall. The expandable film may be expanded such that an expanded distance Y is the distance between the first sidewall and the second sidewall and expanded distance Y is greater than original distance X. A first sidewall material may be applied within at least a part of a space between the first sidewall and the second sidewall. The expandable film may be expanded such that a contracted distance Z is the distance between the first sidewall and the second sidewall, and contracted distance Z is less than expanded distance Y.
    Type: Grant
    Filed: June 3, 2022
    Date of Patent: May 16, 2023
    Assignee: Lumileds LLC
    Inventors: Tze Yang Hin, Yu-Chen Shen, Luke Gordon, Danielle Russell Chamberlin, Daniel Bernardo Roitman
  • Patent number: 11652097
    Abstract: A transient voltage suppression device includes a P-type semiconductor layer, a first N-type well, a first N-type heavily-doped area, a first P-type heavily-doped area, a second P-type heavily-doped area, and a second N-type heavily-doped area. The first N-type well and the second N-type heavily-doped area are formed in the layer. The first P-type heavily-doped area is formed in the first N-type well. The first P-type heavily-doped area is spaced from the bottom of the first N-type well. The second P-type heavily-doped area is formed within the first N-type well and spaced from the sidewall of the first N-type well. The second P-type heavily-doped area is formed between the first P-type heavily-doped area and the second N-type heavily-doped area.
    Type: Grant
    Filed: November 30, 2020
    Date of Patent: May 16, 2023
    Assignee: AMAZING MICROELECTRONIC CORP.
    Inventors: Tun-Chih Yang, Zi-Ping Chen, Kun-Hsien Lin
  • Patent number: 11646364
    Abstract: A power device which is formed on a semiconductor substrate includes: a lateral insulated gate bipolar transistor (LIGBT), a PN diode and a clamp diode. The PN diode is connected in parallel to the LIGBT. The clamp diode has a clamp forward terminal and a clamp reverse terminal, which are electrically connected to a drain and a gate of the LIGBT, to clamp a gate voltage applied to the gate not to be higher than a predetermined voltage threshold.
    Type: Grant
    Filed: February 26, 2021
    Date of Patent: May 9, 2023
    Assignee: RICHTEK TECHNOLOGY CORPORATION
    Inventors: Chih-Feng Huang, Lung-Sheng Lin
  • Patent number: 11646365
    Abstract: A short-circuit semiconductor component comprises a semiconductor body, in which a rear-side base region of a first conduction type, an inner region of a second conduction type complementary to the first conduction type, and a front-side base region of the first conduction type are disposed. The rear-side base region is electrically connected to a rear-side electrode with a rear-side electrode width, and the front-side base region is electrically connected to a front-side electrode with a front-side electrode width. A turn-on structure with a turn-on structure width is embedded into the front-side and/or rear-side base region and is covered by the respective electrode. The turn-on structure is configured to be turned on depending on a supplied turn-on signal and to produce, on a one-off basis, an irreversible, low-resistance connection between the two electrodes. The ratio of the turn-on structure width to the respective electrode width is less than 1.
    Type: Grant
    Filed: January 23, 2019
    Date of Patent: May 9, 2023
    Assignee: Infineon Technologies Bipolar GmbH & Co. KG.
    Inventors: Uwe Kellner-Werdehausen, Michael Stelte, Markus Droldner, Dirk Pikorz, Peter Weidner, Reiner Barthelmess, Mario Schenk, Jens Przybilla
  • Patent number: 11637225
    Abstract: A wavelength converting layer may have a glass or a silicon porous support structure. The wavelength converting layer may also have a cured portion of wavelength converting particles and a binder filling the porous glass or silicon support structure.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: April 25, 2023
    Assignee: Lumileds LLC
    Inventors: Grigoriy Basin, Mooi Guan Ng, Lex Alan Kosowsky, Phillip Barton
  • Patent number: 11631782
    Abstract: A method for etching a semiconductor structure (110) is provided, the semiconductor structure comprising a sub-surface quantum structure (30) of a first III-V semiconductor material,beneath a surface layer (31) of a second III-V semiconductor material having a charge carrier density of less than 5×1017 cm?3. The sub-surface quantum structure may comprise, for example, a quantum well, or a quantum wire, or a quantum dot. The method comprises the steps of exposing the surface layer to an electrolyte (130), and applying a potential difference between the first III-V semiconductor material and the electrolyte, to electrochemically etch the sub-surface quantum structure (30) to form a plurality of nanostructures, while the surface layer (31) is not etched. A semiconductor structure, uses thereof, and devices incorporating such semiconductor structures are further provided.
    Type: Grant
    Filed: January 25, 2019
    Date of Patent: April 18, 2023
    Assignee: CAMBRIDGE ENTERPRISE LIMITED
    Inventors: Rachel A. Oliver, Tongtong Zhu, Yingjun Liu, Peter Griffin
  • Patent number: 11631768
    Abstract: A semiconductor device includes a fin extending along a first direction over a substrate, and a gate structure extending in a second direction overlying the fin. The gate structure includes a gate dielectric layer overlying the fin, a gate electrode overlying the gate dielectric layer, and insulating gate sidewalls on opposing lateral surfaces of the gate electrode extending along the second direction. A source/drain region is formed in the fin in a region adjacent the gate electrode structure, and a stressor layer is between the source/drain region and the semiconductor substrate. The stressor layer includes GeSn or SiGeSn containing 1019 atoms cm?3 or less of a dopant, and a portion of the fin under the gate structure is a channel region.
    Type: Grant
    Filed: July 1, 2019
    Date of Patent: April 18, 2023
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Huang-Siang Lan, CheeWee Liu, Chi-Wen Liu, Shih-Hsien Huang, I-Hsieh Wong, Hung-Yu Yeh, Chung-En Tsai
  • Patent number: 11626352
    Abstract: A semiconductor device includes a semiconductor element, a mount portion, and a sintered metal bond. The semiconductor element includes a body and an electrode pad. The body has an obverse surface facing forward in a first direction and a reverse surface facing rearward in the first direction. The electrode pad covers the element reverse surface. The mount portion supports the semiconductor element. The sintered metal bond electrically bonds the electrode pad and the mount portion. The sintered metal bond includes a first rear edge and a first front edge spaced forward in the first direction from the first rear edge. The electrode pad includes a second rear edge and a second front edge spaced forward in the first direction from the second rear edge. The first front edge of the metal bond is spaced rearward in the first direction from the second front edge of the pad.
    Type: Grant
    Filed: July 25, 2018
    Date of Patent: April 11, 2023
    Assignee: ROHM CO., LTD.
    Inventor: Motoharu Haga
  • Patent number: 11626532
    Abstract: A method for forming a light emitting diode (LED) uses aluminum-based material layers and oxidation during the LED formation. In some embodiments, the method may include forming an n-type layer of the LED on a substrate, forming at least one sidewall restriction layer of the LED on the substrate with the sidewall restriction layer comprising an aluminum-based material, forming a quantum well layer of the LED on the substrate, forming a p-type layer of the LED on the substrate, exposing the substrate to water vapor, and heating the substrate to oxidize at least an outer portion of the electron blocking layer. The aluminum-based material may include aluminum indium nitride or aluminum gallium arsenide.
    Type: Grant
    Filed: January 6, 2021
    Date of Patent: April 11, 2023
    Assignee: APPLIED MATERIALS, INC.
    Inventor: Shiva Rai
  • Patent number: 11626548
    Abstract: A method for transferring electroluminescent structures onto a face, referred to as the accommodating face, of an accommodating substrate. The accommodating face is moreover provided with interconnections intended to individually address each of the structures. The electroluminescent structures are initially formed on a supporting substrate and are separated by tracks. It is then proposed in the present invention to form reflective walls, vertically above the tracks, which comprise a supporting polymer (the second polymer) supporting a metal film on its sides. Such an arrangement of reflective walls makes it possible to reduce the stresses exerted on the electroluminescent structures during the transfer method according to the present invention. Moreover, the reflective walls, within the meaning of the present invention, may be produced on all the electroluminescent structures resting on a supporting substrate.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: April 11, 2023
    Assignees: ALEDIA, COMMISSARIAT À L'ÉNERGIE ATOMIQUE ET AUX ÉNERGIES ALTERNATIVES
    Inventors: Marion Volpert, Vincent Beix, François Levy, Mario Ibrahim, Fabrice De Moro
  • Patent number: 11626540
    Abstract: A semiconductor light-emitting element includes: an n-type semiconductor layer; an active layer; a p-side contact electrode made of Rh; a p-side electrode covering layer made of Ti or TiN that covers the p-side contact electrode; a first protective layer made of SiO2 or SiON that covers an upper surface and a side surface of the p-side electrode covering layer in a portion different from that of a first p-side pad opening; a second protective layer made of Al2O3 that covers the first protective layer, a side surface of a p-side semiconductor layer, and a side surface of the active layer in a portion different from that of a second p-side pad opening; and a p-side pad electrode that is in contact with the p-side electrode covering layer in the first p-side pad opening and the second p-side pad opening.
    Type: Grant
    Filed: September 4, 2020
    Date of Patent: April 11, 2023
    Assignee: NIKKISO CO., LTD.
    Inventors: Noritaka Niwa, Tetsuhiko Inazu
  • Patent number: 11626531
    Abstract: A semiconductor body and a method for producing a semiconductor body are disclosed. In an embodiment a semiconductor body includes a p-conducting region, wherein the p-conducting region has at least one barrier zone and a contact zone, wherein the barrier zone has a first magnesium concentration and a first aluminum concentration, wherein the contact zone has a second magnesium concentration and a second aluminum concentration, wherein the first aluminum concentration is greater than the second aluminum concentration, wherein the first magnesium concentration is at least ten times less than the second magnesium concentration, wherein the contact zone forms an outwardly exposed surface of the semiconductor body, and wherein the barrier zone adjoins the contact zone, and wherein the semiconductor body is based on a nitride compound semiconductor material.
    Type: Grant
    Filed: August 24, 2018
    Date of Patent: April 11, 2023
    Assignee: OSRAM OLED GMBH
    Inventors: Massimo Drago, Alexander Frey, Joachim Hertkorn, Ingrid Koslow
  • Patent number: 11621367
    Abstract: A light-emitting diode (LED) device includes a light-emitting layer having a core-shell structure that comprises a first semiconductor layer, an active layer, and a second semiconductor layer; a passivation layer formed to cover at least a portion of a side surface and a portion of an upper surface of the second semiconductor layer; a first electrode formed on a portion of the passivation layer that is located on a side surface of the light-emitting layer, the first electrode electrically connected to the first semiconductor layer and including a reflective material; and a second electrode formed on a portion of the passivation layer that is located on an upper surface of the light-emitting layer, the second electrode contacting a portion of the upper surface of the second semiconductor layer that is exposed.
    Type: Grant
    Filed: July 20, 2020
    Date of Patent: April 4, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Junsik Hwang, Kyungwook Hwang
  • Patent number: 11610879
    Abstract: A handshake mechanism allows die discovery in a stacked die architecture that keeps inputs isolated until the handshake is complete. Power good indications are used as handshake signals between the die. A die keeps inputs isolated from above until a power good indication from the die above indicates presence of the die above. The die keeps inputs isolated from below until the die detects power is good and receives a power good indication from the die and the die below. In an implementation drivers and receivers, apart from configuration bus drivers and receivers are disabled until a fuse distribution done signal indicates that repairs have been completed. Drivers are then enabled and after a delay to ensure signals are driven, receivers are deisolated. A top die in the die stack never sees a power good indication from a die above and therefore keeps inputs from above isolated. That allows the height of the die stack to be unknown at power on.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: March 21, 2023
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Russell J. Schreiber, Richard M. Born, Carl D. Dietz, William A. Halliday
  • Patent number: 11605769
    Abstract: A light emitting element includes: a semiconductor layered structure; a first electrically insulating film covering surfaces of the semiconductor layered structure and defining a first opening in each of a first region and a second region of a first semiconductor layer, and defining a second opening in a portion above a second semiconductor layer; a first electrode electrically connected to the first semiconductor layer through each first opening; a second electrode electrically connected to the second semiconductor layer through the second opening; a first terminal located on the first electrode and electrically connected to the first electrode; a second terminal located on the second electrode and electrically connected to the second electrode; and a metal member located on a portion of the first electrically insulating film located over the second semiconductor layer and electrically insulated from the first terminal and the second terminal.
    Type: Grant
    Filed: July 16, 2021
    Date of Patent: March 14, 2023
    Assignee: NICHIA CORPORATION
    Inventor: Hiroaki Kageyama
  • Patent number: 11600611
    Abstract: An electronic device can include a drain terminal, a control terminal, and a source terminal, a first HEMT, and a second HEMT. The first HEMT can include a drain electrode coupled to the drain terminal, a gate electrode coupled to the first control terminal, and a source electrode coupled to the source terminal. The second HEMT can include a drain electrode, a gate electrode, and a source electrode. The drain electrode can be coupled to the drain terminal, and the source electrode can be coupled to the source terminal. In an embodiment, a resistor can be coupled between the gate and source electrodes of the second HEMT, and in another embodiment, the gate electrode of the second HEMT can electrically float. During or after a triggering event, the second HEMT can turn on temporarily to divert some of the charging from the triggering event into the second HEMT.
    Type: Grant
    Filed: November 12, 2020
    Date of Patent: March 7, 2023
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Jaume Roig-Guitart