Patents Examined by Matthew C Landau
  • Patent number: 10388649
    Abstract: A semiconductor device includes a semiconductor substrate having a first conductivity type, wherein the semiconductor substrate includes a first region and a second region. The semiconductor device also includes a buried layer disposed in the first region of the semiconductor substrate and having the first conductivity type, wherein the buried layer has a dopant concentration that is greater than that of the semiconductor substrate. The semiconductor device further includes an epitaxial layer disposed on the semiconductor substrate, and a first element disposed on the first region of the semiconductor substrate, wherein the first element includes a bipolar-complementary metal oxide semiconductor (CMOS)-double diffused metal oxide semiconductor (DMOS) (BCD) transistor. In addition, the semiconductor device includes a second element disposed on the second region of the semiconductor substrate, wherein the second element includes an ultra-high voltage (UHV) transistor.
    Type: Grant
    Filed: October 4, 2017
    Date of Patent: August 20, 2019
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Chien-Wei Chiu, Shin-Cheng Lin, Yu-Hao Ho
  • Patent number: 10388681
    Abstract: The present disclosure relates to a solid-state image pickup apparatus and an electronic apparatus capable of preventing charges accumulated in a PD from being lost and suppressing reductions of an S/N and a dynamic range. The apparatus according to an embodiment of the present disclosure includes: a photoelectric conversion unit; a first holding unit that holds the charge transferred from the photoelectric conversion unit; a first transfer gate unit that controls the transfer of the charge; a charge drain unit that is a drain destination of the charge generated by the photoelectric conversion unit; a first drain gate unit that controls the transfer of the charge from the photoelectric conversion unit to the charge drain unit; and a second drain gate unit that connects the charge drain unit with a constant voltage source. The present disclosure can be applied to a CIS and an electronic apparatus provided with the CIS.
    Type: Grant
    Filed: September 14, 2015
    Date of Patent: August 20, 2019
    Assignee: Sony Semiconductor Solutions Corporation
    Inventor: Hiroyuki Ohri
  • Patent number: 10384931
    Abstract: An electronic device includes a substrate, a functional element that is arranged on the substrate, a terminal that is arranged on the substrate and that is electrically connected to the functional element, and a bonding wire that is connected to the terminal. The terminal has an alloy portion that is alloyed to the bonding wire at a connection portion between the terminal and the bonding wire, and the thickness of the terminal is larger than the thickness of the alloy portion. Moreover, the terminal is formed of the same material (silicon) as the functional element.
    Type: Grant
    Filed: September 27, 2016
    Date of Patent: August 20, 2019
    Assignee: Seiko Epson Corporation
    Inventor: Teruo Takizawa
  • Patent number: 10371658
    Abstract: A gas sensor includes a p-type semiconductor layer that contains copper or silver cations and contacts with detection target gas, a first electrode that is a Schottky electrode to the p-type semiconductor layer, a high-resistance layer that is provided between the p-type semiconductor layer and the first electrode such that the p-type semiconductor layer and the first electrode partly contact with each other and has resistance higher than that of each of the p-type semiconductor layer and the first electrode, and a second electrode that is an ohmic electrode to the p-type semiconductor layer.
    Type: Grant
    Filed: August 22, 2017
    Date of Patent: August 6, 2019
    Assignee: FUJITSU LIMITED
    Inventors: Satoru Momose, Osamu Tsuboi, Kazuaki Karasawa
  • Patent number: 10370247
    Abstract: A method for forming a contact to a layer of one or more molecular components that comprises depositing one or more nanoparticles on the layer of one or more molecular components. Each of at least a portion of the one or more nanoparticles bond with each of at least a portion of the one or more molecular components. When there is more than one nanoparticle, each of at least a portion of the one and more nanoparticles cross-link with at least one other of the one or more nanoparticles. The bonded and cross-linked nanoparticles form both a mechanical and electrical contact for the layer of molecular components. The contact may further act as protection and sealing layers to preserve the chemical integrity at ambient operation conditions and/or enable mass and ionic exchange.
    Type: Grant
    Filed: August 29, 2016
    Date of Patent: August 6, 2019
    Assignee: International Business Machines Corporation
    Inventors: Emanuel Loertscher, Marcel Mayor, Gabriel Fernando Puebla Hellman
  • Patent number: 10373982
    Abstract: A semiconductor device includes a oxide semiconductor layer, a gate electrode arranged above the oxide semiconductor layer, a gate insulation layer between the oxide semiconductor layer and the gate electrode, a first insulation layer arranged above the oxide semiconductor layer and arranged with a first aperture part, wiring including an aluminum layer arranged above the first insulation layer, the wiring being electrically connected to the oxide semiconductor layer via the first aperture part, a barrier layer including aluminum oxide above the first insulation layer, above the wiring and covering a side surface of the wiring, and an organic insulation layer arranged above the barrier layer.
    Type: Grant
    Filed: June 12, 2017
    Date of Patent: August 6, 2019
    Assignee: Japan Display Inc.
    Inventors: Toshinari Sasaki, Hajime Watakabe, Akihiro Hanada, Marina Shiokawa
  • Patent number: 10374145
    Abstract: A method for forming a memory device that includes providing a free layer of an alloy of cobalt (Co), iron (Fe) and boron (B) overlying a reference layer; and forming metal layer comprising a boron (B) sink composition atop the free layer. Boron (B) may be diffused from the free layer to the metal layer comprising the boron sink composition. At least a portion of the metal layer including the boron (B) sink composition is removed. A metal oxide is formed atop the free layer. The free layer may be a crystalline cobalt and iron alloy. An interface between the metal oxide and free layer can provide perpendicular magnetic anisotropy character.
    Type: Grant
    Filed: October 14, 2015
    Date of Patent: August 6, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Stephen L. Brown, Guohan Hu, Jonathan Z. Sun, Daniel C. Worledge
  • Patent number: 10367100
    Abstract: A semiconductor element capable of adjusting a barrier height ?Bn and performing zero-bias operation and impedance matching with an antenna for improving detection sensitivity of high-frequency RF electric signals, a method of manufacturing the same, and a semiconductor device having the same. In the semiconductor element, a concentration of InGaAs (n-type InGaAs layer) is intentionally set to be high over a range for preventing the “change of the barrier height caused by the bias” described above up to a deep degeneration range. An electron Fermi level (EF) increases from a band edge of InGaAs (n-type InGaAs layer) to a band edge of InP (InP depletion layer).
    Type: Grant
    Filed: August 13, 2015
    Date of Patent: July 30, 2019
    Assignee: NTT ELECTRONICS CORPORATION
    Inventors: Makoto Shimizu, Hiroki Itoh, Tadao Ishibashi, Isamu Kotaka
  • Patent number: 10357768
    Abstract: A method for fabricating an MEMS device includes providing a first substrate with a central region and a peripheral region, and forming a plurality of first openings in the peripheral region and a plurality of third openings in the central region by etching the first substrate from a front side. The depth of the first openings is larger than the depth of the third openings. The method further includes forming a photosensitive layer on the surfaces of the first openings and the third openings, bonding a second substrate to the front side of the first substrate, and forming a trench by etching the first substrate from a back side using a patterned mask layer as an etch mask. The trench has a concave bottom surface and exposes a portion of the photosensitive layer formed on the bottom surfaces of the first openings and the third openings.
    Type: Grant
    Filed: August 28, 2016
    Date of Patent: July 23, 2019
    Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventor: Chao Zheng
  • Patent number: 10347802
    Abstract: An optoelectronic component includes an optoelectronic semiconductor chip and an optical element, wherein the optical element includes a prism structure configured to split light emitted by the semiconductor chip into two beams and deflect the beams in a first direction relative to one another, and the optical element includes a beam deflecting structure configured to deflect both beams jointly in a second direction perpendicular to the first direction.
    Type: Grant
    Filed: November 12, 2015
    Date of Patent: July 9, 2019
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Michael Hirmer, Claus Jaeger
  • Patent number: 10340383
    Abstract: A semiconductor device includes a fin extending along a first direction over a substrate, and a gate structure extending in a second direction overlying the fin. The gate structure includes a gate dielectric layer overlying the fin, a gate electrode overlying the gate dielectric layer, and insulating gate sidewalls on opposing lateral surfaces of the gate electrode extending along the second direction. A source/drain region is formed in the fin in a region adjacent the gate electrode structure, and a stressor layer is between the source/drain region and the semiconductor substrate. The stressor layer includes GeSn or SiGeSn containing 1019 atoms cm?3 or less of a dopant, and a portion of the fin under the gate structure is a channel region.
    Type: Grant
    Filed: September 27, 2016
    Date of Patent: July 2, 2019
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Huang-Siang Lan, CheeWee Liu, Chi-Wen Liu, Shih-Hsien Huang, I-Hsieh Wong, Hung-Yu Yeh, Chung-En Tsai
  • Patent number: 10340389
    Abstract: The present disclosure discloses in embodiments a thin film transistor and a manufacturing method thereof, an array substrate. The thin film transistor comprises: a base substrate, an active layer, a source, a gate, and a drain. Two ends of the active layer are connected to the source and the drain, respectively. The gate comprises a top gate and a bottom gate arranged opposite to each other in a direction perpendicular to the base substrate, the top gate comprising a top gate top portion and a top gate side portion connected to the top gate top portion, the top gate side portion extending from the top gate top portion towards the base substrate. The active layer is sandwiched between the top gate top portion and the bottom gate. A sidewall of the active layer is at least partially surrounded by the top gate side portion.
    Type: Grant
    Filed: November 12, 2015
    Date of Patent: July 2, 2019
    Assignee: BOE Technology Group Co., Ltd.
    Inventors: Xiangyong Kong, Xiaming Zhu, Xiaodi Liu
  • Patent number: 10332873
    Abstract: An apparatus comprises an antifuse cell comprising first and second nodes, an antifuse element, and a transistor. The antifuse element and the transistor are coupled in series between the first and second nodes. The antifuse element comprises an antifuse gate. The transistor comprises a transistor gate comprising a substantially-annular structure substantially surrounding the antifuse gate.
    Type: Grant
    Filed: June 12, 2017
    Date of Patent: June 25, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Toshinao Ishii, Yasuhiko Tanuma
  • Patent number: 10325816
    Abstract: The present disclosure provides an embodiment of a fin-like field-effect transistor (FinFET) device. The device includes a substrate having a first gate region, a first fin structure over the substrate in the first gate region. The first fin structure includes an upper semiconductor material member, a lower semiconductor material member, surrounded by an oxide feature and a liner wrapping around the oxide feature of the lower semiconductor material member, and extending upwards to wrap around a lower portion of the upper semiconductor material member. The device also includes a dielectric layer laterally proximate to an upper portion of the upper semiconductor material member. Therefore the upper semiconductor material member includes a middle portion that is neither laterally proximate to the dielectric layer nor wrapped by the liner.
    Type: Grant
    Filed: June 29, 2017
    Date of Patent: June 18, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kuo-Cheng Ching, Ka-Hing Fung, Chih-Sheng Chang, Zhiqiang Wu
  • Patent number: 10325946
    Abstract: A packaging method and a package for an image sensing chip are provided. The packaging method includes: providing a wafer including a first surface and a second surface opposite to the first surface, where the wafer has multiple image sensing chips arranged in a grid, each of the image sensing chips has an image sensing region and contact pads arranged on a side of the first surface; forming an opening corresponding to each of the contact pads and cutting trenches on a side of the second surface of the wafer, where the contact pad is exposed through the opening; filling the cutting trenches with a first photosensitive ink; and applying a second photosensitive ink on the second surface of the wafer to cover the opening with the second photosensitive ink and form a hollow cavity in the opening.
    Type: Grant
    Filed: September 28, 2016
    Date of Patent: June 18, 2019
    Assignee: China Wafer Level CSP Co., Ltd.
    Inventors: Zhiqi Wang, Zhuowei Wang, Guoliang Xie
  • Patent number: 10325935
    Abstract: This disclosure discloses a display panel, a production method thereof, and a display apparatus. This method comprises: forming a pattern of a first metal layer on a base substrate and a pattern of a metal oxide conductive layer being electrically connected to the first metal layer by at least one through hole at a side of the first metal layer away from the base substrate; forming a reductive metal compound layer on a surface of the first metal layer at a side away from the base substrate before forming the pattern of the metal oxide conductive layer; treating the reductive metal compound layer and the metal oxide conductive layer after forming the pattern of the metal oxide conductive layer so that the reductive metal compound layer is oxidized into a second metal layer and metal particles are produced at the surface of the metal oxide conductive layer.
    Type: Grant
    Filed: July 13, 2018
    Date of Patent: June 18, 2019
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., HEFEI BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Dezhi Xu, Kui Gong
  • Patent number: 10312159
    Abstract: A method comprises providing a substrate of a first conductive type and a layer stack arranged on the substrate. The layer stack comprises a first isolation layer, a sacrificial layer, and a second isolation layer. The layer stack comprises a window formed in the layer stack through the second isolation layer, the sacrificial layer and the first isolation layer up to a surface region of the substrate. The method comprises providing a collector layer. The method comprises providing a base layer on the collector layer within the window of the layer stack. The method comprises providing an emitter layer or an emitter layer stack comprising the emitter layer on the base layer within the window of the layer stack. The method further comprises selectively removing the emitter layer or the emitter layer stack at least up to the second isolation layer.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: June 4, 2019
    Assignee: Infineon Technologies AG
    Inventors: Frank Hoffmann, Dirk Manger, Andreas Pribil, Marc Probst, Stefan Tegen
  • Patent number: 10312471
    Abstract: A method of manufacturing a display device including first electrodes provided for respective pixels, an insulating layer having openings respectively opposed to the first electrodes, an organic layer including a light emitting layer common to all the pixels, and a second electrode formed over an entire surface of the organic layer laminated on a first substrate, includes a step of forming an auxiliary wiring made of a metallic material layer by irradiating the metallic material layer with energy rays from a side of the metallic material layer and selectively removing the metallic material layer by energy absorbed by a part corresponding to the pixel after the metallic material layer has been formed on an entire surface of the second electrode.
    Type: Grant
    Filed: March 4, 2016
    Date of Patent: June 4, 2019
    Assignee: Sony Corporation
    Inventors: Hiroshi Fujimaki, Tomoyoshi Ichikawa
  • Patent number: 10304891
    Abstract: An image sensor includes a semiconductor material including a plurality of photodiodes disposed in the semiconductor material. The image sensor also includes a first insulating material disposed proximate to a frontside of the semiconductor material, and an interconnect disposed in the first insulating material proximate to the frontside of the semiconductor material. A metal pad extends from a backside of the semiconductor material through the first insulating material and contacts the interconnect. A metal grid is disposed proximate to the backside of the semiconductor material, and the semiconductor material is disposed between the metal grid and the first insulating material disposed proximate to the frontside.
    Type: Grant
    Filed: January 17, 2018
    Date of Patent: May 28, 2019
    Assignee: OmniVision Technologies, Inc.
    Inventors: Qin Wang, Gang Chen, Duli Mao
  • Patent number: 10304953
    Abstract: A semiconductor device includes stripe-shaped trench gate structures that extend in a semiconductor body along a first horizontal direction. Transistor mesas between neighboring trench gate structures include body regions and source zones, wherein the body regions form first pn junctions with a drift structure and second pn junctions with the source zones. The source zones directly adjoin two neighboring trench gate structures, respectively. Diode mesas that include at least portions of diode regions form third pn junctions with the drift structure. The diode mesas directly adjoin two neighboring trench gate structures, respectively. The transistor mesas and the diode mesas alternate at least along the first horizontal direction.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: May 28, 2019
    Assignee: Infineon Technologies AG
    Inventors: Thomas Aichinger, Dethard Peters, Ralf Siemieniec