Abstract: An optical semiconductor device includes: a mesa that is provided on a surface in a <011> direction of a semiconductor substrate having a (100) plane orientation and being of a first conductivity type, and includes a first cladding layer of the first conductivity type, an active layer, and a second cladding layer of a second conductivity type; a semi-insulating buried layer that buries both sides of the mesa, is provided on the semiconductor substrate, and includes a first region and a second region farther from the mesa than the first region; an insulation film provided on the first and second regions of the buried layer; and an electrode provided on the mesa and the insulation film on the first region; wherein a surface of the first region is at a height equal to or lower than a surface of the mesa, and lowers at farther distances from the mesa.

Abstract: In an embodiment, the optoelectronic semiconductor component (1) comprises a semiconductor layer sequence (2) with an active zone (22) for generating a radiation. On an bottom side (20) of the semiconductor layer sequence (2) there is an electrically insulating separation layer (3) with several openings (32). An adhesion-promoting layer (4) is located next to the openings (32) on a side of the separation layer (3) facing away from the semiconductor layer sequence (2). A continuous metallization layer (5) is located on a side of the adhesion-promoting layer (4) facing away from the semiconductor layer sequence (2). The semiconductor layer sequence (2) is electrically contacted in the openings (32) directly by the metallization layer (5). The metallization layer (5) and the openings (32) are spaced from the active zone (22) in the direction perpendicular to the separation layer (3).

Abstract: Described are light emitting diode (LED) devices comprising a plurality of mesas defining pixels, each of the plurality of mesas comprising semiconductor layers, an N-contact material in a space between each of the plurality of mesas, a dielectric material which insulates sidewalls of the P-type layer and the active region from the metal. Each of the mesas is spaced so that there is a pixel pitch in a range of from 10 ?m to 100 ?m and dark space gap between adjacent edges of p-contact layer. The dark space gap may be less than 20% of the pixel pitch. The dark space gap may be in a range of from 4 ?m to 10 ?m.

Abstract: A display device includes a first electrode disposed on a substrate, a first insulating film disposed on the first electrode and having a first opening formed, a second insulating film disposed on the first insulating film and having a second opening, and a contact electrode electrically contacting at least a portion of the first electrode through the first opening and the second opening, wherein a side surface of the first insulating film defines the first opening, and the second insulating film overlaps the side surface of the first insulating film such that the contact electrode and the first insulating film are not in contact with each other.

Abstract: Among multiple drain regions, a contact surface area between second contacts and a drain region most proximal to a central portion of an element region in a second direction is less than a contact surface area between second contacts and a drain region disposed on an outermost side of the element region in the second direction. The multiple drain regions are arranged in the second direction.

Abstract: Metal interconnect structures are reworked to address possible voids or other defects. Etching of initially deposited interconnect metal to open voids is followed by reflow to accumulate interconnect metal at the bottoms of trenches. Additional interconnect metal is deposited over the initially deposited interconnect metal by electroplating and/or electroless plating. Additional diffusion barrier material may be deposited and patterned prior to deposition of the additional interconnect material.

Abstract: An integrated circuit includes a T-coil circuit, a silicon-controlled rectifier (SCR), and a signal-loss prevention circuit. The T-coil circuit is coupled to an input/output (I/O) pad and an internal circuit. The SCR is coupled to the T-coil circuit and the internal circuit. The signal-loss prevention circuit is coupled to the T-coil circuit and the SCR. The signal-loss prevention circuit includes a resistor coupled to the T-coil circuit and the SCR. An electrostatic current flows through the resistor and turns on the SCR. The signal-loss prevention circuit may also include a diode circuit coupled to the T-coil circuit and the SCR. The diode circuit is configured to prevent signal loss.

Abstract: A silicon on insulator (SOI) device includes a wafer and a trap-rich layer. The wafer includes a top silicon layer disposed on a buried oxide layer. The trap-rich layer having nano-dots and an oxide layer are stacked on a high resistivity substrate sequentially, wherein the oxide layer is bonded with the buried oxide layer. Or, a silicon on insulator (SOI) device includes a wafer and a high resistivity substrate. The wafer includes a top silicon layer disposed on a buried oxide layer. The high resistivity substrate is bonded with the buried oxide layer, wherein a positive fixed charge layer is induced at a surface of the buried oxide layer contacting the high resistivity substrate, and a doped negative charge layer is right next to the positive fixed charge layer. The present invention also provides a method of forming said silicon on insulator (SOI) device.

Abstract: In a method for manufacturing a semiconductor device, a doped region is formed in a substrate from a first main surface. An insulating layer is formed over the doped region of the substrate. Contacts are formed in the insulating layer such that the contacts extend into the doped region. A portion of the substrate is removed from a second main surface. A trench, a first conductive line, and a second conductive line are formed from the doped region of the substrate through etching the substrate from the second main surface. The trench extends through the substrate to expose the insulating layer. The first and second conductive lines are spaced apart from each other by the trench. The contacts are positioned along and in contact with the first and second conductive lines. The trench is filled with a dielectric material.

Abstract: Aspects of the disclosure provide a method for fabricating semiconductor device. The method includes characterizing an etch process that is used to etch channel holes and dummy channel holes in a stack of alternating sacrificial gate layers and insulating layers upon a substrate of a semiconductor device. The channel holes are in a core region and the dummy channel holes are in a staircase region. The stack of alternating sacrificial gate layers and insulating layers extend from the core region into in the staircase region of a stair-step form. The method further includes determining a first shape for defining the dummy channel holes in a layout based on the characterization of the etch process. The first shape is different from a second shape for defining the channel holes.

Abstract: A nanorod light-emitting device is provided. The nanorod light-emitting device includes a first semiconductor layer, a light-emitting layer on the first semiconductor layer, a second semiconductor layer disposed on the light-emitting layer, at least one conductive layer disposed between a central portion of a lower surface of the light-emitting layer and the first semiconductor layer, or between a central portion of an upper surface of the light-emitting layer and the second semiconductor layer, at least one current blocking layer that surrounds a side surface of the at least one conductive layer, and an insulating film that surrounds a side surface of the second semiconductor layer, a side surface of the light-emitting layer, and a side surface of the at least one current blocking layer.

Abstract: A wavelength-converting member includes a wavelength-converting layer, a heat-dissipating component, and a securing member. The wavelength-converting layer has an upper surface, a lower surface, and one or more lateral surfaces with each of the one or more lateral surfaces of the wavelength-converting layer defining an inclined surface inclined at an acute angle with respect to the lower surface of the wavelength-converting layer. The wavelength-converting layer includes a thermally conductive part, and a fluorescent material containing part in contact with the thermally conductive part. The wavelength-converting layer is mounted on the heat-dissipating component. The securing member is secured to the heat-dissipating component. The securing member presses the inclined surface of each of the one or more lateral surfaces such that the wavelength-converting layer is secured to the heat-dissipating component.

Abstract: A system having an auxiliary plasma source, disposed proximate the workpiece, for use with an ion beam is disclosed. The auxiliary plasma source is used to create ions and radicals which drift toward the workpiece and may form a film. The ion beam is then used to provide energy so that the ions and radicals can process the workpiece. Further, various applications of the system are also disclosed. For example, the system can be used for various processes including deposition, implantation, etching, pre-treatment and post-treatment. By locating an auxiliary plasma source close to the workpiece, processes that were previously not possible may be performed. Further, two dissimilar processes, such as cleaning and implanting or implanting and passivating can be performed without removing the workpiece from the end station.

Abstract: The embodiments herein describe a vertical field effect transistor (FET) with a gate that includes different work function metals (WFMs). Each WFM can be made up of one material (or one layer) or multiple materials forming multiple layers. In any case, the gate includes at least two different WFMs. For example, a first WFM may have a different material or layer than a second WFM in the gate, or one layer of the first WFM may have a different thickness than a corresponding layer in the second WFM. Having different WFMs in the gate can reduce the gate induced drain leakage (GIDL) in the FET.

Abstract: The present disclosure describes a method for the formation of gate-all-around nano-sheet FETs with tunable performance. The method includes disposing a first and a second vertical structure with different widths over a substrate, where the first and the second vertical structures have a top portion comprising a multilayer nano-sheet stack with alternating first and second nano-sheet layers. The method also includes disposing a sacrificial gate structure over the top portion of the first and second vertical structures; depositing an isolation layer over the first and second vertical structures so that the isolation layer surrounds a sidewall of the sacrificial gate structure; etching the sacrificial gate structure to expose each multilayer nano-sheet stack from the first and second vertical structures; removing the second nano-sheet layers from each exposed multilayer nano-sheet stack to form suspended first nano-sheet layers; forming a metal gate structure to surround the suspended first nano-sheet layers.

Abstract: A display apparatus includes an upper substrate including a first area corresponding to a first light-emitting device; a second-color color filter layer on a lower surface of the upper substrate and including a first opening exposing the first area; a first-color color filter layer including a portion filling the first opening and a portion on a lower surface of the second-color color filter layer; a bank between the first-color and second-color color filter layers and a lower substrate, the bank including a second opening corresponding to the first area; and a first-color quantum dot layer filling the second opening, wherein the second opening includes a portion overlapping the first opening and a portion outside the first opening in a plan view.

Abstract: An organic light-emitting display device comprises a substrate, a driving thin-film transistor including an active layer on the substrate, source and drain electrodes directly contacting the active layer, and a gate electrode on the active layer, and an organic light-emitting element connected to the driving thin-film transistor. Each of the source and drain electrodes of the driving thin-film transistor exposes a respective side surface of the active layer.

Abstract: An LED wafer includes LED dies on an LED substrate. The LED wafer and a carrier wafer are joined. The LED wafer that is joined to the carrier wafer is shaped. Wavelength conversion material is applied to the LED wafer that is shaped. Singulation is performed to provide LED dies that are joined to a carrier die. The singulated devices may be mounted in an LED fixture to provide high light output per unit area.

Abstract: A semiconductor capacitor array layout includes a first conductive structure and a second conductive structure. The first conductive structure includes: longitudinal first conductive strips in a first integrated circuit (IC) layer; and lateral first conductive strips that are in a second IC layer and coupled to the longitudinal first conductive strips. The longitudinal and lateral first conductive strips jointly form well-shaped structures including outer wells and inner wells. The outer wells are not electrically coupled to the inner wells. The second conductive structure includes second conductors that are respectively disposed in the well-shaped structures in the first IC layer. The second conductors include outer second conductors respectively positioned in the outer wells and inner second conductors respectively positioned in the inner wells. The outer second conductor are not electrically coupled to the inner second conductor.

Abstract: An ESD protection device (100) is disclosed. More particularly, the ESD protection device is configured so that a gate electrode (140) and a capacitor electrode (170) electrically connected to a drain region (162) are spaced apart from each other by a preset distance, and partially or entirely overlap each other, thereby increasing a capacitance (Cgd) between the gate electrode and the drain region.