Patents Examined by Matthew C Landau
  • Patent number: 12224382
    Abstract: A display device may include: a substrate; first and second electrode on the substrate; light emitting element between the first and second electrodes; a barrier structure on the substrate and including a first surface, a second surface, and a third surface; a light conversion layer on the barrier structure; and a passivation layer on the light conversion layer. A first space defined by the second and third surfaces may be between the substrate and the barrier structure. A second space defined by the first and second surfaces may be between the barrier structure and the passivation layer. The first and second spaces may be alternately located in the first direction. The light emitting element may be in the first space. The light conversion layer may be in the at least one second space.
    Type: Grant
    Filed: February 10, 2023
    Date of Patent: February 11, 2025
    Assignee: Samsung Display Co., Ltd.
    Inventors: Kwang Soo Bae, Beom Soo Park, Min Jeong Oh, Young Je Cho
  • Patent number: 12211956
    Abstract: A radiation-emitting component is specified with—a carrier which has a top surface a radiation-emitting semiconductor chip arranged on the top surface of the carrier and configured to generate primary electromagnetic radiation, a first reflector layer arranged above a top surface of the semiconductor chip, and a cover body arranged between the first reflector layer and the radiation-emitting semiconductor chip, wherein a side surface of the cover body is inclined to the top surface of the carrier. Furthermore, a method for producing such a radiation-emitting component is specified.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: January 28, 2025
    Assignee: OSRAM OLED GMBH
    Inventors: Andreas Reith, Rainer Bradl, Ulrich Streppel, Thomas Birke
  • Patent number: 12211921
    Abstract: Aspects of the disclosure provide a method for forming a fin field effect transistor (FinFET) incorporating a fin top hardmask on top of a channel region of a fin. Because of the presence of the fin top hardmask, a gate height of the FinFET can be reduced without affecting proper operations of vertical gate channels on sidewalls of the fin. Consequently, parasitic capacitance between a gate stack and source/drain contacts of the FinFET can be reduced by lowering the gate height of the FinFET.
    Type: Grant
    Filed: January 14, 2022
    Date of Patent: January 28, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Cheng Ching, Kai-Chieh Yang, Ching-Wei Tsai, Kuan-Lun Cheng, Chih-Hao Wang
  • Patent number: 12211960
    Abstract: A micro LED display device includes an epitaxial structure layer, a connection layer, a light conversion layer and a transparent layer. The epitaxial structure layer includes a plurality of micro LEDs disposed apart from each other. The connection layer is disposed at one side of the epitaxial structure layer away from the micro LEDs. The light conversion layer is fixed on the epitaxial structure layer through the connection layer and includes a plurality of light conversion portions. Each of the light conversion portions corresponds to one of the micro LEDs. The transparent layer is disposed at one side of the light conversion layer away from the epitaxial structure layer. The ratio of the thickness of the transparent layer to the width of each light conversion portion is between 0.1 and 40. A manufacturing method of the micro LED display device is also provided.
    Type: Grant
    Filed: November 3, 2021
    Date of Patent: January 28, 2025
    Assignee: PLAYNITRIDE DISPLAY CO., LTD.
    Inventors: Yen-Yeh Chen, Yu-Jui Tseng, Sheng-Yuan Sun, Loganathan Murugan, Po-Wei Chiu
  • Patent number: 12213323
    Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a first and second transistors arranged over a substrate. The first transistor includes first channel structures extending between first and second source/drain regions. A first gate electrode is arranged between the first channel structures, and a first protection layer is arranged over a topmost one of the first channel structures. The second transistor includes second channel structures extending between the second source/drain region and a third source/drain region. A second gate electrode is arranged between the second channel structures, and a second protection layer is arranged over a topmost one of the second channel structures. The integrated chip further includes a first interconnect structure arranged between the substrate and the first and second channel structures, and a contact plug structure coupled to the second source/drain region and arranged above the first and second gate electrodes.
    Type: Grant
    Filed: August 9, 2023
    Date of Patent: January 28, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuan-Liang Liu, Sheng-Chau Chen, Chung-Liang Cheng, Chia-Shiung Tsai, Yeong-Jyh Lin, Pinyen Lin, Huang-Lin Chao
  • Patent number: 12206045
    Abstract: Provided is a light emitting device including a buffer layer, a body provided on the buffer layer, the body including a first semiconductor layer, an active layer, and a second semiconductor layer, a reflective layer configured to reflect light incident from the active layer, and a scattering pattern provided between the first semiconductor layer and the buffer layer, the scattering pattern being configured to scatter the light incident from the active layer and light incident from the reflective layer.
    Type: Grant
    Filed: September 17, 2021
    Date of Patent: January 21, 2025
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dongho Kim, Kyungwook Hwang
  • Patent number: 12183848
    Abstract: A light emitting device including a substrate, a first conductivity-type semiconductor layer, a mesa including a second conductivity-type semiconductor layer and an active layer, first and second contact electrodes respectively contacting the first and second conductivity-type semiconductor layers, a passivation layer covering the first and second contact electrodes, the mesa, and including first and second openings, and first and second bump electrodes electrically connected to the first and second contact electrodes through the first and second openings, respectively, in which the first and second bump electrodes are disposed on the mesa, the passivation layer is disposed between the first bump electrode and the second contact electrode, the first contact electrode includes a reflective material, and a portion of the first opening is surrounded with a side surface of the mesa, and another portion of the first opening is not surrounded with the side surface of the mesa.
    Type: Grant
    Filed: October 12, 2022
    Date of Patent: December 31, 2024
    Assignee: Seoul Viosys Co., Ltd.
    Inventors: Seong Kyu Jang, Hong Suk Cho, Kyu Ho Lee, Chi Hyun In
  • Patent number: 12165729
    Abstract: A semiconductor device includes logic circuitry including a transistor disposed over a substrate, multiple layers each including metal wiring layers and an interlayer dielectric layer, respectively, disposed over the logic circuitry, and memory arrays. The multiple layers of metal wiring include, in order closer to the substrate, first, second, third and fourth layers, and the memory arrays include lower multiple layers disposed in the third layer.
    Type: Grant
    Filed: July 1, 2022
    Date of Patent: December 10, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hung-Li Chiang, Yu-Sheng Chen, Chao-Ching Cheng, Tzu-Chiang Chen
  • Patent number: 12136449
    Abstract: A capacitor is provided. The capacitor includes a substrate, at least two conductive plates formed in the substrate and extending into the substrate, at least one insulating structure formed between two adjacent conductive plates of the at least two conductive plates and extending into the substrate, and a plurality of contacts, each extending into respective one of the at least two conductive plates.
    Type: Grant
    Filed: December 14, 2021
    Date of Patent: November 5, 2024
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventors: Liang Chen, Cheng Gan, Xin Wu, Wei Liu
  • Patent number: 12136684
    Abstract: A method for manufacturing a light emitting apparatus according to an aspect of the present disclosure includes forming a light emitting section on a substrate, the light emitting section including a group of columnar sections formed of a plurality of columnar sections each including a light emitting layer, forming a first insulating layer on the substrate so as to cover the light emitting section, etching the tip of a protrusion-shaped section that contains the same substance as the substance of which the light emitting section is made and protrudes beyond the first insulating layer, forming a second insulating layer on the first insulating layer, and forming an electrode to be electrically coupled to the light emitting section on the second insulating layer.
    Type: Grant
    Filed: November 29, 2021
    Date of Patent: November 5, 2024
    Assignee: SEIKO EPSON CORPORATION
    Inventor: Takashi Miyata
  • Patent number: 12129572
    Abstract: There is provided a nitride semiconductor template, including: a substrate having a front surface and a back surface opposite to the front surface; a back side semiconductor layer provided on a back surface side of the substrate, comprising a polycrystalline group III nitride semiconductor, and having a linear expansion coefficient different from a linear expansion coefficient of the substrate; and a front side semiconductor layer provided on a front surface side of the substrate, comprising a monocrystalline group III nitride semiconductor, and having a linear expansion coefficient different from a linear expansion coefficient of the substrate, wherein a thickness of the front side semiconductor layer is a thickness exceeding a critical thickness at which cracks are generated in the front side semiconductor layer when only the front side semiconductor layer is formed without forming the back side semiconductor layer.
    Type: Grant
    Filed: January 24, 2017
    Date of Patent: October 29, 2024
    Assignee: SUMITOMO CHEMICAL COMPANY, LIMITED
    Inventors: Hajime Fujikura, Taichiro Konno
  • Patent number: 12125942
    Abstract: A semiconductor light emitting device is provided. The device includes a light emitting structure stack including a first conductive semiconductor layer, a second conductive semiconductor layer, and an active layer arranged between the first conductive semiconductor layer and the second conductive semiconductor layer; a first electrode electrically connected to the first conductive semiconductor layer; a second electrode electrically connected to the second conductive semiconductor layer; and a field control structure on a sidewall of the light emitting structure stack, the field control structure including a field control electrode on a sidewall of the active layer; and a dielectric layer between the field control electrode and the active layer.
    Type: Grant
    Filed: June 21, 2021
    Date of Patent: October 22, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Youngjo Tak, Joosung Kim, Jonguk Seo, Sungjin Ahn, Donggun Lee, Jeongwook Lee, Youngjin Choi, Yongseok Choi, Jonghoon Ha
  • Patent number: 12113154
    Abstract: A display device includes a substrate including pixels; a first electrode and a second electrode that are spaced apart from each other on the substrate; a light emitting element disposed between the first electrode and the second electrode; a first connection electrode electrically contacting the first electrode and a first end of the light emitting element; a second connection electrode electrically contacting the second electrode and another end of the light emitting element; and an organic pattern disposed between the first connection electrode and the second connection electrode and on the light emitting element. The organic pattern tapers toward the light emitting element.
    Type: Grant
    Filed: July 28, 2021
    Date of Patent: October 8, 2024
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Su Jeong Kim, Yi Seop Shim, Yun Ho Lee
  • Patent number: 12113091
    Abstract: A LED structure includes a substrate, a first semiconductor layer, a second semiconductor layer, and a color conversion layer. The first semiconductor layer is formed on the substrate, and the first semiconductor layer includes a first LED unit and a second LED unit formed therein. The first LED unit and the second LED unit emit light of a first color. The second semiconductor layer is formed above the first semiconductor layer, and the second semiconductor layer includes a third LED unit formed therein. The third LED unit emits light of a second color different from the first color. The color conversion layer is formed on the first LED unit to convert light of the first color to light of a third color different from the first color and the second color.
    Type: Grant
    Filed: April 29, 2021
    Date of Patent: October 8, 2024
    Assignee: Raysolve Optoelectronics (Suzhou) Company Limited
    Inventor: Wing Cheung Chong
  • Patent number: 12107144
    Abstract: Incorporation of metallic quantum dots (e.g., silver bromide (AgBr) films) into the source and drain regions of a MOSFET can assist in controlling the transistor performance by tuning the threshold voltage. If the silver bromide film is rich in bromine atoms, anion quantum dots are deposited, and the AgBr energy gap is altered so as to increase Vt. If the silver bromide film is rich in silver atoms, cation quantum dots are deposited, and the AgBr energy gap is altered so as to decrease Vt. Atomic layer deposition (ALD) of neutral quantum dots of different sizes also varies Vt. Use of a mass spectrometer during film deposition can assist in varying the composition of the quantum dot film. The metallic quantum dots can be incorporated into ion-doped source and drain regions. Alternatively, the metallic quantum dots can be incorporated into epitaxially doped source and drain regions.
    Type: Grant
    Filed: January 12, 2022
    Date of Patent: October 1, 2024
    Assignee: STMICROELECTRONICS, INC.
    Inventor: John H. Zhang
  • Patent number: 12095008
    Abstract: A light emitting element includes a first semiconductor layer including a first type of semiconductor, the first semiconductor layer including a 1-1-th semiconductor layer and a 1-2-th semiconductor layer, which are arranged in a length direction of the light emitting element; a second semiconductor layer including a second type of semiconductor different from the first type; an active layer disposed between the 1-2-th semiconductor layer and the second semiconductor layer; and an intermediate layer disposed between the 1-1-th semiconductor layer and the 1-2-th semiconductor layer and having a porous structure.
    Type: Grant
    Filed: July 1, 2021
    Date of Patent: September 17, 2024
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Young Chul Sim, Hyung Rae Cha, Dong Uk Kim, Sung Ae Jang, Ji Hyun Ham
  • Patent number: 12074255
    Abstract: The display device according to an exemplary embodiment of the present disclosure includes a substrate and a display element unit. The display element unit includes a first electrode on the substrate, a second electrode on the substrate and spaced apart from the first electrode in a first direction, and a plurality of light emitting elements between the first electrode and the second electrode in a plan view. Each of the first and second electrodes includes an opening.
    Type: Grant
    Filed: March 16, 2021
    Date of Patent: August 27, 2024
    Assignee: Samsung Display Co., Ltd.
    Inventors: Hyun Wook Lee, Myeong Hun Song, Jeong Hyun Lee, Jong Chan Lee, Tae Hee Lee
  • Patent number: 12074251
    Abstract: A structure includes a first material layer, a second material layer, and a stress relaxation layer having a thickness of 0.5 nm or less between the first material layer and the second material layer.
    Type: Grant
    Filed: April 26, 2021
    Date of Patent: August 27, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Saket Chadda, Zhen Chen
  • Patent number: 12068429
    Abstract: A method for manufacturing a light-emitting element, includes: introducing a gas comprising gallium, an ammonia gas, and a gas comprising a p-type impurity to a reactor and forming a first p-type nitride semiconductor layer on a first light-emitting layer in a state in which the reactor has been heated to a first temperature; introducing an ammonia gas at a first flow rate and a nitrogen gas to the reactor in a state in which the reactor is held at the first temperature; and subsequently introducing a gas comprising gallium, an ammonia gas at a second flow rate, and a gas comprising an n-type impurity to the reactor, and forming a second n-type nitride semiconductor layer on the first p-type nitride semiconductor layer. The first flow rate is less than the second flow rate.
    Type: Grant
    Filed: December 22, 2022
    Date of Patent: August 20, 2024
    Assignee: NICHIA CORPORATION
    Inventor: Seiichi Hayashi
  • Patent number: 12057525
    Abstract: A nitride semiconductor light-emitting element includes an n-type semiconductor layer, a p-type semiconductor layer, an active layer, and an electron blocking layer comprising at least one layer. The at least one layer of the electron blocking layer includes a peak-containing layer having an n-type impurity concentration peak in an n-type impurity concentration distribution along a stacking direction. The n-type impurity concentration peak appears as a local maximum in the n-type impurity concentration distribution along the stacking direction in the peak-containing layer and has an n-type impurity concentration of not less than 10 times a smallest value of the n-type impurity concentration in a region along the stacking direction between positions that are separated from a position of the peak in the stacking direction on both sides in the stacking direction by 10% of a thickness of the peak-containing layer.
    Type: Grant
    Filed: October 26, 2021
    Date of Patent: August 6, 2024
    Assignee: Nikkiso Co., Ltd.
    Inventors: Yusuke Matsukura, Cyril Pernot