Abstract: According to an aspect, a semiconductor device for integrating multiple transistors includes a wafer substrate including a first region and a second region. The first region defines at least a portion of at least one first transistor. The second region defines at least a portion of at least one second transistor. The semiconductor device includes an isolation area located between the first region and the second region, at least one terminal of the at least one first transistor contacting the first region of the wafer substrate, at least one terminal of the at least one second transistor contacting the second region of the wafer substrate, and an encapsulation material, where the encapsulation material includes a portion located within the isolation area.

Abstract: Techniques facilitating resistive random-access memory device with step height difference are provided. A resistive random-access memory device can comprise a first electrode located within a trench of a dielectric layer. The resistive random-access memory device can also comprise a metal oxide layer comprising a first section located within the trench of the dielectric layer, and a second section located over the first electrode, and over a barrier metal layer. Further, the resistive random-access memory device can comprise a second electrode located over the metal oxide layer.

Abstract: A light emitting diode (LED) structure includes a semiconductor template having a template top-surface, an active quantum well (QW) structure formed over the semiconductor template, and a p-type layer. The p-type layer has a bottom-surface that faces the active QW and the template top-surface. The bottom-surface includes a recess sidewall. The recess sidewall of the p-type layer is configured for promoting injection of holes into the active QW structure through a QW sidewall of the active QW structure.

Abstract: A semiconductor device includes a JFET and a MOSFET cascode-connected to each other such that a source electrode of the JFET is connected to a drain electrode of the MOSFET. The JFET is configured such that a breakdown voltage between a gate layer and a body layer is set lower than a breakdown voltage of the MOSFET.

Abstract: A process for fabricating a heterostructure includes at least one elementary structure made of III-V material on the surface of a silicon-based substrate successively comprising: producing a first pattern having at least a first opening in a dielectric material on the surface of a first silicon-based substrate; a first operation for epitaxy of at least one III-V material so as to define at least one elementary base layer made of III-V material in the at least first opening; producing a second pattern in a dielectric material so as to define at least a second opening having an overlap with the elementary base layer; a second operation for epitaxy of at least one III-V material on the surface of at least the elementary base layer made of III-V material(s) so as to produce the at least elementary structure made of III-V material(s) having an outer face; an operation for transferring and assembling the at least photonic active elementary structure via its outer face, on an interface that may comprise passive elem

Abstract: A semiconductor on insulator multilayer structure is provided. The multilayer comprises a high resistivity single crystal semiconductor handle substrate, an optionally relaxed semiconductor layer comprising silicon, germanium, or silicon germanium, an optional polycrystalline silicon layer, a dielectric layer, and a single crystal semiconductor device layer.

Abstract: The present invention relates to a method for manufacturing a diamond substrate, and more particularly, to a method of growing diamond after forming a structure of an air gap having a crystal correlation with a lower substrate by heat treatment of a photoresist pattern and an air gap forming film material on a substrate such as sapphire (Al2O3). Through such a method, a process is simplified and the cost is lowered when large-area/large-diameter single crystal diamond is heterogeneously grown, stress due to differences in a lattice constant and a coefficient of thermal expansion between the heterogeneous substrate and diamond is relieved, and an occurrence of defects or cracks is reduced even when a temperature drops, such that a high-quality single crystal diamond substrate may be manufactured and the diamond substrate may be easily self-separated from the heterogeneous substrate.

Abstract: An embodiment discloses an ultraviolet light emitting element including: a light emitting structure including a first conductive semiconductor layer, a second conductive semiconductor layer, an active layer disposed between the first conductive semiconductor layer and the second conductive semiconductor layer, and an etched region in which the first conductive semiconductor layer is exposed; a first insulating layer disposed on the light emitting structure and including a first hole which exposes a portion of the etched region; a first electrode electrically connected to the first conductive semiconductor layer; and a second electrode electrically connected to the second conductive semiconductor layer, wherein the light emitting structure includes an intermediate layer regrown on the first conductive semiconductor layer exposed in the first hole, the first electrode is disposed on the intermediate layer, the etched region includes a first etched region disposed at an inner side and a second etched region disp

Abstract: A method of manufacturing a nitride semiconductor device includes: forming a first semiconductor layer containing Al, Ga, and N and having a first thickness by doping a p-type impurity; forming a second semiconductor layer over the first semiconductor layer without doping an n-type impurity and without doping a p-type impurity, the second semiconductor layer containing Al and N and having a second thickness; and heat treating the first semiconductor layer and the second semiconductor layer. The second thickness is less than the first thickness. T band gap energy of the second semiconductor layer is greater than a band gap energy of the first semiconductor layer. After the heat treating of the first semiconductor layer and the second semiconductor layer, the second semiconductor layer contains the p-type impurity by diffusion of the p-type impurity from the first semiconductor layer.

Abstract: An image sensor may include a semiconductor substrate having a light receiving surface thereon and a plurality of spaced-apart semiconductor photoelectric conversion regions at adjacent locations therein. A grating structure is provided on the light receiving surface. This grating structure extends opposite each of the plurality of spaced-apart photoelectric conversion regions. An optically-transparent layer is provided on the grating structure. This grating structure includes a plurality of spaced-apart grating patterns, which can have the same height and the same width. In addition, the grating patterns may be spaced apart from each other by a uniform distance. The grating structure is configured to selectively produce ±1 or higher order diffraction lights to the photoelectric conversion regions, in response to light incident thereon.

Abstract: A semiconductor device having a semiconductor module. The semiconductor module includes first and second conductor layers facing each other, a first semiconductor element provided between the first and second conductor layers, positive and negative electrode terminals respectively provided on edge portions of the first and second conductor layers at a first side of the semiconductor module in a top view of the semiconductor module, control wiring that is electrically connected to the first control electrode, and that extends out of the first and second conductor layers at a second side of the semiconductor module that is opposite to the first side in the top view, and a control terminal that is electrically connected to the control wiring, that is positioned outside the first and second conductor layers in the top view, and that has an end portion that is aligned with the positive and negative electrode terminals.

Abstract: A first component with a first sidewall and a second component with a second sidewall may be mounted onto an expandable film such that an original distance X is the distance between the first sidewall and the second sidewall. The expandable film may be expanded such that an expanded distance Y is the distance between the first sidewall and the second sidewall and expanded distance Y is greater than original distance X. A first sidewall material may be applied within at least a part of a space between the first sidewall and the second sidewall. The expandable film may be expanded such that a contracted distance Z is the distance between the first sidewall and the second sidewall, and contracted distance Z is less than expanded distance Y.

Abstract: A transient voltage suppression device includes a P-type semiconductor layer, a first N-type well, a first N-type heavily-doped area, a first P-type heavily-doped area, a second P-type heavily-doped area, and a second N-type heavily-doped area. The first N-type well and the second N-type heavily-doped area are formed in the layer. The first P-type heavily-doped area is formed in the first N-type well. The first P-type heavily-doped area is spaced from the bottom of the first N-type well. The second P-type heavily-doped area is formed within the first N-type well and spaced from the sidewall of the first N-type well. The second P-type heavily-doped area is formed between the first P-type heavily-doped area and the second N-type heavily-doped area.

Abstract: A power device which is formed on a semiconductor substrate includes: a lateral insulated gate bipolar transistor (LIGBT), a PN diode and a clamp diode. The PN diode is connected in parallel to the LIGBT. The clamp diode has a clamp forward terminal and a clamp reverse terminal, which are electrically connected to a drain and a gate of the LIGBT, to clamp a gate voltage applied to the gate not to be higher than a predetermined voltage threshold.

Abstract: A short-circuit semiconductor component comprises a semiconductor body, in which a rear-side base region of a first conduction type, an inner region of a second conduction type complementary to the first conduction type, and a front-side base region of the first conduction type are disposed. The rear-side base region is electrically connected to a rear-side electrode with a rear-side electrode width, and the front-side base region is electrically connected to a front-side electrode with a front-side electrode width. A turn-on structure with a turn-on structure width is embedded into the front-side and/or rear-side base region and is covered by the respective electrode. The turn-on structure is configured to be turned on depending on a supplied turn-on signal and to produce, on a one-off basis, an irreversible, low-resistance connection between the two electrodes. The ratio of the turn-on structure width to the respective electrode width is less than 1.

Abstract: A wavelength converting layer may have a glass or a silicon porous support structure. The wavelength converting layer may also have a cured portion of wavelength converting particles and a binder filling the porous glass or silicon support structure.

Abstract: A method for etching a semiconductor structure (110) is provided, the semiconductor structure comprising a sub-surface quantum structure (30) of a first III-V semiconductor material,beneath a surface layer (31) of a second III-V semiconductor material having a charge carrier density of less than 5×1017 cm?3. The sub-surface quantum structure may comprise, for example, a quantum well, or a quantum wire, or a quantum dot. The method comprises the steps of exposing the surface layer to an electrolyte (130), and applying a potential difference between the first III-V semiconductor material and the electrolyte, to electrochemically etch the sub-surface quantum structure (30) to form a plurality of nanostructures, while the surface layer (31) is not etched. A semiconductor structure, uses thereof, and devices incorporating such semiconductor structures are further provided.

Abstract: A semiconductor device includes a fin extending along a first direction over a substrate, and a gate structure extending in a second direction overlying the fin. The gate structure includes a gate dielectric layer overlying the fin, a gate electrode overlying the gate dielectric layer, and insulating gate sidewalls on opposing lateral surfaces of the gate electrode extending along the second direction. A source/drain region is formed in the fin in a region adjacent the gate electrode structure, and a stressor layer is between the source/drain region and the semiconductor substrate. The stressor layer includes GeSn or SiGeSn containing 1019 atoms cm?3 or less of a dopant, and a portion of the fin under the gate structure is a channel region.

Abstract: A method for forming a light emitting diode (LED) uses aluminum-based material layers and oxidation during the LED formation. In some embodiments, the method may include forming an n-type layer of the LED on a substrate, forming at least one sidewall restriction layer of the LED on the substrate with the sidewall restriction layer comprising an aluminum-based material, forming a quantum well layer of the LED on the substrate, forming a p-type layer of the LED on the substrate, exposing the substrate to water vapor, and heating the substrate to oxidize at least an outer portion of the electron blocking layer. The aluminum-based material may include aluminum indium nitride or aluminum gallium arsenide.

Abstract: A semiconductor device includes a semiconductor element, a mount portion, and a sintered metal bond. The semiconductor element includes a body and an electrode pad. The body has an obverse surface facing forward in a first direction and a reverse surface facing rearward in the first direction. The electrode pad covers the element reverse surface. The mount portion supports the semiconductor element. The sintered metal bond electrically bonds the electrode pad and the mount portion. The sintered metal bond includes a first rear edge and a first front edge spaced forward in the first direction from the first rear edge. The electrode pad includes a second rear edge and a second front edge spaced forward in the first direction from the second rear edge. The first front edge of the metal bond is spaced rearward in the first direction from the second front edge of the pad.