Abstract: Disclosed herein are exemplary techniques for generating trace information streams to facilitate the reconstruction of the instruction execution history of a processing device for a given time period. The linear instruction pointers or other representations of the instructions executed by a processing device are output as a trace information stream. When one or more translation lookaside buffers (TLBs) used by the processing device are modified by the addition of a new linear-to-physical translation and/or the eviction of an old linear-to-physical translation, a representation of the newly added translation entry, or, alternatively the evicted translation entry, is inserted into the trace information stream. In this manner, the context for the address mapping of the instruction pointers of the trace information stream is provided and, consequently, the execution instruction history of the processing device may be more fully reconstructed.

Abstract: An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. In one aspect of an embodiment of the invention, the data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.

Abstract: A method, apparatus, and computer instructions are provided for storage provisioning automation in a data center. A storage manager is provided in the present invention to facilitate end-to-end deployment of storage resources for a server in the data center. The storage manager includes functionalities of a volume manager, file system, and physical volumes. In addition, a hierarchical structure is provided by the present invention to specify configuration data for a volume container. The hierarchical structure includes volume container settings, which includes physical volume settings and logical volume settings linked through data partition settings. For SAN volumes, storage multipath settings and data path settings are included in the structure. File system settings and mounting settings are also included to mount a file system once it is created.

Abstract: A method for using non-volatile memory and an electronics device thereof is provided. The method includes the following steps. First, a non-volatile memory pre-loaded with a plurality of original data is provided. When updating the original data with new data, if free space is available in the non-volatile memory, then the new data is written into the free space. If free space is not available, all the updated original data is written into the erased non-volatile memory.

Abstract: Tracing instruction flow in an integrated processor by defeaturing a cache hit into a cache miss to allow an instruction fetch to be made visible on a bus, which instruction would not have been made visible on the bus had the instruction fetch hit in the cache. The defeature activation is controlled by use of a defeature hit signal bit in a defeature register, and in which the bit may be programmed.

Abstract: Computer memory is initialized by generating configuration data for a portion of memory, saving the configuration data, restarting computer memory initialization, copying the saved configuration data to initialize the portion of memory, and using the portion of memory to execute instructions to initialize a remainder of memory.

Abstract: A method and system for using a requeueing procedure to resolve deadlocks in a computing system is disclosed. A request for a resource may be requeued after a designated period of time or wait cycles if it is blocked from being granted. For example, a request for exclusive ownership of a resource could be requeued if it cannot be granted within an appropriate period of time. These types of requests are requeued to allow other requests for the same resource to move ahead in the wait queue. This allows other grantable requests behind the blocked request to be immediately granted. Using this approach, it is possible that allowing the other requests behind the timed-out request to move ahead in the queue will set off a chain reaction of accesses to resources which will clear the deadlock situation that initially causes the requeued request(s) to be blocked.

Abstract: A hierarchical programmable-priority content addressable memory (CAM) system including first, second and third CAM devices. The first CAM device has a first priority number output and a first enable input. The second CAM device has a priority number input and an enable output coupled to the priority number output and the first enable input, respectively, of the first CAM device. The second CAM device also has a priority number output and an enable input. The third CAM device has a priority number input and an enable output coupled to the priority number output and the enable input, respectively, of the second CAM device.

Abstract: An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. In one aspect of an embodiment of the invention, the data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.

Abstract: A cache system comprises i (e.g., 2) groups of m (e.g., 2) ways and n (e.g., 2) sets of cache arrays, a set address decoder, a comparator, a cache address and cache management information. The set address decoder selects all or one of the i groups of cache arrays based on the cache address and cache management information, and selects a j-th set in the selected cache memories according to the cache address.

Abstract: Managing memory includes subdividing the memory into a first set of blocks corresponding to a first size and a second set of blocks corresponding to a second size that is greater than said first size, in response to a request for an amount of memory that is less than or equal to the first size, providing one of the first set of blocks, and, in response to a request for an amount of memory that is greater than the first size and less than or equal to the second size, providing one of the second set of blocks. Subdividing the memory may also include subdividing the memory into a plurality of sets of blocks, where each particular set contains blocks corresponding to one size that is different from that of blocks not in the particular set. Each set of blocks may correspond to a size that is a multiple of a predetermined value. Managing memory may also include providing a table containing an entry for each set of blocks. The entry for each set of blocks may be a pointer to one of: an unused block and null.

Abstract: A method for calculating flow control credits includes determining a number of entries added to each of a pair of storage devices, determining a number of entries removed from each of the storage devices, calculating a difference between available space in the storage devices, and calculating a number of credits to release based on the numbers of entries added to each of the storage devices, on the numbers of entries removed from each of the storage devices, and on the difference in available space. Entries removed from one storage device are treated as an entry added to the other storage device.

Abstract: A dynamic parity distribution system and technique distributes parity across disks of an array. The dynamic parity distribution system includes a storage operating system that integrates a file system with a RAID system. In response to a request to store (write) data on the array, the file system determines which disks contain free blocks in a next allocated stripe of the array. There may be multiple blocks within the stripe that do not contain file system data (i.e., unallocated data blocks) and that could potentially store parity. One or more of those unallocated data blocks can be assigned to store parity, arbitrarily. According to the dynamic parity distribution technique, the file system determines which blocks hold parity each time there is a write request to the stripe. The technique alternately allows the RAID system to assign a block to contain parity when each stripe is written.

Abstract: Device for treating a memory state resulting from incomplete writing or erasing of data. The memory includes memory cells organized in a plurality of pages each having generation information indicating a programming time of the page. A unit determines generation information from the generation information of the plurality of pages to obtain determined generation information indicating a programming time which is not the oldest programming time. A page determination unit determines a page including an inconsistency from the plurality of pages to obtain a determined page. A selection unit selects a further page, a marking unit marks the further page to obtain a marked page, and a providing unit provides new generation information based on the determined generation information. A reading unit reads data from the marked page and a writing unit writes the data read from the marked page and the new generation information to the determined page.

Abstract: A computer system is provided with a collection section for collecting load information related to an application server and a storage subsystem, a transmission section for predicting a write processing property based on the load information collected by the collection section and for transmitting the write processing property to the storage subsystem, and a write control section for controlling a write processing to a hard disk drive in the storage subsystem based on the write processing property transmitted by the transmission section. A target of the writable cache amount is set so that a write processing amount from a cache of the storage subsystem to the hard disk drive is averaged in terms of time, and the write processing to the hard disk drive is performed to satisfy the target of the writable cache amount.

Abstract: A mechanism for filtering snoop requests to a cache memory includes, in one embodiment, a storage including a plurality of entries configured to store corresponding snoop filter indications. The mechanism also includes a cache controller configured receive a transaction request including an address and to generate an index for accessing the storage by performing a hash function on the address. The cache controller selectively generates a snoop operation to the cache memory for the transaction request dependent upon a snoop filter indication stored in the storage that corresponds to the address.

Abstract: A low overhead method for identifying memory leaks is provided. The low overhead method includes a) detecting completion of a garbage collection cycle; and b) identifying a boundary between used objects in memory and free memory space. The steps of a) and b) are repeated and then it is determined if there is an existing memory leak based upon evaluation of boundary identifiers. A computer readable media and a system for identifying memory leaks for an object-oriented application are also provided.

Abstract: A storage device includes a plurality of memories storing data; and a controller controlling the memories, the controller performing in parallel in a number of the memories, the number being specified by a supplied specifying signal, one of a data writing process for writing data supplied from a connection destination device to which the storage device is connectable and a data reading process for reading data requested by the connection destination device.

Abstract: A control mechanism that allows individual applications to turn hardware prefetch on or off is provided. By preliminary trial run one can determine precisely whether an application will benefit or suffer from hardware prefetch. The selective control of prefetching by individual applications is made possible by associating a status bit with individual processes in the machine status word of each processor. Using this prefetch bit, a process turns prefetching on or off to its own advantage in the processor core immediately after a context switch.

Abstract: A non-volatile semiconductor memory device includes: a cell array having electrically rewritable and non-volatile memory cells arranged therein, the cell array being divided into a plurality of blocks, each the block being divided into a plurality of sub-blocks each having one or plural and continuous pages; and a controller for controlling data erasure of the cell array in a way that each the sub-block serves as a unit of data erasure, wherein each the sub-block in the cell array stores the number of data erasure which is renewed by each data erasure, and the number of data erasure is limited for each the sub-block to a permissible maximum value stored in a certain block in the cell array.