Abstract: A method for identifying memory leak causes is provided. The method initiates with tracking a number of allocations of objects during a time period. Potentially leaking objects are identified and object lifetime tracking instrumentation is injected into the code to track potentially leaking objects. Then, object lifetime logs are generated for each of the potentially leaking objects. A computer readable medium and a system are also provided.

Abstract: Embodiments of the present invention provide a data storage apparatus with new features to more easily enable atomic transactions. Rather than having the host system issue the multiple logging commands to the data storage apparatus, the data storage apparatus can be modified so that it can perform the logging function itself. In one embodiment, a data storage controller of a data storage apparatus for implementing an atomic transaction comprises a receiving module configured to receive from a host one or more commands to be executed as an atomic transaction; a log recording module, configured to record in a nonvolatile storage a log containing the one or more commands of the atomic transaction, the log to be administered by the data storage controller and not by the host; and an execution module configured to perform the one or more commands of the atomic transaction.

Abstract: A data processor including a central processing unit and a data transfer control unit is disclosed. The data transfer control unit has an address register for storing a transfer address. The data transfer control unit transfers data according to a transfer unit size selected from a plurality of transfer unit sizes. If the address register contains an odd address as an initial value, the data transfer control unit transfers data according to a different transfer unit size that is smaller than the selected transfer unit size. If the data transfer control unit determines that a remaining quantity of data to be transferred is smaller than the selected transfer unit size, the selected transfer unit size is switched to a smaller transfer unit size selected from the plurality of transfer unit sizes.

Abstract: An internal nonvolatile memory contains a program to be executed during a rewrite operation mode. During the rewrite operation mode a CPU core writes received rewrite data to an external nonvolatile memory according to a program in the internal nonvolatile memory. A first selector circuit transmits a first chip select signal to the external nonvolatile memory when a mode signal indicates a normal operation mode, and transmits the first chip select signal to the internal nonvolatile memory when the mode signal indicates the rewrite operation mode. Since the activation of the internal nonvolatile memory is inhibited during the normal operation mode, it is possible to prevent erroneous execution of the program in the internal nonvolatile memory during the normal operation mode, and to prevent data rewrite to the external nonvolatile memory.

Abstract: A method of protecting memory locations in an embedded system using a write filter. The method includes the steps of starting a write filter that intercepts writes to the protected memory locations and stores the writes in a cache; starting a state machine with a change state and a normal state; upon starting the state machine, entering the change state when an indication is present that data needs to be persisted to the protected memory otherwise entering the normal state; in the normal state identifying critical writes to the protected memory and creating at least one update file containing the changes in such writes; and in the change state, applying the changes in the update file and rebooting the system in a manner that persists the changes to the protected memory.

Abstract: A processor-based automatic alignment device and method for data movement. Data stored in a memory at a first position is partitioned by word boundaries into a first part, a second part and a third part and written to the memory at a second position. The device includes: an internal register, a load combine register, a shifter, a rotator, a store combine register and a mask selector. Data is loaded in and aligned by the device for storing in internal register of a processor. Next, data stored in the internal register is automatically aligned and then written in the memory at an unaligned position.

Abstract: A method, computer program product, and distributed data processing system that allows a single physical I/O adapter, such as a PCI, PCI-X, or PCI-E adapter, to track performance and reliability statistics per virtual upstream and downstream port, thereby allowing a system and network management to be performed at finer granularity than what is possible using conventional physical port statistics, is provided. Particularly, a mechanism of managing per-virtual port performance metrics in a logically partitioned data processing system including allocating a subset of resources of a physical adapter to a virtual adapter of a plurality of virtual adapters is provided. The subset of resources includes a virtual port having an identifier assigned thereto. The identifier of the virtual port is associated with an address of a physical port. A metric table is associated with the virtual port, wherein the metric table includes metrics of operations that target the virtual port.

Abstract: A storage system including a memory unit having a disk management program, plural disk controllers each having a SAS port which can be attached to either a SAS disk drive or a SATA disk drive, and a LAN port which communicates with a user interface program in a management console.

Abstract: A device for writing data in a processor to memory at unaligned location. The data is stored in an internal register of the processor for writing to unaligned addresses of a memory partitioned by word boundaries into a plurality of words. A rotator is coupled to the internal register for rotating data of the internal register to a first position in accordance with written unaligned address. A store combine register is coupled to the rotator for temporarily storing data of the rotator. A mask selector is coupled to the rotator and the store combine register for selectively masking their data in accordance with the written unaligned address and storing the data masked to the memory.

Abstract: A processor-based automatic alignment device and method for data movement. Data stored in a memory at a first position is partitioned by word boundaries into a first part, a second part and a third part and written to the memory at a second position. The device includes: an internal register, a load combine register, a shifter, a rotator, a store combine register and a mask selector. Data is loaded in and aligned by the device for storing in internal register of a processor. Then, data stored in the internal register is automatically aligned and then written in the memory at an unaligned position.

Abstract: A method and apparatus for invalidating entries within a translation control entry (TCE) cache are disclosed. A host bridge is coupled between a group of processors and a group of adaptors. The host bridge includes a TCE cache. The TCE cache contains the most-recently use copies of TCEs in a TCE table located in a system memory. In response to a modification to a TCE in the TCE table by one of the processors, a memory mapped input/output (MMIO) Store is sent to a TCE invalidate register to specify an address of the modified TCE. The data within the TCE invalidate register is then utilized to generate a command for invalidating an entry in the TCE cache containing an unmodified copy of the modified TCE in the TCE table. The command is subsequently sent to the host bridge to invalidate the entry in the TCE cache.

Abstract: A processor device capable of cross-boundary alignment of plural register data and the method thereof. The processor includes a decoder to decode a multiple shift instruction, a register unit with plural N-bit registers, a shifter to combine a first and a second output contents of the register unit to form a 2N-bit word and shift the word by w bits, thereby outputting first N bits of the word shifted, a controller to set the register unit in accordance with the multiple shift instruction decoded, thereby reading contents of corresponding registers for shifting w bits by the shifter and then writing an output of the shifter to the register unit.

Abstract: A prior art mass storage device for bootstrap loading of a computer operating system must be configured on a set-up computer whose BIOS has the same geometrical translation scheme as the BIOS of the host computer where the storage device is intended to be installed and used. The present invention provides a mass storage device capable of bootstrap loading the computer operating system despite differences between the BIOS geometrical translation scheme of the set-up computer and that of the host computer, along with methods for implementing and preparing such a device. The present invention provides executable code on the storage device itself, which resolves the geometrical translation of the set-up configuration to comply with that of the host computer, independent of the respective BIOS translation schemes used for set-up and host computers.

Abstract: Methods and apparatus are disclosed for maintaining and using entries in one or more associative memories. A last bit of a prefix is checked, and based on this result, the entry is placed into one of two classes of associative memory entries. The entry can then be identified within the associative memory by performing a lookup operation using the prefix padded with ones if the last bit of the prefix is zero or with zeros if the last bit is one to fill out the remaining bits of the lookup word. Entries of different classes of entries are typically either stored in different associative memories, or in the same associative memory with each of these entries including a class specific identifier. Among other applications, these entries can be used to locate a prefix and to store a tree data structure in the one or more associative memories.

Abstract: Scaling address space utilization in a multi-threaded, multi-processor computer, including attaching to process memory of an exporting process a region of virtual memory specified in a cross-memory descriptor; requesting, by an importing thread of an importing process having process memory, a lightweight attachment of the region of virtual memory to the process memory of the importing process for exclusive use by the importing thread; and lightweight attaching, by an operating system to the process memory of the importing process, the region of virtual memory for exclusive use by the importing thread.

Abstract: Method and apparatus for storing and retrieving copy-protected data within storage devices such as, for example, disc drives. Data that is to be copy protected is written on the storage device. A first data list, such as a manufacturer's storage device defect list, is copied and used to make a second data list. Then, the first data list is modified such that the area where the copy protected data is stored is identified as defective. Unless a request to read the copy protected data is received, the first data list is used and the copy protected data area is considered defective. However, if a request to read the copy protected data is received, the second data list is used and the copy protected data is read from its storage location.

Abstract: A technique to increase transfer rate of command and address signals via a given number of command and address pins in each of one or more integrated circuit memory devices during a clock cycle of a clock signal. In one example embodiment, the command and address signals are sent on both rising and falling edges of a clock cycle of a clock signal to increase the transfer rate and essentially reduce the number of required command and address pins in each integrated circuit memory device.

Abstract: Disclosed is a vector indexed memory unit and method of operation. In one embodiment a plurality of values are stored in segments of a vector index register. Individual ones of the values are provided to an associated operator (e.g., adder or bit replacement). Individual ones of the operators operates on its associated vector index value and a base value to generate a memory address. These memory addresses are then concurrently accessed in one or more memory units. If the data in the memory units are organized as data tables, the apparatus allows for multiple concurrent table lookups. In an alternate embodiment, in addition to the above described operators generating multiple memory addresses, an adder is provided to add the base value to the value represented by the concatenation of the bits in the vector index register to generate a single memory address.

Abstract: A method, apparatus, and computer program product in a shared processor data processing system are disclosed for dynamically tuning an amount of physical processor capacity that is allocated to each one of multiple logical partitions. A physical processor is shared among the logical partitions. A service window is allocated to each logical partition during each dispatch time slice. Processes that are defined by a first one of the logical partitions are executed during a first service window that was allocated to the first logical partition. A determination is made dynamically during runtime as to whether a length of the first service window should be increased to optimize interrupt processing and reduce interrupt latency. If it is determined that the length should be increased, the length of the first service window is dynamically increased during runtime.

Abstract: Arbitrary patterns of address locations of digital data can be efficiently read from a memory of a signal processor. For example, a first memory address generator receives a first memory command signal from a first communication register to retrieve a first set of data from memory according to a look up table of memory addresses. The first memory access generator reads the look up table of memory addresses, which contain a second set of memory commands and reroutes the second set of commands to a bypass register. In turn, the second set of memory commands stored at the bypass register are read by a second memory address generator which retrieves a second set of data from memory according to the second set of memory command signals read out of memory by the first memory address generator.