Patents Examined by Matthew Landau
  • Patent number: 10249764
    Abstract: A method for manufacturing a transistor with stable electric characteristics and little signal delay due to wiring resistance, used in a semiconductor device including an oxide semiconductor film. A semiconductor device including the transistor is provided. A high-performance display device including the transistor is provided.
    Type: Grant
    Filed: August 4, 2017
    Date of Patent: April 2, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 10199412
    Abstract: This disclosure describes optoelectronic modules that include an image sensor having at least two regions separated optically from one another by a wall. The wall can include a bridge portion that extends over the image sensor and further can include a cured adhesive portion, part of which is disposed between a lower surface of the bridge portion and an upper surface of the image sensor. Various techniques are described for fabricating the modules so as to help prevent the adhesive from contaminating sensitive regions of the image sensor. The wall can be substantially light-tight so as to prevent undesired optical cross-talk, for example, between a light emitter located to one side of the wall and a light sensitive region of the image sensor located to the other side of the wall.
    Type: Grant
    Filed: July 22, 2015
    Date of Patent: February 5, 2019
    Assignee: Heptagon Micro Optics Pte. Ltd.
    Inventors: Simon Gubser, Sonja Hanselmann, Qichuan Yu, Cris Calsena, Guo Xiong Wu, Hartmut Rudmann
  • Patent number: 10177205
    Abstract: A display device including a plurality of first electrodes arranged in a display region above a substrate, each of the plurality of first electrodes being in common with n (n is an integer of 2 or more) number of light emitting elements, a bank having a recess part and partitioning the n number of light emitting elements with the recess part as a boundary in each of the plurality of first electrodes, a light emitting layer arranged above the plurality of first electrodes throughout the display region, and n groups of second electrodes arranged above the light emitting layer and electrically separated with the recess part as a boundary.
    Type: Grant
    Filed: September 27, 2016
    Date of Patent: January 8, 2019
    Assignee: Japan Display Inc.
    Inventors: Yasukazu Kimura, Toshihiro Sato
  • Patent number: 10163979
    Abstract: Memory devices and manufacturing methods thereof are presented. A memory device a substrate and a memory cell having at least one selector and a storage element. The selector includes a well of a first polarity type disposed in the substrate, a region of a second polarity type disposed over the well and in the substrate, and first and second regions of the first polarity type disposed adjacent to the region of the second polarity type. The storage element includes a programmable resistive layer disposed on the region of the second polarity type and an electrode disposed over the programmable resistive layer.
    Type: Grant
    Filed: September 11, 2014
    Date of Patent: December 25, 2018
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Xuan Anh Tran, Eng Huat Toh, Shyue Seng Tan, Yuan Sun, Elgin Kiok Boone Quek
  • Patent number: 10134899
    Abstract: The presence of a facet or a void in an epitaxially grown crystal indicates that crystal growth has been interrupted by defects or by certain material boundaries. Faceting can be suppressed during epitaxial growth of silicon compounds that form source and drain regions of strained silicon transistors. It has been observed that faceting can occur when epitaxial layers of certain silicon compounds are grown adjacent to an oxide boundary, but faceting does not occur when the epitaxial layer is grown adjacent to a silicon boundary or adjacent to a nitride boundary. Because epitaxial growth of silicon compounds is often necessary in the vicinity of isolation trenches that are filled with oxide, techniques for suppression of faceting in these areas are of particular interest. One such technique, presented herein, is to line the isolation trenches with SiN to provide a barrier between the oxide and the region in which epitaxial growth is intended.
    Type: Grant
    Filed: December 29, 2015
    Date of Patent: November 20, 2018
    Assignee: STMicroelectronics, Inc.
    Inventors: Nicolas Loubet, Prasanna Khare, Qing Liu
  • Patent number: 10134895
    Abstract: The presence of a facet or a void in an epitaxially grown crystal indicates that crystal growth has been interrupted by defects or by certain material boundaries. Faceting can be suppressed during epitaxial growth of silicon compounds that form source and drain regions of strained silicon transistors. It has been observed that faceting can occur when epitaxial layers of certain silicon compounds are grown adjacent to an oxide boundary, but faceting does not occur when the epitaxial layer is grown adjacent to a silicon boundary or adjacent to a nitride boundary. Because epitaxial growth of silicon compounds is often necessary in the vicinity of isolation trenches that are filled with oxide, techniques for suppression of faceting in these areas are of particular interest. One such technique, presented herein, is to line the isolation trenches with SiN to provide a barrier between the oxide and the region in which epitaxial growth is intended.
    Type: Grant
    Filed: December 3, 2012
    Date of Patent: November 20, 2018
    Assignee: STMicroelectronics, Inc.
    Inventors: Nicolas Loubet, Prasanna Khare, Qing Liu
  • Patent number: 10079315
    Abstract: The present invention provides a semiconductor structure, including a substrate, a gate dielectric layer disposed on the substrate, a charge storage layer disposed on the gate dielectric layer, and at least two poly silicon layers, disposed on the gate dielectric layer respectively, and covering parts of the charge storage layer simultaneously.
    Type: Grant
    Filed: September 11, 2014
    Date of Patent: September 18, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventor: Po-Han Jen
  • Patent number: 10079257
    Abstract: A method of forming an image sensor device includes forming a light sensing region at a front surface of a silicon substrate and a patterned metal layer there over. Thereafter, the method includes depositing a metal oxide anti-reflection laminate on the first surface of the substrate. The metal oxide anti-reflection laminate includes one or more composite layers of thin metal oxides stacked over the photodiode. Each composite layer includes two or more metal oxide layers: one metal oxide is a high energy band gap metal oxide and another metal oxide is a high refractive index metal oxide.
    Type: Grant
    Filed: January 31, 2013
    Date of Patent: September 18, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsing-Lien Lin, Yeur-Luen Tu, Cheng-Yuan Tsai, Cheng-Ta Wu, Chia-Shiung Tsai
  • Patent number: 10074770
    Abstract: A quantum dot includes a core-shell structure including a core including a first semiconductor nanocrystal and a shell disposed on the core, and including a material at least two different halogens, and the quantum dot does not include cadmium.
    Type: Grant
    Filed: December 21, 2016
    Date of Patent: September 11, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Garam Park, Tae Hyung Kim, Eun Joo Jang, Hyo Sook Jang, Shin Ae Jun, Yongwook Kim, Taekhoon Kim, Jihyun Min, Yuho Won
  • Patent number: 10056341
    Abstract: An electronic device may include a first substrate, an electrically conductive feed line on the first substrate, an insulating layer on the first substrate and the electrically conductive feed line, a second substrate on the insulating layer, and an antenna on the second substrate and having nanofilm layers stacked on the second substrate. The antenna is coupled to the feed line through an aperture.
    Type: Grant
    Filed: December 6, 2017
    Date of Patent: August 21, 2018
    Inventor: Amit Verma
  • Patent number: 10020256
    Abstract: A structure including a dual damascene feature in a dielectric layer, the dual damascene feature including a first via, a second via, and a trench, the first via, the second via being filled with a conductive material, a fuse line at the bottom of the trench on top of the first via and the second via, the fuse line including the conductive material; an insulating layer on top of the fuse line and along a sidewall of the trench, and a fill material on top of the insulating layer and substantially filling the trench.
    Type: Grant
    Filed: January 19, 2015
    Date of Patent: July 10, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Chad M. Burke, Baozhen Li, Keith Kwong Hon Wong, Chih-Chao Yang
  • Patent number: 10014439
    Abstract: Aspects of the disclosure pertain to a system and method for providing an electron blocking layer with doping control. The electron blocking layer is included in a semiconductor assembly. The electron blocking layer includes a lithium aluminate layer. The lithium aluminate layer promotes reduced diffusion of magnesium into a layer stack of the semiconductor assembly.
    Type: Grant
    Filed: July 21, 2016
    Date of Patent: July 3, 2018
    Assignee: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
    Inventors: Joseph M. Freund, John M. DeLucca
  • Patent number: 9997602
    Abstract: A semiconductor device includes transistor cells and enhancement cells. Each transistor cell includes a body zone that forms a first pn junction with a drift structure. The transistor cells may form, in the body zones, inversion channels when a first control signal exceeds a first threshold. The inversion channels form part of a connection between the drift structure and a first load electrode. A delay unit generates a second control signal which trailing edge is delayed with respect to a trailing edge of the first control signal. The enhancement cells form inversion layers in the drift structure when the second control signal falls below a second threshold lower than the first threshold. The inversion layers are effective as minority charge carrier emitters.
    Type: Grant
    Filed: December 19, 2015
    Date of Patent: June 12, 2018
    Assignee: Infineon Technologies AG
    Inventors: Johannes Georg Laven, Roman Baburske, Matteo Dainese, Christian Jaeger
  • Patent number: 9941178
    Abstract: Systems and methods for processing a semiconductor wafer includes a plasma processing chamber. The plasma processing chamber includes an exterior, an interior region with a wafer receiving mechanism and a viewport disposed on a sidewall of the plasma processing chamber providing visual access from the exterior to the wafer received on the wafer receiving mechanism. A camera is mounted to the viewport of the plasma processing chamber on the exterior and coupled to an image processor. The image processor includes pattern recognition logic to match images of emerging pattern captured and transmitted by the camera, to a reference pattern and to generate signal defining an endpoint when a match is detected. A system process controller coupled to the image processor and the plasma processing chamber receives the signal from the image processor and adjusts controls of one or more resources to stop the etching operation.
    Type: Grant
    Filed: November 16, 2016
    Date of Patent: April 10, 2018
    Assignee: Lam Research Corporation
    Inventors: Alan Jeffrey Miller, Evelio Sevillano, Jorge Luque, Andrew D. Bailey, III, Qing Xu
  • Patent number: 9941201
    Abstract: In one embodiment, an integrated circuit die includes first and second inductor structures, a first ground conductor, a second ground conductor and a conductive trace. The first ground conductor provides a first ground pathway for the first inductor structure. The second ground conductor provides a second ground pathway for the second inductor structure. The conductive trace coupled between the first and second ground conductors may magnetically decouple the first and second inductor structures. In addition, the integrated circuit die may also include conductive guard ring structures that surround the first and second inductor structures. One of the conductive guard ring structures may be connected to the first grounding pathway and the other conductive guard ring structure may be connected to the second grounding pathway. The conductive guard ring structures may further magnetically decouple the first and second inductor structures.
    Type: Grant
    Filed: February 2, 2016
    Date of Patent: April 10, 2018
    Assignee: Altera Corporation
    Inventors: Xiaohong Jiang, Nathaniel Wright Unger, Kyung Suk Oh
  • Patent number: 9935124
    Abstract: Split memory cells can be provided within an alternating stack of insulating layers and word lines. At least one lower-select-gate-level electrically conductive layers and/or at least one upper-select-level electrically conductive layers without a split memory cell configuration can be provided by limiting the levels of separator insulator structures within the levels of the word lines. At least one etch stop layer can be formed above at least one lower-select-gate-level spacer material layer. An alternating stack of insulating layers and spacer material layers is formed over the at least one etch stop layer. Separator insulator structures are formed through the alternating stack employing the etch stop layer as a stopping structure. Upper-select-level spacer material layers can be subsequently formed. The spacer material layers and the select level material layers are formed as, or replaced with, electrically conductive layers.
    Type: Grant
    Filed: July 26, 2016
    Date of Patent: April 3, 2018
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Masatoshi Nishikawa, Masafumi Miyamoto, Hiroyuki Ogawa
  • Patent number: 9935123
    Abstract: An alternating stack of sacrificial material layers and insulating layers is formed over a substrate. Replacement of sacrificial material layers with electrically conductive layers can be performed employing a subset of openings. A predominant subset of the openings is employed to form memory stack structures therein. A minor subset of the openings is employed as access openings for introducing an etchant to remove the sacrificial material layers to form lateral recesses and to provide a reactant for depositing electrically conductive layers in the lateral recesses. By distributing the access openings across the entirety of the openings and eliminating the need to employ backside trenches for replacement of the sacrificial material layers, the size and lateral extent of backside trenches can be reduced to a level sufficient to accommodate only backside contact via structures.
    Type: Grant
    Filed: July 26, 2016
    Date of Patent: April 3, 2018
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Masatoshi Nishikawa, Masafumi Miyamoto, James Kai
  • Patent number: 9929269
    Abstract: Embodiments of the present disclosure include a semiconductor device, a FinFET device, and methods for forming the same. An embodiment is a semiconductor device including a first semiconductor fin extending above a substrate, the first semiconductor fin having a first lattice constant, an isolation region surrounding the first semiconductor fin, and a first source/drain region in the first semiconductor fin, the first source/drain having a second lattice constant different from the first lattice constant. The semiconductor device further includes a first oxide region along a bottom surface of the first source/drain region, the first oxide region extending into the isolation region.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: March 27, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Cheng Ching, Chih-Hao Wang, Ching-Wei Tsai, Zhiqiang Wu, Jean-Pierre Colinge
  • Patent number: 9927654
    Abstract: It is an object to provide a display device of which image display can be favorably recognized. Another object is to provide a manufacturing method of the display device with high productivity. Over a substrate, a pixel electrode that reflects incident light through a liquid crystal layer, a light-transmitting pixel electrode, and a structure whose side surface is covered with a reflective layer and which is positioned to overlap with the light-transmitting pixel electrode are provided. The structure is formed over a light-transmitting etching-stop layer, and the etching-stop layer remains below the structure as a light-transmitting layer.
    Type: Grant
    Filed: April 3, 2015
    Date of Patent: March 27, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Masami Jintyou, Yamato Aihara
  • Patent number: 9911702
    Abstract: A semiconductor package structure and a fabrication method thereof are provided. The fabrication method comprises: providing a substrate strip, the substrate strip comprising a plurality of substrate units; disposing a plurality of chips on the plurality of substrate units; disposing a packaging encapsulant on the substrate strip to encapsulate the chips; forming a warp-resistant layer on a top surface of the packaging encapsulant; and dividing the substrate strip to separate the plurality of substrate units to further fabricate a plurality of semiconductor package structures, wherein the warp-resistant layer is formed of a selected material with a selected thickness to make a variation of warpage of the semiconductor package structure at a temperature between 25° C. and 260° C. to be smaller than 560 ?m.
    Type: Grant
    Filed: May 2, 2014
    Date of Patent: March 6, 2018
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Tien-Szu Chen, Sheng-Ming Wang, Kuang-Hsiung Chen, Yu-Ying Lee