Patents Examined by Matthew Reames
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Patent number: 10128362Abstract: A layer structure for a normally-off transistor has an electron-supply layer made of a group-III-nitride material, a back-barrier layer made of a group-III-nitride material, a channel layer between the electron-supply layer and the back-barrier layer, made of a group-III-nitride material having a band-gap energy that is lower than the band-gap energies of the other layer mentioned. The material of the back-barrier layer is of p-type conductivity, while the material of the electron-supply layer and the material of the channel layer are not of p-type conductivity, the band-gap energy of the electron-supply layer is smaller than the band-gap energy of the back-barrier layer. In absence of an external voltage a lower conduction-band-edge of the third group-III-nitride material in the channel layer is higher in energy than a Fermi level of the material in the channel layer.Type: GrantFiled: September 8, 2017Date of Patent: November 13, 2018Assignee: AZURSPACE Solar Power GmbHInventors: Stephan Lutgen, Saad Murad
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Patent number: 10128260Abstract: A semiconductor device includes a substrate including a cell region and a peripheral region adjacent to the cell region, a cell stack structure located in the cell region, the cell stack structure including vertical memory strings, a circuit located in the peripheral region, the circuit driving the vertical memory strings, and an interlayer insulating layer formed on the substrate to cover the cell stack structure and the circuit, and including air gaps located between the cell region and the peripheral region.Type: GrantFiled: July 5, 2016Date of Patent: November 13, 2018Assignee: SK Hynix Inc.Inventor: Sung Jae Chung
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Patent number: 10128405Abstract: A method of producing an optoelectronic component, comprising the method steps: A) providing a growth substrate (1); B) growing at least one semiconductor layer (2) epitaxially, to produce an operationally active zone; C) applying a metallic mirror layer (3) to the semiconductor layer (2); D) applying at least one contact layer (8) for electronic contacting of the component; E) detaching the growth substrate (1) from the semiconductor layer (2), so exposing a surface of the semiconductor layer (2); and F) structuring the semiconductor layer (2) by means of an etching method from the side of the surface which was exposed in method step E).Type: GrantFiled: June 3, 2009Date of Patent: November 13, 2018Assignee: OSRAM Opto Semiconductors GmbHInventors: Stephan Kaiser, Andreas Ploessl
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Patent number: 10121842Abstract: A display device and a method of manufacturing the same are disclosed. In one aspect, the display device includes a substrate including a separation area and a plurality of pixel formed over the substrate. The separation area is formed between adjacent pixels, and a plurality of through holes are respectively defined by a plurality of surrounding inner surfaces of the separation area, and wherein each of the inner surfaces passes through the substrate. The display device also includes an encapsulation layer formed over the substrate and covering the inner surfaces of the separation area.Type: GrantFiled: October 16, 2015Date of Patent: November 6, 2018Assignee: Samsung Display Co., Ltd.Inventors: Kwanghoon Lee, Mugyeom Kim
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Patent number: 10121899Abstract: A thin film transistor substrate includes a first thin film transistor disposed having a polycrystalline semiconductor layer, a first gate electrode on the polycrystalline semiconductor layer, a first source electrode and a first drain electrode; a first gate insulating layer between the polycrystalline semiconductor layer and the first gate electrode; a second thin film transistor disposed having an oxide semiconductor layer on the first gate electrode, a second gate electrode on the oxide semiconductor layer, a second source electrode and a second drain electrode; an intermediate insulating layer disposed on the first gate electrode and under the oxide semiconductor layer; and a second gate insulating layer on the intermediate insulating layer and under the first source electrode, the first drain electrode and the second gate electrode.Type: GrantFiled: November 16, 2016Date of Patent: November 6, 2018Assignee: LG Display Co., Ltd.Inventors: Kyeongju Moon, Soyoung Noh, Hyunsoo Shin, Wonkyung Kim
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Patent number: 10121768Abstract: A face-to-face semiconductor assembly is characterized in that first and second semiconductor devices are face-to-face mounted on two opposite sides of a first routing circuitry and is further electrically connected to an interconnect board through the first routing circuitry. The interconnect board has a heat spreader to provide thermal dissipation for the second semiconductor device, and a second routing circuitry formed on the heat spreader and electrically coupled to the first routing circuitry. The first routing circuitry provides primary fan-out routing for the first and second semiconductor devices, whereas the second routing circuitry provides further fan-out wiring structure for the first routing circuitry.Type: GrantFiled: May 26, 2016Date of Patent: November 6, 2018Assignee: BRIDGE SEMICONDUCTOR CORPORATIONInventors: Charles W. C. Lin, Chia-Chung Wang
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Patent number: 10121701Abstract: Embodiments of substrates, semiconductor devices and methods are shown that include elongated structures to improve conduction. Elongated structures and methods are also shown that provide electromagnetic isolation to reduce noise in adjacent components.Type: GrantFiled: July 26, 2016Date of Patent: November 6, 2018Assignee: Intel CorporationInventors: Harold Ryan Chase, Mihir K. Roy, Mathew J. Manusharow, Mark Hlad
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Patent number: 10115816Abstract: A semiconductor device is provided. The device includes an n? type layer with a trench disposed in a first surface of an n+ type silicon carbide substrate. An n+ type region and a first p type region are disposed at the n? type layer and at a lateral surface of the trench. A plurality of second p type regions are disposed at the n? type layer and spaced apart from the first p type region. A gate electrode includes a first and a plurality of second gate electrodes disposed at the trench and extending from the first gate electrode, respectively. A source electrode is disposed on and insulated from the gate electrode. A drain electrode is disposed on a second surface of the n+ type silicon carbide substrate. The source electrode contacts the plurality of second p type regions spaced apart with the n? type layer disposed therein.Type: GrantFiled: June 20, 2016Date of Patent: October 30, 2018Assignee: Hyundai Motor CompanyInventors: Dae Hwan Chun, Youngkyun Jung, Nackyong Joo, Junghee Park, Jong Seok Lee
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Patent number: 10115809Abstract: A semiconductor memory device and a method of manufacturing the same are provided. The device includes a semiconductor substrate in which active regions and isolation regions are alternately defined, and a support region is defined in a direction crossing the active regions and the isolation regions, first trenches formed in the isolation regions, second trenches formed under the first trenches in the active regions and the isolation regions; and a support layer formed under the first trenches in the support region.Type: GrantFiled: April 22, 2015Date of Patent: October 30, 2018Assignee: SK Hynix Inc.Inventors: Yun Kyoung Lee, Jung Ryul Ahn
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Patent number: 10115744Abstract: The present disclosure provides an array substrate, including a substrate, a first functional layer configured on one side of the substrate, a first insulating layer configured on the first functional layer facing away from the substrate, a second functional layer configured on the first insulating layer facing away from the substrate, a second insulating layer configured on the second functional layer facing away from the substrate, a third functional layer configured on the second insulating layer facing away from the substrate, a third insulating layer configured on the third functional layer facing away from the substrate, a fourth functional layer configured on the third insulating layer facing away from the substrate, and a plurality of through-holes configured to electrically connect different functional layers, wherein the depth of any through-holes does not exceed the thickness of two adjacent insulating layers.Type: GrantFiled: June 20, 2016Date of Patent: October 30, 2018Assignees: Shanghai Tianma AM-OLED Co., Ltd., Tianma Micro-electronics Co., Ltd.Inventors: Qi Li, Dong Qian, Duzen Peng
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Patent number: 10115763Abstract: A semiconductor device, which is configured as a backside illuminated solid-state imaging device, includes a stacked semiconductor chip which is formed by bonding two or more semiconductor chip units to each other and in which, at least, a pixel array and a multi-layer wiring layer are formed in a first semiconductor chip unit and a logic circuit and a multi-layer wiring layer are formed in a second semiconductor chip unit; a semiconductor-removed region in which a semiconductor section of a part of the first semiconductor chip unit is completely removed; and a plurality of connection wirings which is formed in the semiconductor-removed region and connects the first and second semiconductor chip units to each other.Type: GrantFiled: September 28, 2017Date of Patent: October 30, 2018Assignee: Sony CorporationInventors: Kazuichiroh Itonaga, Machiko Horiike
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Patent number: 10115761Abstract: A solid-state imaging device includes a photoelectric conversion unit, a transistor, and an element separation region separating the photoelectric conversion unit and the transistor. The photoelectric conversion unit and the transistor constitute a pixel. The element separation region is formed of a semiconductor region of a conductivity type opposite to that of a source region and a drain region of the transistor. A part of a gate electrode of the transistor protrudes toward the element separation region side beyond an active region of the transistor. An insulating film having a thickness substantially the same as that of a gate insulating film of the gate electrode of the transistor is formed on the element separation region continuing from a part thereof under the gate electrode of the transistor to a part thereof continuing from the part under the gate electrode of the transistor.Type: GrantFiled: March 20, 2017Date of Patent: October 30, 2018Assignee: Sony Semiconductor Solutions CorporationInventor: Kazuichiro Itonaga
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Patent number: 10109627Abstract: A method of fabricating a semiconductor device is provided. The method may include steps of receiving a device that includes a source/drain, a gate, a gate spacer formed on a sidewall of the gate, and a dielectric component formed over the source/drain, forming a recess in a top surface of the dielectric component; forming a dielectric layer over the top surface of the dielectric component and over the recess, such that a portion of the dielectric layer assumes a recessed shape; and etching a contact hole through the dielectric layer and the dielectric component, the contact hole exposing the source/drain.Type: GrantFiled: March 8, 2016Date of Patent: October 23, 2018Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chih-Han Lin, Che-Cheng Chang, Horng-Huei Tseng
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Patent number: 10103329Abstract: The present invention provides a non-volatile switching element that can be applied to a programmable-logic wiring changeover switch and in which an electrochemical reaction is used. Of the two electrodes for applying a bias voltage to the variable resistance layer of the non-volatile switching element, the electrode that does not feed metal ions to the variable resistance layer when the switch is in the ON state is made from a ruthenium alloy. The ruthenium alloy includes ruthenium and a metal in which the standard Gibbs energy of forming ?G when metal ions are generated from the metal is higher in the negative direction than ?G of ruthenium. As a result, it becomes possible to maintain the low-resistance state in the ON state for a longer period of time without increasing the amount of electrical current required when a switch is made between the ON state and the OFF state.Type: GrantFiled: June 3, 2013Date of Patent: October 16, 2018Assignee: NEC CORPORATIONInventors: Naoki Banno, Munehiro Tada, Toshitsugu Sakamoto
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Patent number: 10103095Abstract: A method to produce a semiconductor package or system-on-flex package comprising bonding structures for connecting IC/chips to fine pitch circuitry using a solid state diffusion bonding is disclosed. A plurality of traces is formed on a substrate, each respective trace comprising five different conductive materials having different melting points and plastic deformation properties, which are optimized for both diffusion bonding of chips and soldering of passives components.Type: GrantFiled: October 6, 2016Date of Patent: October 16, 2018Assignee: Compass Technology Company LimitedInventors: Kelvin Po Leung Pun, Chee Wah Cheung
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Patent number: 10096641Abstract: According to one embodiment, a CMOS image sensor includes a photoelectric conversion element and an amplifier transistor. The photoelectric conversion element converts incident light into an electric signal. The amplifier transistor has a heterojunction in which a Ge layer and an SiGeSn layer are joined together, as a channel region and amplifies the electric signal resulting from conversion by the photoelectric conversion element.Type: GrantFiled: March 10, 2016Date of Patent: October 9, 2018Assignee: Kabushiki Kaisha ToshibaInventors: Keiji Ikeda, Tsutomu Tezuka
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Patent number: 10096705Abstract: An integrated high side gate driver structure for driving a power transistor. The structure includes a semiconductor substrate having a first polarity semiconductor material in which a first well diffusion including a second polarity semiconductor material is formed. An outer wall of the first well diffusion is abutted to the substrate. A second well diffusion, having first polarity semiconductor material, is arranged inside the first well diffusion such that an outer wall of the second well diffusion abuts an inner wall of the first well diffusion. The structure includes a gate driver having high side positive and negative supply voltage ports, and a driver input and output. The gate driver includes a transistor driver in the second well diffusion such that control and output terminals of the transistor driver are coupled to the driver input and output, respectively.Type: GrantFiled: January 16, 2015Date of Patent: October 9, 2018Assignee: Infineon Technologies Austria AGInventors: Allan Nogueras Nielsen, Mikkel Høyerby
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Patent number: 10096376Abstract: A device for the storage and/or processing of quantum information comprises: a body (6), formed from a material having negligible net nuclear or electronic magnetic field; a set of data entities (4) embedded in said body, each having a plurality of magnetic field states; a set of probes (2), offset from the body, arranged to acquire internal phase shifts due to the magnetic fields of said data entities; wherein the probes (2) are each arranged to move relative to a plurality of data entities (4) in order that each probe (2) acquires an internal phase shift from the plurality of data entities (4); and means for reading each probe (2), thereby establishing a parity of the plurality of data entities (4).Type: GrantFiled: February 23, 2015Date of Patent: October 9, 2018Assignee: OXFORD UNIVERSITY INNOVATION LIMITEDInventors: Simon Benjamin, John Morton
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Patent number: 10090269Abstract: A bump structure includes a first bump disposed on a substrate, the first bump including a first metal, at least one antioxidant member surrounded by the first bump, the at least one antioxidant member including a second metal having an ionization tendency greater than an ionization tendency of the first metal, and a second bump disposed on the first bump and the at least one antioxidant member.Type: GrantFiled: January 17, 2017Date of Patent: October 2, 2018Assignee: SAMSUNG DISPLAY CO., LTD.Inventors: Ho-Seok Han, Nam-Hee Park
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Patent number: 10090233Abstract: A semiconductor device has a first semiconductor die and second semiconductor die with a conductive layer formed over the first semiconductor die and second semiconductor die. The second semiconductor die is disposed adjacent to the first semiconductor die with a side surface and the conductive layer of the first semiconductor die contacting a side surface and the conductive layer of the second semiconductor die. An interconnect, such as a conductive material, is formed across a junction between the conductive layers of the first and second semiconductor die. The conductive layer may extend down the side surface of the first semiconductor die and further down the side surface of the second semiconductor die. An extension of the side surface of the first semiconductor die can interlock with a recess of the side surface of the second semiconductor die. The conductive layer extends over the extension and into the recess.Type: GrantFiled: July 25, 2016Date of Patent: October 2, 2018Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Francis J. Carney, Jefferson W. Hall, Michael J. Seddon