Abstract: A heat treatment method which can prevent heat deformation of a substrate caused during a heat treatment process on the substrate with a thin film formed on its surface is provided. The heat treatment method in accordance with the present invention includes (a) stacking a second substrate 10b on a first substrate 10a; and (b) stacking a weight 20 on the second substrate 10b, wherein the first substrate 10a and the second substrate 10b are stacked, with thin films 12 of the substrates 10a and 10b being in contact with each other. In accordance with the present invention, deformation of the substrate can be prevented by stacking the substrates, with thin films formed on the substrates being in contact with each other, and placing a weight on the stacked substrates during the heat treatment process.

Abstract: A method is provided for producing semiconductor nanoparticles comprising: (i) dissolving a semiconductor compound or mixture of semiconductor compounds in a solution; (ii) generating spray droplets of the resulting solution of semiconductor compound(s); (iii) vaporizing the solvent of said spray droplets, consequently producing a stream of unsupported semiconductor nanoparticles; and (iv) collecting said unsupported semiconductor nanoparticles on a support.

Abstract: A method for fabricating a semiconductor device comprises patterning a layer of photoresist material to form a plurality of mandrels. The method further comprises depositing an oxide material over the plurality of mandrels by an atomic layer deposition (ALD) process. The method further comprises anisotropically etching the oxide material from exposed horizontal surfaces. The method further comprises selectively etching photoresist material.

Abstract: A method of forming a display device is provided.

Abstract: Panel level methods and systems for packaging integrated circuits are described. In a method aspect of the invention, a substrate formed from a sacrificial semiconductor wafer is provided having a plurality of metallized device areas patterned thereon. Each device area includes an array of metallized contacts and a die attach area. Dice are mounted onto each device area and electrically connected to the array of contacts. The entire surface of the substrate including the dice, contacts and electrical connections is then encapsulated. The semiconductor wafer is then sacrificed leaving portions of the contacts exposed allowing the contacts to be used as external contacts in an IC package. In various embodiments, other structures, including die attach pads, may be incorporated into the device areas as desired. By way of example, structures having thicknesses in the range of 10 to 20 microns are readily attainable.

Abstract: A device disclosed herein includes a first layer, a second layer, and a first plurality of nanowires established between the first layer and the second layer. The first plurality of nanowires is formed of a first semiconductor material. The device further includes a third layer, and a second plurality of nanowires established between the second and third layers. The second plurality of nanowires is formed of a second semiconductor material having a bandgap that is the same as or different from a bandgap of the first semiconductor material.

Abstract: A method of manufacturing a semiconductor device including a semiconductor layer and a dielectric layer deposited on the semiconductor layer, including: forming the semiconductor layer; performing a surface treatment for removing a residual carbon compound, on a surface of the semiconductor layer formed; forming a dielectric film under a depositing condition corresponding to a surface state after the surface treatment, on at least a part of the surface of the semiconductor layer on which the surface treatment has been performed; and changing a crystalline state of at least a partial region of the semiconductor layer by performing a heat treatment on the semiconductor layer on which the dielectric film has been formed.

Abstract: The present disclosure is related to a method for determining time to failure characteristics of a microelectronics device. A test structure, being a parallel connection of a plurality of such on-chip interconnects, is provided. Measurements are performed on the test structure under test conditions for current density and temperature. The test structure is arranged such that failure of one of the on-chip interconnects within the parallel connection changes the test conditions for at least one of the other individual on-chip interconnects of the parallel connection. From these measurements, time to failure characteristics are determined, whereby the change in the test conditions is compensated for.

Abstract: Apparatus and methods for detecting evaporation conditions in an evaporator for evaporating metal onto semiconductor wafers, such as GaAs wafers, are disclosed. One such apparatus can include a crystal monitor sensor configured to detect metal vapor associated with a metal source prior to metal deposition onto a semiconductor wafer. This apparatus can also include a shutter configured to remain in a closed position when the crystal monitor sensor detects an undesired condition, so as to prevent metal deposition onto the semiconductor wafer. In some implementations, the undesired condition can be indicative of a composition of a metal source, a deposition rate of a metal source, impurities of a metal source, position of a metal source, position of an electron beam, and/or intensity of an electron beam.

Abstract: Methods and apparatuses directed to high density holes and metallization are described herein. A method may include providing a dielectric layer including a plurality of holes, forming a fill material over a top surface of the dielectric layer and in the plurality of holes, and reflowing the fill material to substantially remove any voids in the plurality of holes. Other embodiments are also described.

Abstract: A method for manufacturing a liquid crystal display device is disclosed.

Abstract: A method for forming flash memory devices is provided. The method includes providing a semiconductor substrate, which comprises a silicon material and has a periphery region and a cell region. The method further includes forming an isolation structure between the cell region and the periphery region. Additionally, the method includes forming an ONO layer overlying the cell region and the periphery region. Furthermore, the method includes removing the ONO layer overlying the periphery region to expose silicon material in the periphery region. The method also includes forming a gate dielectric layer overlying the periphery region, while protecting the ONO layer in the cell region. In addition, the method includes forming a polysilicon layer overlying the cell region and the periphery region.

Abstract: An epitaxial wafer comprises a silicon substrate, a gettering epitaxial film formed thereon and containing silicon and carbon, and a main silicon epitaxial film formed on the gettering epitaxial film, in which the gettering epitaxial film has a given carbon atom concentration and carbon atoms are existent between its silicon lattices.

Abstract: A trench gate type power transistor of high performance is provided. A trench gate as a gate electrode is formed in a super junction structure comprising a drain layer and an epitaxial layer. In this case, the gate electrode is formed in such a manner that an upper surface of the epitaxial layer becomes higher than that of a channel layer formed over the drain layer. Then, an insulating film is formed over each of the channel layer and the epitaxial layer and thereafter a part of the insulating film is removed to form side wall spacers over side walls of the epitaxial layer. Subsequently, with the side wall spacers as masks, a part of the channel layer and that of the drain layer are removed to form a trench for a trench gate.

Abstract: A technique for embedding metal in a microscopic recess provided in the surface of a process object, such as a semiconductor wafer, by plasma sputtering. A film forming step and a diffusion step are alternately performed a plurality of times. The film forming step deposits a small amount of metal film in the recess. The diffusion step moves the deposited metal film towards the bottom portion of the recess. In the film forming step, bias power to be applied to a stage for supporting the wafer is set to a value ensuring that, on the surface of the wafer, the rate of metal deposition due to the drawing-in of metal particles is substantially equal to the rate of the sputter etching by plasma. In the diffusion step, the wafer is maintained at a temperature which permits occurrence of surface diffusion of the metal film deposited in the recess.

Abstract: The invention provides for an alternative and less complex method of manufacturing a bipolar transistor comprising a field plate (17) in a trench (7) adjacent to a collector region (21), which field plate (17) employs a reduced surface field (Resurf) effect. The Resurf effect reshapes the electric field distribution in the collector region (21) such that for the same collector-base breakdown voltage the doping concentration of the collector region (21) can effectively be increased resulting in a reduced collector resistance and hence an increased bipolar transistor speed. The method comprises a step of forming a base window (6) in a first base layer (4) thereby exposing a top surface of the collector region (21) and a part of an isolation region (3). The trench (7) is formed by removing the exposed part of the isolation region (3), after which isolation layers (9,10) are formed on the surface of the trench (7).

Abstract: A platform-independent temperature controller system and method are provided. Included is a sensor is in communication with an integrated circuit. Further, a platform-independent temperature controller is in communication, with the sensor for controlling a temperature of the integrated circuit.

Abstract: The light emitting device 100 includes a light emitting element 101, a package for arranging the light emitting element 101, and an electrically conductive wire 106 for connecting an electrode disposed on the package and an electrode of the light emitting element. The package includes a support member 108 having a mounting portion to arrange the light emitting element 101 and defining a recess 103 to house a semiconductor element 102 which is different than the light emitting element, and a light transmissive member 107 covering at least the light emitting element 101. The package defines a hollow portion 111 between the light transmissive member 107 covering the opening of the recess 103 and an inner wall defining the recess 103.

Abstract: To provide a laser irradiation apparatus which performs alignment of an irradiated object and emits a laser beam precisely, a laser irradiation method, and a manufacturing method of a TFT with high reliability with the use of a method for precisely targeting a desired irradiation position of the laser beam. A substrate with marker is mounted on a stage formed using a material which transmits infrared light; a marker, which is provided in the substrate with marker mounted on the stage, is detected using a camera capable of sensing infrared light, and a position of the stage is controlled; a laser beam is emitted from a laser oscillator; the laser beam emitted from the laser oscillator is processed into a linear shape by an optical system, and the substrate with marker mounted on the stage is irradiated with the laser beam.

Abstract: A method includes forming a first dielectric layer over a substrate; forming nanoclusters over the first dielectric layer; forming a second dielectric layer over the nanoclusters; annealing the second dielectric layer using nitrous oxide; and after the annealing the second dielectric layer, forming a gate electrode over the second dielectric layer.