Patents Examined by Mehdi Namazi
  • Patent number: 9524401
    Abstract: There is provided a method for providing access to data securely stored in memory card. An exemplary method comprises specifying first time information corresponding to a time period and storing the first time information in the memory card. The exemplary method also comprises inserting the memory card into a terminal. The exemplary method additionally comprises determining in a control unit included in the memory card, whether the time period has lapsed. The exemplary method also comprises allowing the terminal to access the data until it is determined that the time period has lapsed.
    Type: Grant
    Filed: October 12, 2009
    Date of Patent: December 20, 2016
    Assignee: Vodafone Holding GMBH
    Inventors: Najib Koraichi, Sebastiaan Hoeksel
  • Patent number: 9514040
    Abstract: A memory storage device and a memory controller and an access method thereof are provided. The memory storage device includes a rewritable non-volatile memory chip having a plurality of physical blocks. The access method includes configuring a plurality of logical blocks to be mapped to a part of the physical blocks and dividing the logical blocks into at least a first partition and a second partition, wherein the first partition records an auto-execute file. The access method also includes determining whether a trigger signal is existent and sending a media ready message to a host system if the trigger signal is existent, so as to allow the host system to automatically run the auto-execute file and receive a first password. The access method further includes determining whether to provide the logical blocks in the second partition to the host system according to the first password received from the host system.
    Type: Grant
    Filed: June 28, 2011
    Date of Patent: December 6, 2016
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Chia-Jung Hsu, Shih-Hsien Hsu
  • Patent number: 9507536
    Abstract: Dynamically allocates a new target volume and a Flashcopy map (fcmap) for ingest upon one of a mount operation and a clone operation breaking a FlashCopy chain for creating a stable FlashCopy Map (fcmaps) for ingest while a Flashcopy backup is mounted.
    Type: Grant
    Filed: April 2, 2014
    Date of Patent: November 29, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Shay H. Akirav, Joseph W. Dain, Gregory T. Kishi, Osnat Shasha
  • Patent number: 9478263
    Abstract: Systems and methods for monitoring and controlling repetitive accesses to a dynamic random-access memory (DRAM) row are disclosed. A method for monitoring and controlling repetitive accesses to a DRAM can include dividing a bank of the DRAM into a number of logical blocks, mapping each row of the bank to one of the logical blocks, monitoring accesses to the logical blocks, and controlling accesses to the logical blocks based on the monitoring.
    Type: Grant
    Filed: January 17, 2014
    Date of Patent: October 25, 2016
    Assignee: APPLE INC.
    Inventors: Bin Ni, Kai Lun Charles Hsiung, Yanzhe Liu, Sukalpa Biswas
  • Patent number: 9465735
    Abstract: Systems and methods for uniformly interleaving memory accesses across physical channels of a memory space with a non-uniform storage capacity across the physical channels are disclosed. An interleaver is arranged in communication with one or more processors and a system memory. The interleaver identifies locations in a memory space supported by the memory channels and is responsive to logic that defines virtual sectors having a desired storage capacity. The interleaver accesses the asymmetric storage capacity uniformly across the virtual sectors in response to requests to access the memory space.
    Type: Grant
    Filed: October 3, 2013
    Date of Patent: October 11, 2016
    Assignee: QUALCOMM INCORPORATED
    Inventors: Bohuslav Rychlik, Feng Wang, Anwar Rohillah, Simon Booth
  • Patent number: 9460000
    Abstract: A method and a system of dynamically changing a page allocator are provided. The method includes determining a state of a page allocation system; and forking a child page allocator from a parent page allocator, or merging a child page allocator into a parent page allocator, based on the determination.
    Type: Grant
    Filed: January 17, 2014
    Date of Patent: October 4, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Junghyun Yoo, Sungmin Lee
  • Patent number: 9460015
    Abstract: A storage system in an embodiment of this invention comprises a non-volatile storage area for storing write data from a host, a cache area capable of temporarily storing the write data before storing the write data in the non-volatile storage area, and a controller that determines whether to store the write data in the cache area or to store the write data in the non-volatile storage area without storing the write data in the cache area, and stores the write data in the determined area.
    Type: Grant
    Filed: March 20, 2014
    Date of Patent: October 4, 2016
    Assignee: HITACHI, LTD.
    Inventors: Tomohiro Yoshihara, Akira Deguchi, Hiroaki Akutsu
  • Patent number: 9454490
    Abstract: An instruction is provided to perform invalidation of an instruction specified range of segment table entries or region table entries. The instruction can be implemented by software emulation, hardware, firmware or some combination thereof.
    Type: Grant
    Filed: April 30, 2013
    Date of Patent: September 27, 2016
    Assignee: International Business Machines Corporation
    Inventors: Timothy J Slegel, Lisa C Heller, Erwin F Pfeffer, Kenneth E Plambeck
  • Patent number: 9454329
    Abstract: In one embodiment, a system on a chip (SoC) includes a plurality of processor cores and a memory controller to control communication between the SoC and a memory coupled to the memory controller. The memory controller may be configured to send mirrored command and address signals to a first type of memory device and to send non-mirrored control and address signals to a second type of memory device. Other embodiments are described and claimed.
    Type: Grant
    Filed: April 30, 2012
    Date of Patent: September 27, 2016
    Assignee: Intel Corporation
    Inventors: Christopher E. Cox, Rebecca Z. Loop, Christopher P. Mozak
  • Patent number: 9442834
    Abstract: A data management method for a rewritable non-volatile memory module including a first memory unit and a second memory unit is provided. The method includes: grouping erasing units of the first memory unit into a data area and a spare area; and grouping the physical erasing units of the second memory unit into a data backup area and a command recording area; configuring multiple logical addresses to map to the physical erasing units associated with the data area; receiving a write command which instructs writing data; writing the data to a physical erasing unit associated with the spare area, and writing the data to a physical erasing unit associated with the data backup area; recording at least a portion of the write command in a physical erasing unit associated with the command recording area. Accordingly, data is backuped in the rewritable non-volatile memory module.
    Type: Grant
    Filed: October 2, 2012
    Date of Patent: September 13, 2016
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Yi-Hsiang Huang, Chao-Ming Chan
  • Patent number: 9423960
    Abstract: The present disclosure includes methods and devices for logical memory blocks. One method for operating a memory device includes receiving a command to operate X pages of the memory device, X being greater than Y, and executing the command by executing multiple subcommands, each subcommand operating on a logical memory block portion of the X pages, each logical memory block including at most Y pages. T is a timeout limit, N is a number of pages comprising a block of memory, and Y is number of pages that can be operated within time T.
    Type: Grant
    Filed: July 16, 2013
    Date of Patent: August 23, 2016
    Assignee: Micron Technology, Inc.
    Inventor: Ryan G. Fisher
  • Patent number: 9418022
    Abstract: According to one embodiment, a storage system includes a host device, 2 storing medium. The secure storing medium includes: a memory provided with a protected first storing region which stores secret information sent from the host device, and a second storing region which stores encoded contents; and a controller which carries out authentication processing for accessing the first storing region. The host device and the secure storing medium produce a bus key which is shared only by the host device and the secure storing medium by authentication processing, and which is used for encoding processing when information of the first storing region is sent and received between the host device and the secure storing medium. The host device has the capability to request the secure storing medium to send a status.
    Type: Grant
    Filed: October 2, 2012
    Date of Patent: August 16, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yuji Nagai, Yasufumi Tsumagari, Shinichi Matsukawa, Hiroyuki Sakamoto, Hideki Mimura
  • Patent number: 9411745
    Abstract: Methods, devices, and instructions for performing a reverse translation lookaside buffer (TLB) look-up using a physical address input, including obtaining with a first processor the physical address input, wherein the physical address input indicates a physical address corresponding to a shared memory, obtaining a first mask associated with a first virtual address from a first TLB entry within a TLB associated with the first processor, wherein the obtained first mask is a bit pattern, obtaining from the first TLB entry a first page frame number associated with the shared memory, applying the obtained first mask to the obtained first page frame number to generate a first value, applying the obtained first mask to the obtained physical address input to generate a second value, and comparing the first value and the second value to determine whether the first value and the second value match.
    Type: Grant
    Filed: October 4, 2013
    Date of Patent: August 9, 2016
    Assignee: QUALCOMM Incorporated
    Inventors: Jian Shen, Lew Go Chua-Eoan
  • Patent number: 9405474
    Abstract: A data store is configurable in terms of various tradeoffs including consistency and availability, among others. Consistency can be specified in terms of one of a myriad of configuration levels. Availability can be specified with respect to a maximum and minimum number of replicas or failure tolerance. In operation, one or more of write or read quorums can be automatically adjusted to ensure satisfaction of a specified configuration level in light of changes in the number of replicas.
    Type: Grant
    Filed: October 3, 2012
    Date of Patent: August 2, 2016
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Dharma Shukla, Karthik Raman
  • Patent number: 9400723
    Abstract: A storage system is provided with a plurality of physical storage devices, a cache memory, a control device that is coupled to the plurality of physical storage devices and the cache memory, and a buffer part. The buffer part is a storage region that is formed by using at least a part of a storage region of the plurality of physical storage devices and that is configured to temporarily store at least one target data element that is to be transmitted to a predetermined target. The control device stores a target data element into a cache region that has been allocated to a buffer region (that is a part of the cache memory and that is a storage region of a write destination of the target data element for the buffer part). The control device transmits the target data element from the cache memory.
    Type: Grant
    Filed: March 15, 2012
    Date of Patent: July 26, 2016
    Assignee: Hitachi, Ltd.
    Inventor: Akira Deguchi
  • Patent number: 9396107
    Abstract: In a memory system including a flash memory and a memory controller having a cache memory and a nonvolatile random access memory (NVRAM), a method of operating the memory system includes; receiving a write request specifying a write operation directed to a page of a designated active write block in the flash memory, storing a page mapping table for the active write block in the cache memory, generating update information for the page mapping table stored in the cache memory as a result of executing the write operation, and storing the update information in the NVRAM, and storing an updated version of the page mapping table in the flash memory after execution of the write operation is complete.
    Type: Grant
    Filed: November 14, 2013
    Date of Patent: July 19, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Joon-Ho Lee, Hyun-Seok Kim
  • Patent number: 9372792
    Abstract: A method of managing a non-volatile memory module, the method may include: receiving data sectors during a set of at least one write transactions; selecting, out of the currently buffered portions, to-be-merged memory space portions and to-be-cleaned memory space portions; merging, for each to-be-merged memory space portion and before the buffer becomes full, data sectors that belong to the to-be-merged memory space portion into a sequential portion of the non-volatile memory module, wherein the sequential portion differs from the buffer; and copying, for each to-be-cleaned memory space and before the buffer becomes full, data sectors that belong to the to-be-cleaned memory space portion into a buffer block of the buffer.
    Type: Grant
    Filed: October 10, 2013
    Date of Patent: June 21, 2016
    Assignee: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
    Inventors: Hanan Weingarten, Michael Katz, Ilan Bar
  • Patent number: 9361103
    Abstract: A method is provided for executing a cacheable store. The method includes determining whether to replay a store instruction to re-acquire one or more cache lines based upon a state of the cache line(s) and an execution phase of the store instruction. The store instruction is replayed in response to determining to replay the store instruction. An apparatus is provided that includes a store queue (SQ) configurable to determine whether to replay a store instruction to re-acquire one or more cache lines based upon a state of the cache line(s) and an execution phase of the store instruction. Computer readable storage devices for adapting a fabrication facility to manufacture the apparatus are provided.
    Type: Grant
    Filed: November 2, 2012
    Date of Patent: June 7, 2016
    Assignee: Advanced Micro Devices, Inc.
    Inventors: David A. Kaplan, Jeff Rupley, Tarun Nakra
  • Patent number: 9329999
    Abstract: In an exemplary storage system, a processor assigns an unused process to a read request designating an area of a logical volume. The processor determines whether the data designated by the read request is in a cache memory, based on a first identifier for identifying the area designated by the read request. When the designated data is not in the cache memory and a part of physical volumes providing the logical volume is a first kind of physical volume, the processor stores the first identifier associated with an identifier for identifying an area allocated in the cache memory. When the designated data is not in the cache memory and a part of the physical volumes is a second kind of physical volume, the processor stores a second identifier for identifying the process assigned to the read request associated with an identifier for identifying an area allocated in the cache memory.
    Type: Grant
    Filed: July 29, 2014
    Date of Patent: May 3, 2016
    Assignee: Hitachi, Ltd.
    Inventors: Tomohiro Yoshihara, Akira Deguchi, Hiroaki Akutsu
  • Patent number: 9317438
    Abstract: A cache memory apparatus according to the present invention includes a cache memory that caches an instruction code corresponding to a fetch address and a cache control circuit that controls the instruction code to be cached in the cache memory. The cache control circuit caches an instruction code corresponding to a subroutine when the fetch address indicates a branch into the subroutine and disables the instruction code to be cached when the number of the instruction codes to be cached exceeds a previously set maximum number.
    Type: Grant
    Filed: November 2, 2012
    Date of Patent: April 19, 2016
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Takashi Kitahara