Abstract: A system for producing output signals representative of the densities of coloring agents such as process inks, toners, or the like used in producing color reproductions which are color corrected for the effects of linearity failures of the coloring agents at various densities and combinations thereof. The preferred system includes a scanner for providing input signals representative of the primary color readings of an original color image and a microcomputer having a memory for storing data representative of increments of primary color readings and corresponding agent color densities, contribution factors, and contribution correction factors. In use, the microcomputer is operated to determine the final coloring agent densities as respective functions of corresponding initial agent color densities and respective contribution amounts from the other agent colors and to produce output signals representative thereof.

Abstract: A printing apparatus of the type in which printing is carried out in accordance with data transmitted from a host computer. The data transmitted from the host computer is temporarily stored in a input buffer provided in the printing apparatus and the printing is carried out while fetching the data stored therein. When a clear switch is depressed to halt the printing operation, the printing operation is halted and the residual ensuing data remained in the host computer is not fed into the input buffer for storage but led to a data receiving means, whereby the residual ensuing data of the last block of data and another block of forthcoming data are not mixing with each other in the line buffer and thus the subsequent printing for another block can be started from the beginning.

Abstract: Dimensioned sketches are analyzed using graph theoretical concepts to determine whether dimension constraints are sufficient to define unique geometry and are nonredundant.

Abstract: An image memory write control apparatus includes an image memory unit which is divided into a plurality of block memories. For each of the block memories there are provided a double buffer memory and a timing control circuit. Based on the contents of lower digits of coordinate data supplied from a linear interpolation operation unit, there are generated control signals for designating the functions of the two memory planes of each of the double buffer memories, and for selecting the block memories for receipt of image data from a designated memory plane.

Abstract: A circuit which computes the scan position of any pixel on the display as the sum of the number of scan lines multiplied by the number of pixels per scan line plus the number of pixels on the scan line to the particular position using an adder for a changing portion of the computation and an incrementer for a constant portion of the computation and combining the two of these to produce a result which accomplishes in a relatively economic fashion what would normally require an inordinate number of gates to obtain a variety of screen resolutions which are not simply powers of two multiples of one another.

Abstract: A coprocessor device having a virtual storage system comprises a master microprocessor, a slave microprocessor controlled by the master microprocessor to execute an operation designated by instructions for the slave microprocessor, a main storage for storing information and data for the master microprocessor and the slave microprocessor, and an external storage coupled to the main storage for storing information and data for the master microprocessor and/or the slave microprocessor. The master microprocessor has a circuit for detecting whether or not the memory location required by a certain instruction is physically present in the main storage. This detecting circuit operates to enable access to the main storage or to generate an interrupt to transfer information and/or data from the external storage to the main storage, in accordance with the content of the instruction.

Abstract: A personal computer (PC) running on MS/DOS interactively and graphically creates or modifies definitions for print fonts, electronic forms, page compositions and sketches and includes a function for converting the definitions for transfer to a mainframe computer facility for use by the mainframe printer control function and printer. The PC further includes functions for creating or modifying character arrangements, EFORM arrangements, page composition arrangements and sketch arrangements where the arrangements include all of the components required to print the entity. The mainframe computer comprises an OS1100 system with PERCON for controlling a laser printer. The invention includes a function at the mainframe facility for converting the definitions transferred thereto from the PC into omnibus elements containing the data required by PERCON to print the entities. The omnibus elements are stored in a user library.

Abstract: A data communications system for a computer for transferring data between the memory of the computer and one or more peripheral devices without requiring an interrupt context switch. The data communications system includes a number of specialized registers in the central processing unit of a computer, a computer memory, a data storage location associated with one or more peripheral devices, and a bus connecting the data storage location to the memory. The specialized registers in the central processing unit are dedicated exclusively to processing data transfers between the memory and the data storage location associated with the peripheral devices. Data transfers between the computer memory and the data storage location associated with the peripheral devices are made under the control of the central processing unit with the use of the special registers without the execution of an interrupt context switch.

Abstract: A microcomputer system has a first, low order address, memory soldered to the planar printed circuit board and can accept further memory pluggable into a socket on the board. At power on self test, the memories are tested, and, if an error is detected in the first memory, this memory is disabled by directing the lowest order memory addresses to the second memory and reducing the highest order addresses by the number of locations in the first memory.

Abstract: In order, for example, to expand the input and output of a microcomputer (7) having a serial input/output capability, a parallel data input port (2 or 3) or output port (4 or 5) is selected by clocking serial selection bits from a serial data line (1) into a first shift register (56) and then enabling a latch (58) for the register parallel output (57). This results in a change in level on a particular one of a set of a parallel output lines (35,36,49,50) which corresponds to the particular group of selection bits written, and hence to a particular port. If the selected port is an output port the change in level results in the strobing of a latch (43 or 44) corresponding to that port, and hence the transfer of the contents of a further shift register (39 or 40) corresponding to that port. These contents are previously written in from the serial data path (1), each further shift register (39,40) being connected in cascade with the first register.

Abstract: An office automation system that provides for the incorporation of documents of all types by integrating images into the system. A minicomputer-based system includes applications such as word processing, data base, and mail, each of which can access image documents. Bulk storage of document images is provided using a variety of storage media such as microfilm, microfiche, and optical disks. An image access subsystem provides to each of the office automation applications uniform access to images stored on all of the media. The image access subsystem can use a hardward controller to handle some of the complexity of retrieval of images from the image storage devices. A relational data base system is used to organize the stored images so as to provide flexible access to the images and to isolate any effects of reconfiguration of the image storage system.

Abstract: A technique is described for performing a fast write operation. A host write request, which would normally be serviced by an immediate physical write to a data storage device, is instead written to cache and nonvolatile storage in the data storage device controller. Then, the controller signals the host that the write operation is complete and does not update the physical data storage device until later. A journal log is also used to provide recovery capability in the event of system failure. This technique provides high performance for the units' operation while assuring integrity by keeping two copies of the write operation until the physical update transpires.

Abstract: A central subsystem of a data processing system includes a writable control store which is loaded with firmware to control the central subsystem operations. The central subsystem logic is responsive to a sequence of commands from a system management facility to load the control store and verify that the control store firmware is loaded correctly.

Abstract: Apparatus and methods for displaying two and three dimensional graphics within a plurality of windows on a display system. The display system includes a central processing unit (CPU) which provides RGB data to a bit-mapped display memory coupled to a cathode ray tube (CRT) display. A Z-buffer memory is provided with a Z-value for each RGB data point corresponding to a point on the object to be displayed. The Z-buffer is organized such that the value of the entire n bit buffer (0 through 2.sup. n-1) identifies the window in which the graphics and/or text is displayed. For windows in which only two dimensional (2D) graphics/text is displayed, the Z-value is the same for both the window and each RGB point of the image. For windows which display three dimensional (3D) graphics, a range of Z-values for the buffer are provided which define the window boundaries. Images to be displayed within a 3D window must have Z-values which fall within the particular window's Z-value range.

Abstract: This circuitry permits equal access to a shared resource by a number of central processing units (CPUs). In a multiple CPU arrangement, common resource contention problems arise, when several CPUs attempt to access the common resource. To resolve these contention problems, this circuitry is an improvement to arbitration ring circuitry. The circuitry of this invention permits each of the CPUs equal access to the common resource during situations in which each CPU is constantly generating requests (high bandwith utilization) for access to the common resource. This invention is particularly useful for systems in which a large number of CPUs must have their local memory rapidly reloaded from a common memory source. Reloading procedures for large numbers of CPUs require up to an hour. By employing the present invention, these reloading times can be cut from one hour to approximately 5 minutes.

Abstract: A multiple window display system includes a display device and a screen ownership area pointing to the identity of the window which is to contribute the data for each display area of the display device. An ordered list is maintained of the active windows in the priority order thereof. Means are provided to regenerate the screen ownership area from the ordered list, on each change made to the list, in terms of list position per device display area, by overwriting, progressing through the list in order of increasingly significantly priority order, the list indicating, in each position thereof, the identity of the window having the respective priority. The list contains the addresses of the windows in storage and the type thereof. The screen ownership area is reset to the lowest potential priority list position value and is overwritten.

Abstract: A secure system includes a secure central processor unit, an input/output emulator, a number of commodity controller boards and a number of commodity memory boards. Apparatus in the secure CPU and firmware in the I/O emulator maintain the security of the overall system.

Abstract: An information processing system for performing a prior control in determining a branch destination address by an execution of a branch instruction, includes a branch history table for storing prior branch destination address due to the fact that the possibility of branching to the prior branch destination address is high. By storing, in the branch history table, the branch destination address together with residual instruction number from the branch destination address to segment boundary, it is possible to restrict an instruction prefetch beyond the boundary area of a main memory to thereby prevent an excessive request from being produced. By storing, in the branch history table, the branch destination address together with mode information, it is possible to prevent an access to the main memory in a different mode from that at an instruction prefetch from occurring.

Abstract: An interactive data processing implemented method and apparatus for composing and editing a document in which a user is afforded great flexibility in defining the document geometry and in changing the data presentation characteristics associated with non-continguous portions of the document. According to the present invention, each of the distinct line formats in the document is assigned an abstract format name (i.e., a Named Format) and each line in the document is associated with a distinct format. A Names Format is associated with each fragment of the text in the document. Likewise, an abstract means, referred to as a Named Font, is associated with a wide range of specificable data presentation characteristics which operate over a range of the document defined by the user. The same Named Format and Names Font is used to simultaneously specify different data presentation characteristics for the output device of the system.

Abstract: A method and means for extending the collation functions of a sorting program (SORT) enable the program to permute, combine, or filter input records having collating characteristics that are not recognized by the SORT program. The extension includes provision of an extended function support program (EFS) that can be invoked by and concurrently executed with the sorting program. The EFS program is provided with a modality for modifying control statements received by the SORT program but executable only against records having the non-recognized collating characteristics. The EFS program modifies such control statements to a form executable by the SORT program. The EFS program also is provided with the capability of modifying the collating characteristic fields of records which are to be processed by the SORT program, the modification resulting in the provision of the records of counterpart collating characteristics recognized by the SORT program.