Patents Examined by Michael C. Kessell
  • Patent number: 5313427
    Abstract: A nonvolatile memory has pairs of cells in which each cell includes a control gate, a floating gate and a source/drain diffusion. A first cell in each of the pairs is producible to have one value of floating-gate to diffusion capacitance. A second cell in each of the pairs is producible to have a second value of floating-gate to diffusion capacitance different from the first value. The memory includes a first circuit for applying a first erasing pulse to the control gates and the diffusions of the first cells of the pairs and includes a second circuit for applying a second erasing pulse to the control gates and the diffusions of the second cells of the pairs. The first erasing pulse is adjustable to have a different magnitude than the second erasing pulse in order to narrow the margin of erased threshold voltages and thereby compensate for misalignment.
    Type: Grant
    Filed: September 20, 1991
    Date of Patent: May 17, 1994
    Assignee: Texas Instruments Incorporated
    Inventors: John F. Schreck, David J. McElroy, Pradeep L. Shah
  • Patent number: 5309391
    Abstract: A two-transistor, single capacitor ferroelectric memory cell in which a stepped voltage is applied to the drive line for writing polarization states into the capacitor. The isolation transistors are driven into cut off during the intermediate voltage level of the drive line, thereby isolating the ferroelectric capacitor plates with a balanced voltage to enhance full polarization of the ferroelectric domains, irrespective of the polarization state.
    Type: Grant
    Filed: October 2, 1992
    Date of Patent: May 3, 1994
    Assignee: National Semiconductor Corporation
    Inventor: Andreas G. Papaliolios
  • Patent number: 5307142
    Abstract: An asymmetric response latch providing immunity to single event upset without loss of speed. The latch has cross-coupled inverters having a hardened logic state and a soft state, wherein the logic state of the first inverter can only be changed when the voltage on the coupling node of that inverter is low and the logic state of the second inverter can only be changed when the coupling of that inverter is high. One of more of the asymmetric response latches may be configured into a memory cell having complete immunity, which protects information rather than logic states.
    Type: Grant
    Filed: November 15, 1991
    Date of Patent: April 26, 1994
    Assignee: The United States of America as represented by the United States Department of Energy
    Inventors: Wayne T. Corbett, Harry T. Weaver
  • Patent number: 5305451
    Abstract: A circuit to provide single phase clock signals having controlled clock skew to multiple integrated circuit chips is described. A source of single phase clock signals is supplied to a clock signal distribution tree of each integrated circuit. Phase comparison of signals produced by each clock distribution circuit tree provides a control signal for controlling the delay of a clock signal applied to a respective clock distribution tree. A gating circuit is disclosed which produces, in response to each clock signal produced by the clock distribution trees, an accurately controlled LOAD ENABLE and OUTPUT ENABLE signal.
    Type: Grant
    Filed: September 5, 1990
    Date of Patent: April 19, 1994
    Assignee: International Business Machines Corporation
    Inventors: Hu H. Chao, Jung H. Chang, Feng-Hsien W. Shih
  • Patent number: 5305270
    Abstract: A circuit and method for charging the plate electrodes of a plurality of memory cells. The plate electrodes are initially charged by a voltage generator having a large current driving capacity. After the plate electrodes have reached a predetermined threshold voltage, the large-capacity generator is disconnected or deactivated, and the cells are driven by a second, small capacity generator during a standby period. Switches are responsive to a control signal for selectively enabling and disabling the first and second voltage generators. The control unit initially sets the control signal in accordance with the plate electrode voltage level and a clock signal.
    Type: Grant
    Filed: October 13, 1992
    Date of Patent: April 19, 1994
    Assignee: Goldstar Electron Co., Ltd.
    Inventor: Toe H. Kim
  • Patent number: 5305268
    Abstract: A static random-access memory is disclosed which utilizes bit line pairs for each column of memory cells for communication of data between external data terminals and the memory cells. A precharge transistor is connected between each bit line and a precharge voltage, for example V.sub.cc, and an equilibration transistor is connected between the bit lines in each bit line pair. The precharge and equilibration transistors are controlled according to selection of the column, so that all columns which are not selected by the column address are precharged and equilibrated, including the unselected columns in the same sub-array as the selected columns.
    Type: Grant
    Filed: December 13, 1990
    Date of Patent: April 19, 1994
    Assignee: SGS-Thomson Microelectronics, Inc.
    Inventor: David C. McClure
  • Patent number: 5303184
    Abstract: A non-volatile semiconductor memory is provided having a memory cell formed in a semiconductor substrate and arranged in rows and columns to form an X-character shape array. Each cell includes a control electrode and a first region and a second region having a conductivity-type different from that of the substrate. Alternate first and second column lines are provided wherein the first region and the second region of each cell in each column are coupled to the first column line and the second column line, respectively. The first column lines selectively function as ground lines for inputting data during a data writing mode. The first column lines function as bit lines, and the second column lines function as ground lines for outputting data during a data reading mode.
    Type: Grant
    Filed: November 27, 1991
    Date of Patent: April 12, 1994
    Assignee: Sony Corporation
    Inventor: Masanori Noda
  • Patent number: 5301178
    Abstract: A drive unit for use in an optical memory unit has a front panel, a drive mechanism, and sealing members. The front panel has an air vent and a slot for allowing passage of a cassette case containing a disk-shaped recording medium. The drive mechanism loads the cassette case through the slot and drive the recording medium in a specified direction in order to record and reproduce information on and from the recording medium. The sealing members seals the drive mechanism nearly completely, in order to prevent migration of the outside air into the drive mechanism as the air is introduced via the air vent.
    Type: Grant
    Filed: February 19, 1991
    Date of Patent: April 5, 1994
    Assignee: Olypus Optical Co., Ltd.
    Inventors: Satoshi Okabe, Sunao Aoki
  • Patent number: 5297084
    Abstract: A plurality of reference memory cell units are arranged to be connected to rows of matrix-patterned information memory cell units. Each of the reference memory cell units comprises a selection cell of an NMOS transistor, and three reference memory cells of depletion type NMOS transistors, and each of the information memory cell units comprises a selection cell of an NMOS transistor, and three information memory cells of NMOS transistors, one of which is of a depletion type. The selection cells are connected between the reference and information memory cells by a common selection line. The reference and information memory cells are connected by common word lines. Current mirror type sense amplifiers are connected to the columns of information memory cell units by digit lines. This arrangement avoids the occurrence of the unevenness of characteristics resulting from the fabrication process.
    Type: Grant
    Filed: November 26, 1991
    Date of Patent: March 22, 1994
    Assignee: NEC Corporation
    Inventor: Akira Ban
  • Patent number: 5295103
    Abstract: A read/write circuit for use in a dynamic RAM includes transistors connected in series between a pair of bit lines. A gate of the second transistor is connected to one bit line, a gate of the third transistor is connected to another bit line. A write control signal is provided to the gate of each of the first and fourth transistors. During a writing cycle, the gate control signal opens the gate circuit, and then the write control signal enables the first and fourth transistors to enable access from the data buses to the pair of bit lines, and during a reading cycle, the write control signal disables the first and fourth transistors to produce an amplified bit line data between the second and third transistors, and then the gate control signal opens the gate circuit to supply the amplified bit line data to the data buses.
    Type: Grant
    Filed: April 20, 1993
    Date of Patent: March 15, 1994
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Hiroyuki Yamauchi
  • Patent number: 5295098
    Abstract: A dynamic random access memory device is equipped with an output data buffer circuit for driving an output data pin, and the output data buffer circuit comprises an output inverter coupled with the data pin, a driving unit responsive to a data bit on a data line pair in the absence of a high-impedance control signal for controlling the output inverter, the driving unit being further operative to cause the output inverter to enter high-impedance state in the presence of the high-impedance control signal, and a switching transistor coupled between the data pin and a constant voltage source and responsive to a preceding signal for coupling the output data pin with the constant voltage source, wherein the high-impedance control signal and the preceding signal are supplied to the output data buffer circuit before reaching the data bit thereto so that power voltage lines are prevented from voltage fluctuation without sacrifice of switching speed.
    Type: Grant
    Filed: April 13, 1992
    Date of Patent: March 15, 1994
    Assignee: NEC Corporation
    Inventor: Takaki Kohno
  • Patent number: 5293287
    Abstract: Methods and apparatus for providing Bernoulli stabilization to flexible media in an information storage system, are shown to include a stabilizer having a body on which a first surface is formed of a contour sufficient to provide Bernoulli stabilization to media passing thereover. The stabilizer is positioned so that the first surface is proximate backside of the media. In one embodiment, the first surface has a number of grooves which channel air passing between the first surface and the backside. In those situations where the flexible media includes two flexible disks, each having an active side and a backside and where the disks are oriented so that the backsides face one another, the body further includes a second surface of a contour sufficient to provide Bernoulli stabilization to media passing thereover. In such situations the stabilizer is positioned between the disks.
    Type: Grant
    Filed: November 2, 1992
    Date of Patent: March 8, 1994
    Assignee: Iomega Corporation
    Inventors: Israel Tzur, David R. Dodds
  • Patent number: 5293293
    Abstract: A disk cartridge includes a main body of the cartridge having an opening or its major surface by which the signal recording surface of an optical disk accommodated in the main body is exposed to outside and an aperture formed on the lateral surface orthogonal to the major surface of the main body for enabling the optical disk to be inserted into and taken out of the cartridge for disk exchange. The disk cartridge also an opening/closing member which is rotatably supported by the main body by pivot pins provided at its one end for engaging in recesses in the aperture in the main body, for opening and closing the aperture and, which is provided at its other end with a resilient arm having a retaining end pawl engageable with a mating retaining section in the main body. By actuation of the opening/closing member, the aperture in the main body is opened or closed to permit exchange of the optical disk.
    Type: Grant
    Filed: March 16, 1992
    Date of Patent: March 8, 1994
    Assignee: Sony Corporation
    Inventors: Hirokimi Iwata, Shuji Haruna
  • Patent number: 5291436
    Abstract: A ferroelectric memory using ferroelectric capacitors, in which a plurality of electrodes are juxtaposed on each of the two sides of one ferroelectric substance, and the electric fields between the electrodes are controlled, so that more than two different amounts of charges are provided by the ferroelectric capacitors formed by the electrodes. Thereby, the quantity of storage per ferroelectric cell is increased without increase of the cell area.
    Type: Grant
    Filed: April 30, 1992
    Date of Patent: March 1, 1994
    Assignee: Rohm Co., Ltd.
    Inventor: Akira Kamisawa
  • Patent number: 5289427
    Abstract: A write priority detector in a multiport memory prioritizes write operations to memory cell by activating one of its enable signals to a memory cell upon receiving multiple address signals at different write ports of the multiport memory, each attempting to access the same memory cell. The other enable signals are de-activated. One prioritization scheme provides first-come first-serve access to the memory cell among completing address signals. Alternately, a fixed priority scheme always gives one enable signal first priority.
    Type: Grant
    Filed: July 20, 1992
    Date of Patent: February 22, 1994
    Assignee: Motorola, Inc.
    Inventors: James W. Nicholes, Douglas D. Smith
  • Patent number: 5289418
    Abstract: The present invention provides a dedicated memory circuit which supports the generation of parity data in connection with the storing of data. This improved memory circuit allows the parity generation to be done remotely from the CPU while consuming less time. The memory array is provided with its data output being connected to combinational logic. Another input to combinational logic is for external data. The data already in the array and the new data are combined to the combinational logic, preferably an exclusive-or arrangement, to produce the parity data which is then returned to the memory array. A latch is provided between the exclusive-or logic and the memory array data lines to allow isolation of the data during the two cycles of the read out of the array and the right back to the array after the exclusive-or.
    Type: Grant
    Filed: February 14, 1992
    Date of Patent: February 22, 1994
    Assignee: Extended Systems, Inc.
    Inventor: Al Youngerth
  • Patent number: 5289415
    Abstract: A memory circuit uses sense amplifiers to amplify a low level differential data signal from the memory cells to full logic levels. A first sense amplifier converts the low level differential data signal to an intermediate differential voltage level at first and second nodes during the read cycle. A second sense amplifier converts the intermediate differential voltage level to the full logic level. The first and second sense amplifiers are powered down after sensing is complete. A circuit drives the intermediate differential data signal to an equilibrium voltage level when the sensing is complete to reduce the power up delay time of the second sense amplifier and thereby increase the operating speed of the memory circuit. A latching circuit is synchronized with the power down of the first sense amplifier to latch the output logic level at the end of the read cycle.
    Type: Grant
    Filed: April 17, 1992
    Date of Patent: February 22, 1994
    Assignee: Motorola, Inc.
    Inventors: David P. DiMarco, James W. Nicholes, Douglas D. Smith
  • Patent number: 5289429
    Abstract: An address decoder comprising a match signal generating circuit responsive to an inputted address signal and an address mask signal to mask any given bits of the inputted address signal, and an address selection signal generating circuit responsive to signals outputted from the match signal generating circuit, for generating a selection signal of a plurality of addresses which have corresponding bit values except for the masked bits. The address decoder can be used as a row address decoder or column address decoder of the semiconductor memory device for selecting a plurality of addresses simultaneously.
    Type: Grant
    Filed: April 13, 1992
    Date of Patent: February 22, 1994
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Nobuo Watanabe
  • Patent number: 5287315
    Abstract: A structure and method for improving the sense margin of nonvolatile memories is disclosed. An improvement to the sense margin of nonvolatile memories is accomplished by improving the margin both for "ones" at low control gate voltage Vcc and for "zeros" at high control gate voltage Vcc. Improvement in sensing at low control gate voltages Vcc is accomplished by skewing the sense amplifier response characteristics by forming the channel length of the reference memory cell to have a longer channel length than the memory cells of the array.
    Type: Grant
    Filed: May 7, 1993
    Date of Patent: February 15, 1994
    Assignee: Texas Instruments Incorporated
    Inventors: John F. Schreck, Debra J. Dolby, David J. McElroy, Eddie H. Breashears, John H. MacPeak
  • Patent number: 5285420
    Abstract: A semiconductor memory device comprises a plurality of memory cells having respective memory circuits for storing data bits each being of either logic "1" or logic "0" level in a rewritable manner, a read-out unit operative to selectively read out the data bits from the memory cells, a write-in unit operative to selectively write data bits into the memory cells, and a resetting unit operative to concurrently write reset data bits of a predetermined logic level into the memory cells, wherein the resetting unit comprises switching transistors respectively coupled to the memory circuits and a source of the predetermined logic level and is responsive to an external reset controlling signal for causing the switching transistors to concurrently turn on, thereby concurrently writing the reset data bits without failure.
    Type: Grant
    Filed: November 26, 1990
    Date of Patent: February 8, 1994
    Assignee: NEC Corporation
    Inventor: Yasuo Shibue