Abstract: A chip implemented in new technology is designed to include expandable levels of new functionality. The chip includes compatibility circuits which connect to a number of pins which are unused in the chip it replaces in an existing computer system. The compatibility circuits connect to those internal parts of the new chip that contain the newly added or altered levels of functionality. The new chip is installed in the existing computer system just as the prior chip. When so installed, the compatibility circuits enable the new chip to operate in the same manner as the replaced chip but at high speed and with improved performance. When the new chip is installed in the system for which it was designed, the compatibility circuits enable the chip to operate with a selectable level of new functionality at the same higher speed and improved performance.

Abstract: A compound word spelling verification technique is described for use with a dictionary which does not include all verifiable compounds. During verification of a text word, an attempt is made to find a pair of words in the dictionary of which the text word consists. A table associated with the dictionary includes compound class information relative to each of the words stored therein. The compound class of each of the pair of words of which the input text word consists are tested for compatibility to determine if each of the pair of words may acceptably be used in a compound word in the physical position in which it is found in the input text word.

Abstract: A vector data processing system includes at least an A-access pipeline (27) and a B-access pipeline (28) between a main storage unit (4) and vector registers (21). Associated with the A-access pipeline (27) are a write port (WA) and a read port (RA) selectively connected to the vector registers (21). Associated with the B-access pipeline (28) are a write port (WB) and a read port (RB) selectively connected to the vector registers (21). An additional read port (IA) is linked between the read port (RB) of the B-access pipeline (28) and the address input side of the A-access pipeline (27). When an indirect address load/store instruction is carried out for the A-access pipeline (27), an indirect address is generated from the vector registers (21) via the read port (RB) of the B-access pipeline (28) and the additional read port (IA).

Abstract: The programmable interface gives a Block Floating Point processor the capability of performing various real-time signal algorithms on collected radar data in an external batch memory. Normally, Block Floating Point processors are not capable of accommodating data having varying exponent scales such as the data received from a batch memory in a radar system. The programmable interface solves the exponential normalization process using two data paths, an instruction processor, a microcode processor, a pre-shift control and an address generator. Data flow instructions are passed from the instruction processor to the microcode processor which executes the particular instruction's timing sequence. The first data path passes data from the batch memory to the array processor and contains a pre-shifter to normalize the batch memory-stored data. The second data path passes the processed data from the processor to the batch memory.

Abstract: A fast path (comprising control and data busses) directly connects between a storage element in a storage hierarchy and a requestor. The fast path (FP) is in parallel with the bus path normally provided through the storage hierarchy between the requestor and the storage element controller. The fast path may bypass intermediate levels in the storage hierarchy. The fast path is used at least for fetch requests from the requestor, since fetch requests have been found to comprise the majority of all storage access requests. System efficiency is significantly increased by using at least one fast path in a system to decrease the peak loads on the normal path. A requestor using the fast path makes each fetch request simultaneously to the fast path and to the normal path in a system controller element (SCE). The request through the fast path gets to the storage element before the same request through the SCE, but may be ignored by the storage element if it is busy.

Abstract: In an n-wide (n nominally equals 4) snapshot priority network apparatus the access of n+1 requestors to a memory unit is prioritized. Two requestors--the lowest priority one of normal system requestors called instruction processors plus a maintenance exerciser type requestor--share a single memory port which is nominally the lowest priority one of n such prioritized ports. Requests from both requestors are both honored upon a single priority snap, the instruction processor request nominally proceeding before the maintenance processor request. Although the n-wide priority network remains generally faster than any (n+1)-wide priority network, the maintenance exerciser type requestor is expediently serviced and cannot be locked out of access to memory by the competing higher priority requests of the instruction processor.

Abstract: A universal interface adaptor circuit (UIAC) for connecting any one of a plurality of either of two general microprocessor types to a peripheral device using the same interface connections to selectively generate and supply either a WRITE ENABLE signal or a READ ENABLE signal to a peripheral device. A first of the two general types of microprocessors is used in multiplexed-bus multiprocessor (MBM) systems and the second of the two general types of microprocessors is used in non-multiplexed-bus microprocessor (NMBM) systems, where the microprocessors used in both the MBM and the NMBM systems each supply three output signals for determining whether the function is a READ or a WRITE function and the time of occurrence of such READ or WRITE function. The UIAC comprises logic array having three input terminals X, Y, and Z for receiving the three output signals from each of the microprocessors employed in either the MBM systems or the NMBM systems.

Abstract: Data processing apparatus is described, comprising an array of data processing elements in rows and columns. Each element has a data register for input/output. Each column of data registers can be interconnected to form a serial shift path containing either (a) the even-numbered registers, (b) the odd-numbered registers or (c) all the registers. This allows data to be shifted out of the array, one row at a time, either from the even rows, the odd rows, or all the rows. Data can be shifted into the array in a similar way. The facility for selecting the even or odd rows is useful for handling interlaced image data.