Abstract: Various examples of an integrated circuit with a sidewall spacer and a technique for forming an integrated circuit with such a spacer are disclosed herein. In some examples, the method includes receiving a workpiece that includes a substrate and a gate stack disposed upon the substrate. A spacer is formed on a side surface of the gate stack that includes a spacer layer with a low-k dielectric material. A source/drain region is formed in the substrate; and a source/drain contact is formed coupled to the source/drain region such that the spacer layer of the spacer is disposed between the source/drain contact and the gate stack.

Abstract: An initial semiconductor structure includes an underlying substrate, a hard mask stack, an organic planarization layer (OPL), a first complementary material, and a patterned photoresist layer patterned into a plurality of photoresist pillars defining a plurality of photoresist trenches. The first material is partially etched inward of the trenches, to provide trench regions, and the photoresist is removed. The trench regions are filled with a second complementary material, preferentially etchable with respect to the first material. A polymer brush is grafted on the second material but not the first material, to form polymer brush regions with intermediate regions not covered by the brush. The first material is anisotropically etched the at the intermediate regions but not the brush regions. The OPL is etched inward of the intermediate regions, to provide a plurality of OPL pillars defining a plurality of OPL trenches inverted with respect to the photoresist pillars.

Abstract: A semiconductor device includes a wiring substrate having: a first wiring layer having pads; and a second wiring layer having wirings and via-lands. The via-lands include: first-row via-lands connected to first-row pads of the pads, respectively; and second-row via-lands connected to the second-row pads of the pads, respectively. In the perspective plan view, the first-row via-lands have: first via-lands arranged such that a center of each of the first via-lands is shifted in a direction away from a first side of the semiconductor chip than a position overlapping with a center of the corresponding first-row pad; and second via-lands arranged such that a center of each of the second via-lands arranged at a position closer to the first side than the first via-land. In the perspective plan view, the first and second via-lands are alternately arranged in a first direction along the first side.

Abstract: The present application provides an encapsulation film comprising an encapsulation layer, a metal layer, and a protective layer. The encapsulation film provides a structure capable of blocking moisture or oxygen introduced into an organic electronic device from the outside, minimizes the appearance change of the film due to excellent handling properties and processability, and prevents physical and chemical damage during encapsulation process.

Abstract: Provided are transition metal compounds having 5-membered carbocyclic or heterocyclic ring in a unique configuration of fused rings per Formula I The compounds show improved phosphorescent emission in red to near IR region and are useful as emitter materials in organic electroluminescence device.

Abstract: Semiconductor device assemblies having stacked semiconductor dies and thermal transfer devices that include vapor chambers are disclosed herein. In one embodiment, a semiconductor device assembly includes a first semiconductor die having a base region, at least one second semiconductor die at the base region, and a thermal transfer device attached to the first and second dies. The thermal transfer device includes an encapsulant at least partially surrounding the second die and a via formed in the encapsulant. The encapsulant at least partially defines a cooling channel that is adjacent to a peripheral region of the first die. The via includes a working fluid and/or a solid thermal conductor that at least partially fills the channel.

Abstract: A method of forming graphene layers is disclosed. A method of improving graphene deposition is also disclosed. Some methods are advantageously performed at lower temperatures. Some methods advantageously provide graphene layers with lower resistance. Some methods advantageously provide graphene layers in a relatively short period of time.

Abstract: A chip package is provided. The chip package includes a substrate structure. The substrate structure includes a redistribution structure, a third insulating layer, and a fourth insulating layer. The first wiring layer has a conductive pad. The conductive pad is exposed from the first insulating layer, and the second wiring layer protrudes from the second insulating layer. The third insulating layer is under the first insulating layer of the redistribution structure and has a through hole corresponding to the conductive pad of the first wiring layer. The conductive pad overlaps the third insulating layer. The fourth insulating layer disposed between the redistribution structure and the third insulating layer. The chip package includes a chip over the redistribution structure and electrically connected to the first wiring layer and the second wiring layer.

Abstract: A first photoresist material is formed. The first photoresist material is exposed through a phase shift mask. The first photoresist material is developed to form a first photoresist layer, wherein the first photoresist layer comprises a plurality of first photoresist patterns and a plurality of first openings between the plurality of first photoresist patterns. A first conductive material is formed in the plurality of first openings. A second photoresist layer is formed over the first conductive material, wherein the second photoresist layer comprises at least one second opening. A second conductive material is formed in the at least one second opening. The first photoresist layer and the second photoresist layer are removed, to form a plurality of first conductive patterns and at least one second conductive pattern. A dielectric layer is formed, wherein the at least one second conductive pattern is disposed in the dielectric layer.

Abstract: A semiconductor package includes: a connection structure having first and second surface opposing each other and including a plurality of insulating layers, a plurality of redistribution layers, and a plurality of connection vias; at least one semiconductor chip on the first surface having connection pads electrically connected to the plurality of redistribution layers; an encapsulant on the first surface encapsulating the at least one semiconductor chip; and UBM layers including UBM pads on the second surface and UBM vias connecting a redistribution layer. At least one connection via adjacent to the first surface has a tapered structure narrowed toward the second surface, and the other connection vias and the UBM vias have a tapered structure narrowed toward the first surface.

Abstract: A display panel includes: a base substrate; a circuit layer on the base substrate; and a display element layer on the circuit layer, wherein the circuit layer includes an active layer on the base substrate and containing boron and fluorine; a control electrode on the active layer; and a control electrode insulation layer between the active layer and the control electrode, wherein the active layer includes: a core layer in which a concentration of the boron is greater than a concentration of the fluorine; and a surface layer on the core layer and in which a concentration of the fluorine is greater than a concentration of the boron.

Abstract: A method is disclosed for determining a conformation of a molecule on at least one degree of freedom to optimize according to at least one molecular objective function, the method comprising generating using at least one corresponding degree of freedom to optimize a connected rigid bodies representation for the molecule by identifying a plurality of groups of atoms, generating a data structure representative of the connected rigid bodies representation generating at least one neighborhood for each generated neighborhood of the at least one generated neighborhoods, generating a corresponding binary optimization problem using the data structure, providing the generated corresponding binary optimization problem to a high-performance binary optimizer, obtaining a solution from the high-performance binary optimizer; and providing at least one corresponding solution.

Abstract: To provide a display device that is suitable for increasing in size, a display device in which display unevenness is suppressed, or a display device that can display an image along a curved surface. The display device includes a first display panel and a second display panel each including a pair of substrates. The first display panel and the second display panel each include a first region which can transmit visible light, a second region which can block visible light, and a third region which can perform display. The third region of the first display panel and the first region of the second display panel overlap each other. The third region of the first display panel and the second region of the second display panel do not overlap each other.

Abstract: A method for manufacturing a semiconductor device includes forming a plurality of fins on a substrate. The plurality of fins each include a first portion having a first width, and a second portion having a second width greater than the first width. The method also includes forming a sacrificial layer on the substrate in a space between a first fin and a second fin of the plurality of fins, wherein the first fin and the second fin correspond to a vertical transistor. In the method, lower portions of the first and second fins are removed, and an epitaxial region is formed under remaining portions of the first and second fins. The sacrificial layer is removed from the space between the first fin and the second fin after forming the epitaxial region.

Abstract: A display panel comprises a first substrate including a display area and a non-display area surrounding the display area, a light emitting diode disposed in the display area on the first substrate, an adhesive layer covering the display area and the non-display area on the first substrate, and a second substrate bonded to the first substrate by the adhesive layer, wherein the second substrate includes a barrier structure portion for defining a plurality of open spaces on one surface of the second substrate that adjoins the adhesive layer.

Abstract: The subject disclosure relates to high mobility complementary metal-oxide-semiconductor (CMOS) devices and techniques for forming the CMOS devices with fins formed directly on the insulator. According to an embodiment, a method for forming such a high mobility CMOS device can comprise forming, via a first epitaxial growth of a first material, first pillars within first trenches formed within a dielectric layer, wherein the dielectric layer is formed on a silicon substrate, and wherein the first pillars comprise first portions with defects and second portions without the defects. The method can further comprise forming second trenches within a first region of the dielectric layer, and further forming second pillars within the second trenches via a second epitaxial growth of one or more second materials using the second portions of the first pillars as seeds for the second epitaxial growth.

Abstract: A light-emitting element having high emission efficiency is provided. The light-emitting element includes a first organic compound, a second organic compound, and a third organic compound. The first organic compound has a function of converting triplet excitation energy into light emission. The second organic compound is preferably a TADF material. The third organic compound is a fluorescent compound. Light emitted from the light-emitting element is obtained from the third organic compound. Triplet excitation energy in a light-emitting layer is transferred to the third organic compound by reverse intersystem crossing caused by the second organic compound or through the first organic compound.

Abstract: The present disclosure provides an array substrate and a method for manufacturing the same, and a display device. The array substrate includes: a base substrate; a photosensitive element located between the base substrate and a light emitting device and configured to sense light emitted from the light emitting device and generate a sensing signal according to the light; a capacitor configured to store the sensing signal; and a sensing transistor located between the base substrate and the photosensitive element and configured to transmit the sensing signal to a sensing line, wherein an orthographic projection of the sensing transistor on the base substrate at least partially overlaps with an orthographic projection of the photosensitive element on the base substrate.

Abstract: Examples herein provide more integrated circuit packages that allow direct bonding of semiconductor chips to the package, smaller line/spacing of traces, and uniform vias with no capture or cover pads. For example, an integrated circuit (IC) package may include a plurality of pads and a plurality of traces on a substrate with at least two of the plurality of traces located between two of the plurality of pads, and a dielectric layer that completely covers the plurality of traces and partially covers the plurality of pads.

Abstract: A foldable electronic device module includes: a glass-containing cover element having a thickness from about (25) ?m to about (200) ?m, an elastic modulus from about (20) to (140) GPa, and first and second primary surfaces; a stack comprising: (a) an interlayer having an elastic modulus from about (0.01) to (10) GPa and a thickness from about 50 to (200) ?m, and (b) a flexible substrate having a thickness from about (100) to (200) ?m; and a first adhesive joining the stack to the cover element, and comprising an elastic modulus from about (0.001) to (10) GPa and a thickness from about (5) to (25) ?m. Further, the module comprises an impact resistance characterized by tensile stresses of less than about (4100) MPa and less than about (8300) MPa at the first and second primary surfaces of the cover element, respectively, upon an impact in a Pen Drop Test.