Abstract: A computer device reads an indicator from a configuration file that identifies a granularity of units of data at which to track validity. The granularity is one of a plurality of granularities ranging from one unit of data to many units of data. The computer device generates a machine-readable file configured to cause a processing device of a memory system to track validity at the identified granularity using a plurality of data validity counters with each data validity counter in the plurality of data validity counters tracking validity of a group of units of data at the identified granularity. The computer device transfers the machine-readable file to a memory of the memory system.

Abstract: Techniques are disclosed relating to managing storage array invalidations. A computer system may comprise a processor core configured to operate in an idle state and operate in a run state in which the processor core executes instructions. The computer system may further comprise a power management circuit that is configured to receive, while the processor core is in the idle state, a set of invalidation requests directed to the processor core to invalidate a set of entries of a storage array of the processor core. The power management circuit may store invalidation information indicative of the set of invalidation requests. The power management circuit may determine that the processor core has received a request to transition to the run state. Prior to the processor core operating in the run state, the power management circuit may invalidate the set of entries of the storage array based on the invalidation information.

Abstract: A method for execution by a dispersed storage network (DSN) managing unit includes receiving access information from a plurality of distributed storage and task (DST) processing units via a network. Cache memory utilization data is generated based on the access information. Configuration instructions are generated for transmission via the network to the plurality of DST processing units based on the cache memory utilization data.

Abstract: A storage controller including: a host interface circuit receiving first, second, third and fourth requests corresponding to first, second, third and fourth logical addresses; a memory interface circuit communicating with first nonvolatile memories through a first channel and second nonvolatile memories through a second channel; a first flash translation layer configured to manage the first nonvolatile memories; and a second flash translation layer configured to manage the second nonvolatile memories, the first flash translation layer outputs commands corresponding to the first and fourth requests through the first channel, and the second flash translation layer outputs commands respectively corresponding to the second and third requests through the second channel, and a value of the first logical address is smaller than a value of the second logical address, and a value of the third logical address is smaller than a value of the fourth logical address.

Abstract: An apparatus and method are provided for controlling memory accesses. The apparatus has memory access circuitry for performing a tag-guarded memory access operation in response to a target address, the tag-guarded memory access operation by default comprising: comparing an address tag associated with the target address with a guard tag stored in a memory system in association with a block of one or more memory locations comprising an addressed location identified by the target address; and generating an indication of whether a match is detected between the guard tag and the address tag. Further, the apparatus has control tag storage for storing, for each of a plurality of memory regions, configuration control information used to control how the tag-guarded memory access operation is performed by the memory access circuitry when the target address is within that memory region. Each memory region corresponds to multiple of the blocks.

Abstract: Aspects of the present disclosure relate to techniques for minimizing the effects of RowHammer and induced charge leakage. In examples, systems and methods for preventing access pattern attacks in random-access memory (RAM) are provided. In aspects, a data request associated with a page table may be determined to be a potential security risk and such potential security risk may be mitigated by randomly selecting a memory region from a subset of memory regions, copying data stored in a memory region associated with a page table entry in the page table to the second memory region, disassociating the second memory region from the subset of memory regions and associating the memory region associated with the page table to the second memory region, and updating the page table entry in the page table to refer to the second memory region.

Abstract: Examples of systems and method described herein provide for accessing memory devices and, concurrently, generating access codes using an authenticated stream cipher at a memory controller. For example, a memory controller may use a memory access request to, concurrently, perform translation logic and/or error correction on data associated with the memory access request; while also utilizing the memory address as an initialization vector for an authenticated stream cipher to generate an access code. The error correction may be performed subsequent to address translation for a write operation (or prior to address translation for a read operation) to improve processing speed of memory access requests at a memory controller; while the memory controller also generates the encrypted access code.

Abstract: In a general aspect, a hybrid memory system with cache management is disclosed. In some aspects, a memory module includes volatile memory, non-volatile memory, and an internal cache. The internal cache is communicably coupled with the volatile memory and the non-volatile memory. Whether to execute a memory access request is determined by operation of the memory module. In response to the inability of the memory access request to be executed, a data transferring process is performed to copy data between the volatile memory and the non-volatile memory via the internal cache.

Abstract: Techniques involve determining a first slice distribution used to build first storage units in a first pool; in response to a determination that the first pool is expanded to a second pool, determining, at least based on a sum of the slices having been used to build the first storage units, a second slice distribution of updated slices used to build the first storage units in the second pool; determining, based on the first distribution and the second distribution, a first available number of slices and a second available number of slices available for building second storage units in the second pool, the second storage units being different from the first storage units; and determining, at least based on the first available number and the second available number, the number of the second storage units allowed to be built. Accordingly, available capacity allowed for building can be accurately estimated.

Abstract: A storage system determines whether its memory is fragmented (e.g., based on a host read pattern that indicates that a sequential file is being read, but the number of data sense operations required to perform this read indicates that file is stored non-sequentially in the memory). If the storage system determines that its memory is fragmented, the storage system can perform a defragmentation operation on the memory. This defragmentation operation can be done invisibly to the host (i.e., without receiving any hint or instruction from the host to perform the defragmentation operation).

Abstract: A storage system comprises stripes, extents comprised in one stripe among the stripes residing on storage devices in the storage system, respectively. A failed stripe is determined among the stripes, the failed stripe comprising a group of failed extents residing on a group of failed storage devices, respectively, a number of failed storage devices in the group being less than or equal to parity width of the storage system. Distribution of the group of failed extents in the failed stripe is obtained. A rebuild parameter for rebuilding data in the failed stripe is generated based on the obtained distribution. The generated rebuild parameter is stored for rebuilding the storage system. Accordingly, a rebuild parameter generated for one failed stripe is reused for other failed stripe with the same distribution. The performance of rebuild operations may be improved, and time of rebuild operations may be reduced.

Abstract: In one or more embodiments, one or more systems, one or more methods, and/or one or more processes may: determine that a power loss to an information handling system (IHS) has occurred; utilize one or more batteries to power the IHS; enable a predicable latency mode of a non-volatile memory medium of the IHS to enter a deterministic window; transfer data from a volatile memory medium of the IHS to a data repository of a namespace of the non-volatile memory medium; determine that power is provided to the IHS; in response to determining that power is provided to the IHS, transfer the data from the data repository to the volatile memory medium; and after transferring the data from the data repository to the volatile memory medium, disable the predicable latency mode of the non-volatile memory medium to exit the deterministic window of the non-volatile memory medium.

Abstract: The subject technology provides for recovering a validity table for a data storage system. A set of logical addresses in a mapping table is partitioned into subsets of logical addresses. Each of the subsets of logical addresses is assigned to respective processor cores in the data storage system. Each of the processor cores is configured to check each logical address of the assigned subset of logical addresses in the mapping table for a valid physical address mapped to the logical address, for each valid physical address mapped to a logical address of the assigned subset of logical addresses, increment a validity count in a local validity table associated with a blockset of the non-volatile memory corresponding to the valid physical address, and update validity counts in a global validity table associated with respective blocksets of the non-volatile memory with the validity counts in the local validity table.

Abstract: The present disclosure includes apparatuses and methods related to scatter/gather in a memory device. An example apparatus comprises a memory device that includes an array of memory cells, sensing circuitry, and a memory controller coupled to one another. The sensing circuitry includes a sense amplifier and a compute component configured to implement logical operations. A channel controller is configured to receive a block of instructions, the block of instructions including individual instructions for at least one of a gather operation and a scatter operation. The channel controller is configured to send individual instructions to the memory device and to control the memory controller such that the at least one of the gather operation and the scatter operation is executed on the memory device based on a corresponding one of the individual instructions.

Abstract: A secondary storage controller determines one or more tracks of one or more volumes in which data loss has occurred in the secondary storage controller. The secondary storage controller suspends a peer to peer remote copy operation between the secondary storage controller and a primary storage controller. Information on the one or more tracks of the one or more volumes in which the data loss has occurred is transmitted to the primary storage controller.

Abstract: A method includes obtaining a plurality of representations corresponding respectively to a plurality of blocks of data stored on a source node. A plurality of data pairs are sent to a destination node, where each data pair includes a logical address associated with a block of data from the plurality of blocks of data and the corresponding representation of the block of data. A determination is made whether the blocks of data associated with the respective logical addresses are duplicates of data stored on the destination node. In accordance with an affirmative determination, a reference to a physical address of the block of data stored on the destination node is stored. In accordance with a negative determination, an indication that the data corresponding to the respective logical address is not a duplicate is stored. The data indicated as not being a duplicate is written to the destination node.

Abstract: Techniques are disclosed relating to caching for address translation. In some embodiments, address translation circuitry is configured to process requests to translate addresses in a first address space to addresses in a second address space. The translation circuitry may include cache circuitry configured to store translation information, arbitration circuitry configured to arbitrate among ready requests for access to entries of the cache, and hazard circuitry. The hazard circuitry may assign a first request to an ready status the arbitration circuitry based on detection of an absence of hazards for a first address of the first request and add a second request to a queue of requests for the arbitration circuitry based on detection of a hazard for a second address of the second request. Independent arbitration for requests without hazards may improve performance in various aspects, relative to traditional techniques.

Abstract: A method and system for storing data in portable storage devices. Specifically, the disclosed method and system provide a solution for the write-hole problem inflicting persistent storage, especially redundant array of independent disks (RAID) configured storage. The write-hole problem may arise from the occurrence of power failure during a write operation of data to RAID configured storage, subsequently resulting in disparities between the data and parity information thereof—the consistency there-between of which is critical to data reconstruction upon disk failure. To rectify these inconsistencies, a full-stripe (or full-block set) write is recommended, which the disclosed method and system implements through the use of, and re-mapping of relationships between, virtual, physical, and in-memory block sets.

Abstract: Example implementations relate to storing manifest portions in a metadata cache. An example includes receiving, by a storage controller, a read request associated with a first data unit. In response to receiving the read request, the storage controller stores a manifest portion in a metadata cache, the stored manifest portion comprising a plurality of records, the plurality of records including a first record associated with the first data unit. The storage controller determines storage information of the first data unit using pointer information included in the first record of the stored manifest portion, and replaces the pointer information in the first record with the determined storage information of the first data unit.

Abstract: A memory controller circuit is disclosed which is coupleable to a first memory circuit, such as DRAM, and includes: a first memory control circuit to read from or write to the first memory circuit; a second memory circuit, such as SRAM; a second memory control circuit adapted to read from the second memory circuit in response to a read request when the requested data is stored in the second memory circuit, and otherwise to transfer the read request to the first memory control circuit; predetermined atomic operations circuitry; and programmable atomic operations circuitry adapted to perform at least one programmable atomic operation. The second memory control circuit also transfers a received programmable atomic operation request to the programmable atomic operations circuitry and sets a hazard bit for a cache line of the second memory circuit.