Abstract: Example embodiments pertain to an organic semiconductor composition, in which low-molecular-weight oligomer compounds are distributed in the spaces of a polymer compound so that the free spaces of the organic semiconductor polymer compound are filled with the low-molecular-weight oligomer compounds upon the formation of an organic semiconductor thin film, thereby increasing ?-? stacking effects, and to an organic semiconductor thin film using the same and an organic electronic device employing the thin film. Using the organic semiconductor composition according to example embodiments, a semiconductor thin film and an organic electronic device having improved electrical properties may be manufactured.

Abstract: An object of the present invention is to provide a resistive nonvolatile memory element having an electric current path which can be realized by a simple and convenient process, and capable of allowing for micro-fabrication. The resistive nonvolatile memory element of the present invention includes first electrode 203, oxide semiconductor layer 204a which is formed on the first electrode 203 and the resistance of which is altered depending on the applied voltage, metal nanoparticles 204b having a diameter of between 2 nm and 10 nm arranged on the oxide semiconductor layer 204a, tunnel barrier layer 204c formed on the oxide semiconductor layer 204a and on the metal nanoparticles 204b, and second electrode 206 formed on the tunnel barrier layer 204c, in which the metal nanoparticles 204b are in contact with the oxide semiconductor layer 204a.

Abstract: This invention relates to MRAM technology and new variations on MRAM array architecture to incorporate certain advantages from both cross-point and 1T-1MTJ architectures. The fast read-time and higher signal-to-noise ratio of the 1T-1MTJ architecture and the higher packing density of the cross-point architecture are both exploited by combining certain characteristics of these layouts. A single access transistor 16 is used to read the multiple MRAM cells in a segment of a column, which can be stacked vertically above one another in a plurality of MRAM array layers arranged in a “Z” axis direction.

Abstract: An optical memory cell having a material layer associated with a pixel capable of emitting and receiving light. The material layer has phosphorescent material formed therein for storing data as light received from and emitted to the pixel.

Abstract: A method and device of nanostructured titania that is crack free. A method in accordance with the present invention comprises depositing a Ti film on a surface, depositing a masking layer on the Ti film, etching said masking layer to expose a limited region of the Ti film, the limited region being of an area less than a threshold area, oxidizing the exposed limited region of the Th.ucsbi film, and annealing the exposed limited region of the Ti film.

Abstract: The degree of integration and the number of rewriting of a semiconductor device having a nonvolatile memory element are improved. A first MONOS nonvolatile-memory-element and a second MONOS nonvolatile-memory-element having a large gate width compared with the first MONOS nonvolatile-memory-element are mounted together on the same substrate, and the first MONOS nonvolatile-memory-element is used for storing program data which is scarcely rewritten, and the second MONOS nonvolatile-memory-element is used for storing processed data which is frequently rewritten.

Abstract: Disclosed herein are a perfluoroalkyleneoxy group-substituted phenylethylsilane compound and a polymer thereof. The perfluoroalkyleneoxy group-substituted phenylethylsilane compound represented by Formula 1 has excellent thermal and chemical stability to be solution-processed in a monomer state, and the polymer prepared by thermally crosslinking the compound has a high resistance to organic solvents. Moreover, since an insulating layer prepared by applying the same shows improved thermal and physical properties, it is possible to manufacture organic thin-film transistors having a high on/off ratio in a simple process such as a photolithography for a large-size substrate: wherein R1, R2, R3, Z1, Z2, Z3, and n are the same as defined in the detailed description of the invention.

Abstract: A process for forming a solder bump on an under bump metal structure in the manufacture of a microelectronic device comprising exposing the under bump metal structure to an electrolytic bath comprising a source of Sn2+ ions, a source of Ag+ ions, a thiourea compound and/or a quaternary ammonium surfactant; and supplying an external source of electrons to the electrolytic bath to deposit a Sn—Ag alloy onto the under bump metal structure.

Abstract: The invention provides a nanowire light emitting device and a manufacturing method thereof. In the light emitting device, first and second conductivity type clad layers are formed and an active layer is interposed therebetween. At least one of the first and second conductivity type clad layers and the active layer is a semiconductor nanowire layer obtained by preparing a layer of a mixture composed of a semiconductor nanowire and an organic binder and removing the organic binder therefrom.

Abstract: A first variable resistor (5) is connected between a first terminal (7) and a third terminal (9) and increases/reduces its resistance value in accordance with the polarity of a pulse voltage applied between the first terminal (7) and the third terminal (9). A second variable resistor (6) is connected between the third terminal (9) and a second terminal (8) and increases/reduces its resistance value in accordance with the polarity of a pulse voltage applied between the third terminal (9) and the second terminal (8). Given pulse voltages are applied between the first terminal (7) and the third terminal (9) and between the third terminal (9) and the second terminal (8) to reversibly change the resistance values of the first and second variable resistors (5, 6), thereby recording one bit or multiple bits of information.

Abstract: A silicon nanowire substrate having a structure in which a silicon nanowire film having a fine line-width is formed on a substrate, a method of manufacturing the same, and a method of manufacturing a thin film transistor using the same. The method of manufacturing the silicon nanowire substrate includes preparing a substrate, forming an insulating film on the substrate, forming a silicon film on the insulating film, patterning the insulating film and the silicon film into a strip shape, reducing the line-width of the insulating film by undercut etching at least one lateral side of the insulating film, and forming a self-aligned silicon nanowire film on an upper surface of the insulating film by melting and crystallizing the silicon film.

Abstract: An access transistor for a resistance variable memory element and methods of forming the same are provided. The access transistor has first and second source/drain regions and a channel region vertically stacked over the substrate. The access transistor is associated with at least one resistance variable memory element.

Abstract: An on-chip heater and methods for fabrication thereof and use thereof provide that the heater is located within an isolation region that in turn is located within a semiconductor substrate. The heater has a thermal output capable or raising the semiconductor substrate to a temperature of at least about 200° C. The heater may be used for thermally annealing trapped charges within dielectric layers within the semiconductor structure.

Abstract: A semiconductor fin memory structure and a method for fabricating the semiconductor fin memory structure include a semiconductor fin-channel within a finFET structure that is contiguous with and thinner than a conductor fin-capacitor node within a fin-capacitor structure that is integrated with the finFET structure. A single semiconductor layer may be appropriately processed to provide the semiconductor fin-channel within the finFET structure that is contiguous with and thinner than the conductor fin-capacitor node within the fin-capacitor structure.

Abstract: The present invention encompasses an organic field-effect transistor comprising an n-type organic semiconductor formed of a fullerene derivative having a fluorinated alkyl group which is expressed by the following chemical formula (wherein at least any one of R1, R2 and R3 is a perfluoro alkyl group or a partially-fluorinated semifluoro alkyl group each having a carbon number of 1 to 20), and a field-effect transistor production method comprising forming an organic semiconductor layer using the fullerene derivative by a solution process, and subjecting the organic semiconductor layer to a heat treatment in an atmosphere containing nitrogen or argon or in vacuum to provide enhanced characteristics to the organic semiconductor layer. The present invention makes it possible to form an organic semiconductor layer by a solution process and provide an organic field-effect transistor excellent in electron mobility and on-off ratio and capable of operating even in an ambient air atmosphere.

Abstract: A colorant molecule is provided that includes at least one switch unit. The switch unit comprises ring-based tautomers, of which there may be more than one per chromophore, and may include donor and/or acceptor moieties.

Abstract: Phase-changeable memory devices include a lower electrode electrically connected to an impurity region of a transistor in a substrate and a programming layer pattern including a first phase-changeable material on the lower electrode. An adiabatic layer pattern including a material having a lower thermal conductivity than the first phase-changeable material is on the programming layer pattern and an upper electrode is on the adiabatic layer pattern.

Abstract: A memory cell array includes a number of memory cells, each of the memory cells including a source and a drain region defined by corresponding bitlines within a semiconductor substrate. Each of the bitlines has a doped semiconductor region as well as a conductive region in direct electrical contact with the doped semiconductor region.

Abstract: A method, apparatus, and system in which an embedded memory fabricated in accordance with a conventional logic process includes one or more electrically-alterable non-volatile memory cells, each having a programming transistor, a read transistor and a control capacitor, which share a common floating gate electrode. The under-diffusion of the source/drain regions of the programming transistor and control capacitor are maximized. In one embodiment, the source/drain regions of the programming transistor are electrically shored by transistor punch-through (or direct contact).

Abstract: The scale of the devices in a diode array storage device, and their cost, are reduced by changing the semiconductor based diodes in the storage array to cold cathode, field emitter based devices. The field emitters and a field emitter array may be fabricated utilizing a topography-based lithographic technique.