Abstract: A nonvolatile semiconductor memory device that realizes a multi-bit cell and a method for manufacturing the same includes manufacturing the nonvolatile semiconductor memory device to be capable of storing multi-bit data, for example, 4-bit data, in a single memory cell and, as a result, the integration degree of a NOR type nonvolatile semiconductor memory device can be improved.

Abstract: A nitride semiconductor light-emitting device includes a substrate and a nitride semiconductor layer including a light-emitting layer stacked on the substrate, wherein a normal line relative to a lateral face of the nitride semiconductor layer is not perpendicular to a normal line relative to a principal plane of the substrate. A method for the production of a nitride semiconductor light-emitting device that includes a substrate and a nitride semiconductor layer including a light-emitting layer stacked on the substrate includes the steps of covering a first surface of the nitride semiconductor layer with a mask provided with a prescribed pattern, removing the nitride semiconductor layer in regions to be divided into component devices till the substrate, subjecting the nitride semiconductor layer to wet-etching treatment and dividing the nitride semiconductor layer into the component devices.

Abstract: A method for fabricating a silicon-oxide-nitride-oxide-silicon (SONOS) flash memory includes preparing a silicon substrate including a silicon oxide-silicon nitride-silicon oxide (ONO) layer, a first polysilicon layer and a first etch stop layer in sequence; etching the first etch stop layer along a direction of bit line; selectively etching the first polysilicon layer with the first etch stop layer as a mask, till the silicon oxide-silicon nitride-silicon oxide (ONO) layer is exposed, the etched first polysilicon layer having an inverse trapezia section along a direction of word line; and filling a dielectic layer between portions of the first polysilicon layer, the dielectric layer having a trapezia section along the direction of word line. After the above steps, it becomes easier to remove the portion of the first polysilicon layer on a sidewall of the dielectric layer by vertical etching.

Abstract: A nonvolatile ferroelectric memory device using a silicon substrate includes an insulating layer formed in an etching region of the silicon substrate, a floating channel layer formed over the bottom word line, an impurity layer formed at both ends of the floating channel layer and including a source region formed over the insulating layer and a drain region formed over the silicon substrate, a ferroelectric layer formed over the floating channel layer, and a word line formed over the ferroelectric layer.

Abstract: According to some embodiments, an article of manufacture comprises a substrate; a molecular layer on the substrate comprising at least one charge storage molecule coupled to the substrate by a molecular linker; a solid barrier dielectric layer directly on the molecular layer; and a conductive layer directly on the solid barrier dielectric layer. In some embodiments, the solid barrier dielectric layer is configured to provide a voltage drop across the molecular layer that is greater than a voltage drop across the solid barrier dielectric layer when a voltage is applied to the conductive layer. In some embodiments, the molecular layer has a thickness greater than that of the solid barrier dielectric layer. The article of manufacture contains no electrolyte between the molecular layer and the conductive layer.

Abstract: Probes are electrically connected to a surface of a tunnel junction film stack comprising a free layer, a tunnel barrier, and a pinned layer. Resistances are determined for a variety of probe spacings and for a number of magnetizations of one of the layers of the stack. The probe spacings are a distance from a length scale, which is related to the Resistance-Area (RA) product of the tunnel junction film stack. Spacings from as small as possible to about 40 times the length scale are used. Beneficially, the smallest spacing between probes used during a resistance measurement is under 100 microns. A measured in-plane MagnetoResistance (MR) curve is determined from the “high” and “low” resistances that occur at the two magnetizations of this layer. The RA product, resistances per square of the free and pinned layers, and perpendicular MR are determined through curve fitting.

Abstract: A magnetic random access memory (MRAM) device includes a reference magnetic region having a resultant magnetic moment vector generally maintained in a desired orientation without the use of exchange coupling thereto. A storage magnetic region has an anisotropy easy axis and a resultant magnetic moment vector oriented in a position parallel or antiparallel to that of the reference magnetic region. A tunnel barrier is disposed between the reference magnetic region and the storage magnetic region, with the reference magnetic region, storage magnetic region and tunnel barrier defining a storage cell configured for a toggle mode write operation. The storage cell has an offset field applied thereto so as to generally maintain the resultant magnetic moment vector of the reference magnetic region in the desired orientation.

Abstract: A flash memory includes substrate, control gates, trenches, source regions, isolation structures, drain regions, a common source line, floating gates, tunneling dielectric layers, and dielectric layer. The control gates and the trenches are in first and second directions on the substrate, respectively. The source regions are in the substrate and trenches on one side of control gates. The isolation structures fill the trenches between the source regions. The drain regions are in the substrate on the other side of control gates between the isolation structures. The common source line is in the second direction inside the substrate and electrically connected to the source regions. Furthermore, the floating gates are between the control gates and the substrate that between the source and drain regions. The tunneling dielectric layers are disposed between the floating gates and the substrate, and the dielectric layer is disposed between the floating and control gates.

Abstract: The present invention discloses a charge trap flash memory cell with multi-doped layers at the active region, a memory array using of the memory cell, and an operating method of the same. The charge trap memory cell structure of the present invention is characterized by forming multi-doped layers at the active region appropriately, and it is a difference from the conventional art. The present invention induces electrons to band-to-band tunnel at the PN junction with the source/drain region by the multi-doped layers, and accelerates the electrons at the reverse bias to generate an avalanche phenomenon. Therefore, the method for operating a memory array of the present invention comprises programming by injecting holes which are generated by the avalanche phenomenon into multi-dielectric layers of each memory cells, and erasing by injecting electrons through an F-N tunneling from channels into the multi-dielectric layers of each memory cells.

Abstract: An organic electronic device includes a pixel. In one embodiment, the organic electronic device is a bottom emission electronic device. The pixel has an aperture ratio of at least 40%. In another embodiment, the pixel has a first side and a second side opposite the first side. From a plan view, the data line and the first power supply line have lengths that extend along the length of the pixel and lie closer to the first side compared to the second side. In still another embodiment, an organic electronic device includes a substrate, a data line, and a power supply line. The pixel includes a select transistor and a driving transistor. Within the first pixel, each of the data line and the first power supply line lies closer to the substrate compared to the select transistor.

Abstract: A memory device and a method of forming the memory device. The memory device comprises a storage transistor at a surface of a substrate comprising a body portion between first and second source/drain regions, wherein the source/drain regions are regions of a first conductivity type. The storage transistor also comprises a gate structure that wraps at least partially around the body portion in at least two spatial planes. A bit line is connected to the first source/drain region and a word line connected to the gate structure. The memory device does not require an additional capacitive storage element.

Abstract: A micro electronic component, preferably in the form of an electronic memory, includes the use of clusters as an electronic memory. Also disclosed as part of the present invention is a method for fabricating a micro electronic component. The present invention contemplates fabrication of an especially compact electronic memory that works especially with single-electron transistors or single-electronic transfers. According to the present invention, clusters with a metallic cluster nucleus are arranged in parallel grooves essentially in lines or rows and are connected individually to first and second connecting electrodes, such that individually the clusters can be electrically modified or polled independently of each other.

Abstract: A semiconductor device includes: first and second conductive layers; a first insulating film; a first plug; a second insulating film; a first opening; and a capacitor constituted by a lower electrode made of a first metal film formed on the wall and bottom of the first opening and electrically connected to the upper end of the first plug, a capacitive dielectric film made of a ferroelectric film formed on the lower electrode, and an upper electrode made of a second metal film formed on the capacitive dielectric film. The second conductive layer and the upper electrode are electrically connected to each other in the first and second insulating films.

Abstract: A magnetic element includes a channel layer, a first magnetic electrode which is in contact with the channel layer, a second magnetic electrode which is in contact with the channel layer and is insulated from the first magnetic electrode, a first intermediate layer which is provided adjacent to the first magnetic electrode and has a first insulating layer, a first magnetic layer which is provided in contact with a surface of the first intermediate layer on an opposite side to a surface contacting the first magnetic electrode to transfer magnetization to the first magnetic electrode, a first electrode which is connected to the first magnetic electrode, and a second electrode which is connected to the second magnetic electrode, at least one of the first electrode and the second electrode outputting a first signal which changes depending on a magnetic arrangement of the first magnetic electrode and the second magnetic electrode.

Abstract: SRAM devices and methods of fabricating the same are disclosed, by which a process margin and a degree of device integration are enhanced by reducing the number of contact holes of an SRAM device unit cell using local interconnections. A disclosed example device includes first and second load elements; first and second drive transistors; a common gate electrode connected in one body to a gate electrode of the first load element and a gate electrode of the first drive transistor to apply a sync signal to the gate electrodes; the common gate electrode overlapping with a junction layer of the second load element and a junction layer region of the second drive transistor; the common gate electrode being electrically connected to an upper line via a plug in one contact hole.

Abstract: A flash memory device with a nanoscale floating gate and a method of manufacturing thereof are disclosed. At least one embodiment of the present invention provides a much simpler and easier method of manufacturing nanocrystals (or nanocrystallines) for the flash memory device than the conventional method. Since the nanocrystals are homogeneously dispersed as a polymer layer without agglomeration, size and density of the nanoparticles may be controlled. Additionally, one embodiment of the present invention provides memory devices with nanoscale floating gates, and related methods of manufacture, of high efficiency and cost effectiveness by employing electrically and chemically more stable nanoscale floating gates compared to conventional ones.

Abstract: A thin film transistor comprises a layer of organic semiconductor material comprising a tetracarboxylic diimide naphthalene-based compound having, attached to each of the imide nitrogen atoms, a substituted or unsubstituted arylalkyl moiety. Such transistors can further comprise spaced apart first and second contact means or electrodes in contact with said material. Further disclosed is a process for fabricating an organic thin-film transistor device, preferably by sublimation deposition onto a substrate, wherein the substrate temperature is no more than 100° C.

Abstract: A ferroelectric memory device includes a field effect transistor formed on a semiconductor substrate, an interlayer insulation film formed on the semiconductor substrate so as to cover the field effect transistor, a conductive plug formed in the interlayer insulation film in contact with the first diffusion region, and a ferroelectric capacitor formed over the interlayer insulation in contact with the conductive plug, wherein the ferroelectric capacitor includes a ferroelectric film and upper and lower electrodes sandwiching the ferroelectric film respectively from above and below, the lower electrode being connected electrically to the conductive plug, a layer containing oxygen being interposed between the conductive plug and the lower electrode, a layer containing nitrogen being interposed between the layer containing oxygen and the lower electrode, a self-aligned layer being interposed between the layer containing nitrogen and the lower electrode.

Abstract: An access transistor for a resistance variable memory element and methods of forming the same are provided. The access transistor has first and second source/drain regions and a channel region vertically stacked over the substrate. The access transistor is associated with at least one resistance variable memory element.

Abstract: A bistable electrical device employing a bistable polymer body made from an electrically insulating polymer material in which doped nanofibers are dispersed. The doped nanofibers are composed of an electrically conductive nanofiber material and electrically conductive nanoparticles. The doped nanofibers impart bistable electrical characteristics to the polymer body, such that the polymer body is reversibly convertible between a low resistance state and a high resistance state by application of an electrical voltage.