Patents Examined by Michael P McFadden
  • Patent number: 12027316
    Abstract: A multilayer ceramic capacitor includes a multilayer body including dielectric layers which are stacked and internal electrode layers which are stacked, and external electrodes, each connected to the internal electrode layers. The external electrodes each include a conductive resin layer and a plated layer on the conductive resin layer. The conductive resin layer includes a resin portion, conductive fillers dispersed in the resin portion, and metal particles dispersed unevenly in a distribution differing from that of the conductive fillers in the conductive resin layer. An abundance ratio of the metal particles to the resin portion is higher on a side of the plated layer of the conductive resin layer than on a side of the conductive resin layer close to the multilayer body.
    Type: Grant
    Filed: August 8, 2023
    Date of Patent: July 2, 2024
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Yoshiyuki Nomura
  • Patent number: 12027317
    Abstract: A dielectric composition includes dielectric particles and first segregations. The dielectric particles each include a perovskite compound represented by ABO3 as a main component. The first segregations each include Ba, Ti, Si, Ni, and O.
    Type: Grant
    Filed: May 19, 2022
    Date of Patent: July 2, 2024
    Assignee: TDK CORPORATION
    Inventors: Toshihiro Iguchi, Hiroaki Murakami, Yuichiro Sueda, Ryota Namiki
  • Patent number: 12027319
    Abstract: A multilayer ceramic capacitor includes a multilayer body, and external electrodes on a portion of a side surface portion including four side surface of the multilayer body, and on a portion of a first main surface of the multilayer body. The first main surface includes first regions covered with the external electrodes and a second region exposed from the external electrodes. The first regions of the first main surface each include recesses therein. The recesses in each of the first regions each include a spherical curved wall surface. The recesses in each of the first regions each have an average inlet size of about 0.3 ?m or more and about 10.5 ?m or less.
    Type: Grant
    Filed: September 13, 2023
    Date of Patent: July 2, 2024
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Ryo Nishimura
  • Patent number: 12020867
    Abstract: An electronic component includes a laminate in which a plurality of dielectric layers and a plurality of internal electrodes are alternately laminated and external electrodes electrically connected to the internal electrodes. A side margin portion as a region in which the plurality of internal electrodes is not provided when a section of the laminate having the length direction and the width direction is viewed from the laminating direction includes a plurality of side margin layers laminated in the width direction. An outer layer portion as a region in which the plurality of internal electrodes is not provided except for the side margin portion when a section of the laminate including the laminating direction and the width direction is viewed from the length direction includes a plurality of layer-margin layers laminated in the laminating direction.
    Type: Grant
    Filed: February 16, 2023
    Date of Patent: June 25, 2024
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Daiki Fukunaga, Hideaki Tanaka, Masahiro Wakashima, Daisuke Hamada, Hironori Tsutsumi, Satoshi Maeno, Ryota Aso, Koji Moriyama, Akihiro Tsuru
  • Patent number: 12014876
    Abstract: A multilayer capacitor includes a body including a capacitance region in which at least one first internal electrode and at least one second internal electrode are alternately laminated in a first direction with at least one dielectric layer interposed therebetween; and first and second external electrodes spaced apart from each other and disposed on the body to be connected to the at least one first internal electrode and the at least one second internal electrode, respectively, wherein the body further includes a buffer layer disposed in the capacitance region and having a Young's modulus of greater than 0 time and (50/135) times or less of a Young's modulus of the at least one dielectric layer.
    Type: Grant
    Filed: March 10, 2022
    Date of Patent: June 18, 2024
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Won Chul Sim, Soo Hwan Son, Young Ghyu Ahn
  • Patent number: 12002623
    Abstract: A multilayer electronic component according to an exemplary embodiment of the present disclosure may control connectivity of an end of an internal electrode, thereby suppressing occurrence of a short circuit between the internal electrodes, reduced capacitance or lower breakdown voltage.
    Type: Grant
    Filed: May 24, 2022
    Date of Patent: June 4, 2024
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Tae Gyeom Lee, Gi Long Kim, Seon Jae Mun, Byung Rok Ahn, Kyoung Jin Cha
  • Patent number: 12002627
    Abstract: A multilayer electronic component includes: a body including a plurality of dielectric layers and a plurality of internal electrodes alternately disposed with the dielectric layers in a first direction, wherein when a space where the plurality of internal electrodes overlap each other in the first direction is defined as a capacitance forming portion, the plurality of internal electrodes include internal electrodes that are curved at end portions thereof in the capacitance forming portion and internal electrodes that are flat in the capacitance forming portion, and in a cross section of the body in the first and second directions.
    Type: Grant
    Filed: May 20, 2022
    Date of Patent: June 4, 2024
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Tae Gyeom Lee, Gi Long Kim, Seon Jae Mun, Byung Rok Ahn, Kyoung Jin Cha
  • Patent number: 11996242
    Abstract: A multilayer capacitor includes a body including a dielectric layer and a plurality of internal electrodes stacked on each other having the dielectric layer interposed therebetween; and external electrodes including electrode layers positioned externally on the body and connected to the internal electrodes, respectively, wherein the body includes a first surface and a second surface, opposing each other, and to which the plurality of internal electrodes are respectively exposed, and a third surface and a fourth surface which are connected to the first surface and the second surface, and oppose each other in a direction in which the plurality of internal electrodes are stacked on each other, each of the electrode layers including a first region covering the first or second surface and a second region covering the third or fourth surface and having surface roughness lower than that of the first region.
    Type: Grant
    Filed: April 6, 2022
    Date of Patent: May 28, 2024
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Byeong Guk Choi, Dong Yeong Kim, Chung Hyeon Ryu, Seung Been Kim
  • Patent number: 11996244
    Abstract: A multilayer electronic component includes: a body including internal electrodes alternately disposed with dielectric layers in a first direction, wherein when a region in which the internal electrodes overlap each other in the first direction is a capacitance forming portion, the internal electrodes include internal electrodes that are curved at end portions thereof in the capacitance forming portion and internal electrodes that are flat in the capacitance forming portion, and in a cross-section of the body in the first and second directions, (F1+F2)/D1×100 is 35 or less, where F1 is a maximum distance from an uppermost internal electrode to an uppermost flat internal electrode in the first direction, F2 is a maximum distance from a lowermost internal electrode to a lowermost flat internal electrode in the first direction, and D1 is a size of the capacitance forming portion in the first direction at the center thereof in the second direction.
    Type: Grant
    Filed: April 19, 2022
    Date of Patent: May 28, 2024
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Seon Jae Mun, Gi Long Kim, Kyoung Jin Cha, Tae Gyeom Lee, Byung Rok Ahn, Jong Ho Lee
  • Patent number: 11996241
    Abstract: A ceramic electronic component includes an element body, two external electrodes, and an oxide layer. The element body includes a dielectric and internal electrodes. The external electrodes are respectively formed to cover, at least partially, two end faces of the element body. Each external electrode includes a base layer and a plating layer. The base layer has a lower part formed on a bottom face of the element body and an end part formed on a corresponding one of the end faces of the element body. The plating layer is formed on at least the lower part of the corresponding base layer. The oxide layer is formed on a predetermined area of a top face of the element body. The oxide layer has a thinner portion in an area on the top face of the element body that is spaced from the end faces of the element body.
    Type: Grant
    Filed: March 2, 2022
    Date of Patent: May 28, 2024
    Assignee: TAIYO YUDEN CO., LTD.
    Inventor: Shigeto Takei
  • Patent number: 11996246
    Abstract: A multi-layer ceramic electronic component includes a multi-layer ceramic electronic component main body including a multi-layer body including stacked ceramic layers, stacked internal electrode layers, first and second main surfaces, first and second side surfaces, and first and second end surfaces, first and second external electrodes respectively on sides where the first and second end surfaces are located, and first and second metallic terminals respectively connected to the first and second external electrodes. The multi-layer ceramic electronic component main body and at least portion of the first and second metallic terminals are covered with an external material. The second main surface is connected to the metallic terminals. The first and second external electrodes cover a portion of the second main surface. A gap is provided between the multi-layer body and tips of the first and second external electrodes. The external material is in the gap.
    Type: Grant
    Filed: July 10, 2023
    Date of Patent: May 28, 2024
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Satoshi Miyauchi
  • Patent number: 11996243
    Abstract: A ceramic electronic component includes an element body having a first inner electrode exposed at a first end face of the element body, and a second inner electrode exposed at a second end face of the element body. The ceramic electronic component also includes a first outer electrode formed on the first end face and its neighboring faces of the element body. The first outer electrode includes two side portions and a middle portion on each of top and bottom faces of the element body such that the middle portion extends inwardly towards a center of the element body more than the two side portions from the first end face. The ceramic electronic component also includes a second outer electrode having the same dimensions as the first outer electrode on the second end face and its neighboring faces of the element body.
    Type: Grant
    Filed: April 15, 2022
    Date of Patent: May 28, 2024
    Assignee: TAIYO YUDEN CO., LTD.
    Inventors: Yasutomo Suga, Kimio Fujita
  • Patent number: 11990284
    Abstract: A multilayer electronic component according to an exemplary embodiment of the present disclosure may control connectivity of an end of an internal electrode, thereby suppressing occurrence of a short circuit between the internal electrodes, reduced capacitance or lower breakdown voltage. The internal electrode may include a plurality of conductor portions and a plurality of cut-off portions.
    Type: Grant
    Filed: April 27, 2022
    Date of Patent: May 21, 2024
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Jong Ho Lee, Seon Jae Mun, Gi Long Kim, Tae Gyeom Lee, Byung Rok Ahn, Kyoung Jin Cha
  • Patent number: 11990283
    Abstract: A ceramic electronic component includes an element body and at least one external electrode formed on the element body. The element body includes a dielectric and at least one internal electrode therein. The element body has a plurality of surfaces, and these surfaces include a first surface and a second surface opposite the first surface. Each external electrode includes a base layer and a plating layer formed on the base layer. The base layer is in contact with the internal electrode, contains a metal, and has a first end face adjacent to an outer periphery of the second surface of the element body. The plating layer has a second end face adjacent to an outer periphery of the first end face such that the first and second end faces form, in combination, a multilayer structure on the outer periphery of the second surface of the element body.
    Type: Grant
    Filed: December 6, 2021
    Date of Patent: May 21, 2024
    Assignee: TAIYO YUDEN CO., LTD.
    Inventors: Yoshiyuki Motomiya, Masahiko Hirano, Yasutomo Suga
  • Patent number: 11984269
    Abstract: A ceramic electronic component includes a body including a dielectric layer and an internal electrode; and an external electrode disposed on the body, wherein a first carbon material is disposed in the internal electrode. The first carbon material includes carbon black, which has conductivity, a substantially spherical shape, and a particle diameter of 0.05 ?m or less.
    Type: Grant
    Filed: February 11, 2022
    Date of Patent: May 14, 2024
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Won Hee Yoo, Min Seop Kim, Jin Man Jung, Hyo Joong Kim
  • Patent number: 11978593
    Abstract: A film capacitor 1 that includes: a capacitor element including a metallized film with a resin film and a metal layer on a surface of the resin film; an outer case that houses the capacitor element; and a filling resin that fills a space between the capacitor element and the outer case, wherein the outer case includes a resin composition that contains a liquid crystal polymer and an inorganic filler, and an amount of exposure of the inorganic filler from an outer surface of the outer case is 5% to 90%.
    Type: Grant
    Filed: December 17, 2021
    Date of Patent: May 7, 2024
    Assignees: MURATA MANUFACTURING CO., LTD., SHIZUKI ELECTRIC CO., INC.
    Inventors: Satoru Jogan, Kimiaki Kikuchi
  • Patent number: 11977415
    Abstract: A sturdy electronic device is provided. A reliable electronic device is provided. A novel electronic device is provided. An electronic device includes a first board, a second board, a display portion having flexibility, and a power storage device having flexibility. The first board and the second board face each other. The display portion and the power storage device are provided between the first board and the second board. The display portion includes a first surface facing the power storage device. The first surface includes a first region not fixed to the power storage device. The first region overlaps with a display region of the display portion.
    Type: Grant
    Filed: April 12, 2023
    Date of Patent: May 7, 2024
    Assignee: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventor: Masaaki Hiroki
  • Patent number: 11972900
    Abstract: A multilayer ceramic capacitor includes a multilayer body including dielectric layers and internal electrode layers alternately laminated therein, first and second main surfaces opposing each other in a lamination direction, first and second end surfaces opposing each other in a length direction which intersects the lamination direction, and first and second side surfaces opposing each other in a width direction which intersects the lamination direction and the length direction, and external electrodes on the first and second end surfaces, and each electrically connected to the internal electrode layers, wherein the multilayer body includes a slit in at least one of the first side surface, the second side surface, and the second main surface defining and functioning as a board-mounting surface.
    Type: Grant
    Filed: February 10, 2022
    Date of Patent: April 30, 2024
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Yoshiyuki Abe
  • Patent number: 11967639
    Abstract: In accordance with an embodiment, a semiconductor device includes: an n-doped region disposed over an insulating layer; a p-doped region disposed over the insulating layer adjacent to the n-doped region, where an interface between the n-doped region and the p-doped region form a first diode junction; a plurality of segmented p-type anode regions disposed over the insulating layer, each of the plurality of segmented p-type anode regions being surrounded by the n-doped region, where a doping concentration of the plurality of segmented p-type anode regions is greater than a doping concentration of the p-doped region; and a plurality of segmented n-type cathode regions disposed over the insulating layer. Each of the plurality of segmented n-type cathode regions are surrounded by the p-doped region, where a doping concentration of the plurality of segmented n-type cathode regions is greater than a doping concentration of the n-doped region.
    Type: Grant
    Filed: January 26, 2022
    Date of Patent: April 23, 2024
    Assignee: Infineon Technologies AG
    Inventors: Gernot Langguth, Anton Boehm, Christian Cornelius Russ, Mirko Scholz
  • Patent number: 11961667
    Abstract: Provided herein are devices comprising one or more cells, and methods for fabrication thereof. The devices may be electrochemical devices. The devices may include three-dimensional supercapacitors. The devices may be microdevices such as, for example, microsupercapacitors. In some embodiments, the devices are three-dimensional hybrid microsupercapacitors. The devices may be configured for high voltage applications. In some embodiments, the devices are high voltage microsupercapacitors. In certain embodiments, the devices are high voltage asymmetric microsupercapacitors. In some embodiments, the devices are integrated microsupercapacitors for high voltage applications.
    Type: Grant
    Filed: May 27, 2021
    Date of Patent: April 16, 2024
    Assignees: The Regents of the University of California, Nanotech Energy, Inc.
    Inventors: Maher F. El-Kady, Richard B. Kaner, Jack Kavanaugh