Patents Examined by Michael S. Lebentritt
  • Patent number: 8203176
    Abstract: To make it possible to significantly suppress the leakage current in a semiconductor device having a capacitor structure using a dielectric film. There is provided a composite oxide dielectric which is mainly composed of Zr, Al and O, and which has a composition ratio of Zr and Al in a range of (1?x):x where 0.01?x?0.15, and has a crystal structure. When the dielectric is set to have the Al composition in the above described range and is crystallized, the relative dielectric constant of the dielectric can be significantly increased. When the dielectric is used as a dielectric film of a capacitor of a semiconductor device, the leakage current of the capacitor can be significantly reduced.
    Type: Grant
    Filed: February 4, 2008
    Date of Patent: June 19, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Takashi Nakagawa, Toru Tatsumi, Nobuyuki Ikarashi, Makiko Oshida
  • Patent number: 8193521
    Abstract: A phase change memory cell and methods of fabricating the same are presented. The memory cell includes a variable resistance region and a top and bottom electrode. The shapes of the variable resistance region and the top electrode are configured to evenly distribute a current with a generally hemispherical current density distribution around the first electrode.
    Type: Grant
    Filed: May 19, 2010
    Date of Patent: June 5, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Jun Liu, Mike Violette
  • Patent number: 8187968
    Abstract: Presented are methods of fabricating three-dimensional integrated circuits that include post-contact back end of line through-hole via integration for the three-dimensional integrated circuits. Another aspect of the present invention includes three-dimensional integrated circuits fabricated according to methods of the present invention.
    Type: Grant
    Filed: November 5, 2009
    Date of Patent: May 29, 2012
    Assignee: Lam Research Corporation
    Inventors: John Boyd, Fritz Redeker, Yezdi Dordi, Hyungsuk Alexander Yoon, Shijian Li
  • Patent number: 8167573
    Abstract: A gas turbine airfoil (20) having a load-bearing core (30). A honeycomb structure (40A, 42A) is attached to pressure and/or suction sides (22, 24) of the core and is filled with ceramic insulation (50). A ceramic matrix composite boot (60A, 60B, 60C) may cover the leading edge (26) of the core. Edges (61, 62) of the boot may be attached to the core by rows of pins (63A, 63B) or by flanges (65) inserted in slots (69) in the core. The pins may be formed in place by forming pin holes (64) in the boot, clamping the boot onto the core, filling the pin holes with metal or ceramic and metal particles, and heating the particles for internal cohesion and solid-state diffusion bonding (66) with the core. The boot may have a central portion (71) that is not bonded to the core to allow differential thermal expansion.
    Type: Grant
    Filed: September 19, 2008
    Date of Patent: May 1, 2012
    Assignee: Siemens Energy, Inc.
    Inventors: Gary B. Merrill, Douglas A. Keller
  • Patent number: 8101987
    Abstract: A semiconductor device is disclosed. The semiconductor device includes: a first electrode, disposed over a first region of a substrate; and a conductive layer, disposed over the substrate, including a second electrode disposed above the first electrode, wherein the second electrode comprises a mesh main part having a plurality of openings, and a plurality of extending parts, wherein the extending parts are connected to the mesh main part at periphery of the openings and extend toward a surface of the first electrode.
    Type: Grant
    Filed: July 30, 2010
    Date of Patent: January 24, 2012
    Assignee: United Microelectronics Corp.
    Inventor: Hui-Shen Shih
  • Patent number: 8067276
    Abstract: An oxide or nitride semiconductor layer is formed over a substrate. A first conductive layer including a first element and a second element, and a second conductive layer including the second element are formed over the semiconductor layer. The first element is oxidized or nitrogenized near an interface region between the first conductive layer and the oxide or nitride semiconductor layer by heat treatment or laser irradiation. The Gibbs free energy of oxide formation of the first element is lower than those of the second element or any element in the oxide or nitride semiconductor layer.
    Type: Grant
    Filed: December 12, 2008
    Date of Patent: November 29, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Je-Hun Lee, Do-Hyun Kim, Tae-Hyung Ihn
  • Patent number: 8053790
    Abstract: The optical device includes a waveguide and a light sensor on a base. The light sensor includes a light-absorbing medium configured to receive a light signal from the waveguide. The light sensor also includes field sources for generating an electrical field in the light-absorbing medium. The field sources are configured so the electrical field is substantially parallel to the base.
    Type: Grant
    Filed: February 19, 2009
    Date of Patent: November 8, 2011
    Assignee: Kotusa, Inc.
    Inventors: Dazeng Feng, Po Dong, Mehdi Asghari, Ning-Ning Feng
  • Patent number: 8039367
    Abstract: A scribe line structure is disclosed. The scribe line structure includes a semiconductor substrate having a die region, a die seal ring region, disposed outside the die region, a scribe line region disposed outside the die seal ring region and a dicing path formed on the scribe line region. Preferably, the center line of the dicing path is shifted away from the center line of the scribe line region along a first direction.
    Type: Grant
    Filed: May 13, 2009
    Date of Patent: October 18, 2011
    Assignee: United Microelectronics Corp.
    Inventor: Ping-Chang Wu
  • Patent number: 8026606
    Abstract: A structure and a method for forming the same. The structure includes (a) an interlevel dielectric (ILD) layer; (b) a first electrically conductive line and a second electrically conductive line both residing in the ILD layer; (c) a diffusion barrier region residing in the ILD layer. The diffusion barrier region (i) physically isolates, (ii) electrically couples together, and (iii) are in direct physical contact with the first and second electrically conductive lines. The first and second electrically conductive lines each comprises a first electrically conductive material. The diffusion barrier region comprises a second electrically conductive material different from the first electrically conductive material. The diffusion barrier region is adapted to prevent a diffusion of the first electrically conductive material through the diffusion barrier region.
    Type: Grant
    Filed: August 25, 2009
    Date of Patent: September 27, 2011
    Assignee: International Business Machines Corporation
    Inventors: Stephen Ellinwood Luce, Thomas Leddy McDevitt, Anthony Kendall Stamper
  • Patent number: 8026151
    Abstract: A method of performing an STI gapfill process for semiconductor devices is provided. In a specific embodiment of the invention, the method includes forming an stop layer overlying a substrate. In addition, the method includes forming a trench within the substrate, with the trench having sidewalls, a bottom, and a depth. The method additionally includes forming a liner within the trench, the liner lining the sidewalls and bottom of the trench. Furthermore, the method includes filling the trench to a first depth with a first oxide. The first oxide is filled using a spin-on process. The method also includes performing a first densification process on the first oxide within the trench. In addition, the method includes depositing a second oxide within the trench using an HDP process to fill at least the entirety of the trench. The method also includes performing a second densification process on the first and second oxides within the trench.
    Type: Grant
    Filed: November 18, 2008
    Date of Patent: September 27, 2011
    Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventor: Ting Cheong Ang
  • Patent number: 8021974
    Abstract: An improved semiconductor structure consists of interconnects in an upper interconnect level connected to interconnects in a lower interconnect level through use of a conductive protrusion located at the bottom of a via opening in an upper interconnect level, the conductive protrusion extends upward from bottom of the via opening and into the via opening. The improved interconnect structure with the conductive protrusion between the upper and lower interconnects enhances overall interconnect reliability.
    Type: Grant
    Filed: January 9, 2009
    Date of Patent: September 20, 2011
    Assignee: Internatioanl Business Machines Corporation
    Inventors: Chih-Chao Yang, David Vaclav Horak, Takeshi Nogami, Shom Ponoth
  • Patent number: 8022548
    Abstract: A method of forming one or more capacitors on or in a substrate and a capacitor structure resulting therefrom is disclosed. The method includes forming a trench in the substrate, lining the trench with a first copper-barrier layer, and substantially filling the trench with a first copper layer. The first copper layer is substantially chemically isolated from the substrate by the first copper-barrier layer. A second copper-barrier layer is formed over the first copper layer and a first dielectric layer is formed over the second copper-barrier layer. The dielectric layer is substantially chemically isolated from the first copper layer by the second copper-barrier layer. A third copper-barrier layer is formed over the dielectric layer and a second copper layer is formed over the third copper-barrier layer. The second copper layer is formed in a non-damascene process.
    Type: Grant
    Filed: September 29, 2009
    Date of Patent: September 20, 2011
    Assignee: Atmel Corporation
    Inventors: Isaiah O. Oladeji, Alan Cuthbertson
  • Patent number: 8022405
    Abstract: It is an object to provide a light-emitting device including a thin film transistor with high electric characteristics and high reliability, and a method for manufacturing the light-emitting device with high productivity. As for a light-emitting device including an inverted staggered thin film transistor of a channel stop type, the inverted staggered thin film transistor includes a gate electrode, a gate insulating film over the gate electrode, a microcrystalline semiconductor film including a channel formation region over the gate insulating film, a buffer layer over the microcrystalline semiconductor film, a channel protective layer which is provided over the buffer layer so as to overlap with the channel formation region of the microcrystalline semiconductor film, a source region and a drain region over the channel protective layer and the buffer layer, and a source electrode and a drain electrode over the source region and the drain region.
    Type: Grant
    Filed: July 15, 2008
    Date of Patent: September 20, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 8018041
    Abstract: An integrated circuit package system provides a leadframe having a short lead finger and a long lead finger, and the long lead finger and the short lead finger reside substantially within the same horizontal plane. A first die is placed in the leadframe. A second die is offset from the first die. The offset second die is attached over the first die and the long lead finger with an adhesive. The first die is electrically connected to the short lead finger. The second die is electrically connected to at least the long lead finger or the short lead finger. At least portions of the leadframe, the first die, and the second die are encapsulated in an encapsulant.
    Type: Grant
    Filed: April 13, 2010
    Date of Patent: September 13, 2011
    Assignee: Stats Chippac Ltd.
    Inventors: Byung Tai Do, Heap Hoe Kuan
  • Patent number: 8013385
    Abstract: A semiconductor device of the present invention has a first contact and a second contact which are located over a device isolation film so as to be opposed with each other, and have a length in the horizontal direction larger than the height; a first electro-conductive pattern located on the first contact and is formed in at least a single interconnect layer; a second electro-conductive pattern located on the second contact so as to be opposed with the first electro-conductive pattern; and an interconnect formed in an upper interconnect layer which is located above the first electro-conductive pattern and the second electro-conductive pattern, so as to be located in a region above the first electro-conductive pattern and the second electro-conductive pattern.
    Type: Grant
    Filed: December 7, 2009
    Date of Patent: September 6, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Masayuki Furumiya, Yasutaka Nakashiba
  • Patent number: 8012785
    Abstract: An embodiment of a method is provided that includes providing a substrate having a frontside and a backside. A CMOS device is formed on the substrate. A MEMS device is also formed on the substrate. Forming the MEMS device includes forming a MEMS mechanical structure on the frontside of the substrate. The MEMS mechanical structure is then released. A protective layer is formed on the frontside of the substrate. The protective layer is disposed on the released MEMS mechanical structure (e.g., protects the MEMS structure). The backside of the substrate is processed while the protective layer is disposed on the MEMS mechanical structure.
    Type: Grant
    Filed: April 24, 2009
    Date of Patent: September 6, 2011
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kai-Chih Liang, Hua-Shu Wu, Li-Chun Peng, Tsung-Cheng Huang, Mingo Liu, Nick Y. M. Shen, Allen Timothy Chang
  • Patent number: 8012782
    Abstract: In a liquid crystal display device, a first substrate includes electrical wirings and a semiconductor integrated circuit which has TFTs and is connected electrically to the electrical wirings, and a second substrate includes a transparent conductive film on a surface thereof. A surface of the first substrate that the electrical wirings are formed is opposite to the transparent conductive film on the second substrate. the semiconductor integrated circuit has substantially the same length as one side of a display screen (i.e., a matrix circuit) of the display device and is obtained by peeling it from another substrate and then forming it on the first substrate. Also, in a liquid crystal display device, a first substrate includes a matrix circuit and a peripheral driver circuit, and a second substrate is opposite to the first substrate, includes a matrix circuit and a peripheral driver circuit and has at least a size corresponding to the matrix circuit and the peripheral driver circuit.
    Type: Grant
    Filed: July 28, 2010
    Date of Patent: September 6, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Setsuo Nakajima, Yasuyuki Arai
  • Patent number: 8013384
    Abstract: A process for the realization of a high integration density power MOS device includes the following steps of: providing a doped semiconductor substrate with a first type of conductivity; forming, on the substrate, a semiconductor layer with lower conductivity; forming, on the semiconductor layer, a dielectric layer of thickness comprised between 3000 and 13000 A (Angstroms); depositing, on the dielectric layer, a hard mask layer; masking the hard mask layer by means of a masking layer; etching the hard mask layers and the underlying dielectric layer for defining a plurality of hard mask portions to protect said dielectric layer; removing the masking layer; isotropically and laterally etching said dielectric layer forming lateral cavities in said dielectric layer below said hard mask portions; forming a gate oxide of thickness comprised between 150 and 1500 A (Angstroms) depositing a conductor material in said cavities and above the same to form a recess spacer, which is totally aligned with a gate structure c
    Type: Grant
    Filed: September 1, 2009
    Date of Patent: September 6, 2011
    Assignee: STMicroelectronics, S.r.l.
    Inventors: Giuseppe Arena, Giuseppe Ferla, Marco Camalleri
  • Patent number: 8013423
    Abstract: A semiconductor device includes an interlayer insulating layer including a plurality of trenches connecting to a number of via holes formed on a semiconductor substrate including lower interconnections, wherein widths of the trenches are greater than widths of the via holes, and metal interconnections formed by burying metal thin films in the via holes and the trenches. Depths of the trenches are adjusted differently from each other depending on required resistances of the metal interconnections.
    Type: Grant
    Filed: June 25, 2009
    Date of Patent: September 6, 2011
    Assignee: Dongbu HiTek Co., Ltd.
    Inventor: Dong-Yeal Keum
  • Patent number: 8012839
    Abstract: A transistor having an epitaxial channel and a method for fabricating a semiconductor device having an epitaxial channel, the method including forming a hardmask on a substrate and forming an opening in the hardmask. The opening is geometrically characterized by a long dimension and a short dimension, and the opening is arranged in a predetermined manner relative to the channel region of a transistor. An epitaxial material is formed in the opening that induces strain in substrate regions proximate to the epitaxial material. The epitaxial material is confined to the opening, such that an epitaxial channel is formed. A transistor is fabricated in proximity to the epitaxial channel, such that the strain induced in the substrate provides enhanced transistor performance. By confining the epitaxial material to a predefined channel in the substrate, plastic strain relaxation of the epitaxial material is minimized and a maximum amount of strain is induced in the substrate.
    Type: Grant
    Filed: February 29, 2008
    Date of Patent: September 6, 2011
    Assignee: Chartered Semiconductor Manufacturing, Ltd.
    Inventors: Jinping Liu, Alex K H See, Mei Sheng Zhou, Liang Choo Hsia