Abstract: A semiconductor package using a coreless signal distribution structure (CSDS) is disclosed and may include a CSDS comprising at least one dielectric layer, at least one conductive layer, a first surface, and a second surface opposite to the first surface. The semiconductor package may also include a first semiconductor die having a first bond pad on a first die surface, where the first semiconductor die is bonded to the first surface of the CSDS via the first bond pad, and a second semiconductor die having a second bond pad on a second die surface, where the second semiconductor die is bonded to the second surface of the CSDS via the second bond pad. The semiconductor package may further include a metal post electrically coupled to the first surface of the CSDS, and a first encapsulant material encapsulating side surfaces and a surface opposite the first die surface of the first semiconductor die, the metal post, and a portion of the first surface of the CSDS.

Abstract: A dynamic random access memory (DRAM) device includes a substrate, plural buried gates and plural bit lines. The buried gates are disposed in the substrate along a first trench extending along a first direction. The bit lines are disposed over the buried gates and extending along a second direction across the first direction. Each of the bit lines includes a multi-composition barrier layer, wherein the multi-composition barrier layer includes WSixNy with x and y being greater than 0 and the multi-composition barrier layer is silicon-rich at a bottom portion thereof and is nitrogen-rich at a top portion thereof.

Abstract: Disclosed is a semiconductor device including two oxide semiconductor layers, where one of the oxide semiconductor layers has an n-doped region while the other of the oxide semiconductor layers is substantially i-type. The semiconductor device includes the two oxide semiconductor layers sandwiched between a pair of oxide layers which have a common element included in any of the two oxide semiconductor layers. A double-well structure is formed in a region including the two oxide semiconductor layers and the pair of oxide layers, leading to the formation of a channel formation region in the n-doped region. This structure allows the channel formation region to be surrounded by an i-type oxide semiconductor, which contributes to the production of a semiconductor device that is capable of feeding enormous current.

Abstract: A miniaturized transistor, a transistor with low parasitic capacitance, a transistor with high frequency characteristics, or a semiconductor device including the transistor is provided. The semiconductor device includes a first insulator, an oxide semiconductor over the first insulator, a first conductor and a second conductor that are in contact with the oxide semiconductor, a second insulator that is over the first and second conductors and has an opening reaching the oxide semiconductor, a third insulator over the oxide semiconductor and the second insulator, and a fourth conductor over the third insulator. The first conductor includes a first region and a second region. The second conductor includes a third region and a fourth region. The second region faces the third region with the first conductor and the first insulator interposed therebetween. The second region is thinner than the first region. The third region is thinner than the fourth region.

Abstract: Systems and methods are disclosed for processing radio frequency (RF) signals using one or more bipolar transistors disposed on or above a high-resistivity region of a substrate. The substrate may include, for example, bulk silicon, at least a portion of which has high-resistivity characteristics. For example, the bulk substrate may have a resistivity greater than 500 Ohm*cm, such as around 1 kOhm*cm. In certain embodiments, one or more of the bipolar devices are surrounded by a low-resistivity implant configured to reduce effects of harmonic and other interference.

Abstract: Embodiments described herein provide for a sensing device including a sensor die attached to a header. The header has a first working surface composed of a first one or more electrically conductive pads and a bulk of the header. The sensor die has a second working surface and a third surface reverse of the second working surface. The sensor die includes a sensing element on the second working surface, and the third surface of the sensor die is composed of a second one or more electrically conductive pads and a dielectric layer. The first one or more electrically conductive pads of the header contact the second one or more electrically conductive pads of the sensor die, and the bulk of the header at the first working surface of the header contacts the dielectric layer of the third surface of the sensor die.

Abstract: An optoelectronic semiconductor chip is disclosed. In an embodiment the optoelectronic semiconductor chip includes a semiconductor body of semiconductor material, a p-contact layer and an n-contact layer. The semiconductor body includes an active layer intended for generating radiation. The semiconductor body includes a p-side and an n-side, between which the active layer is arranged. The p-contact layer is intended for electrical contacting the p-side. The n-contact layer is intended for electrical contacting the n-side 1b. The n-contact layer contains a TCO layer and a mirror layer, the TCO-layer being arranged between the n-side of the semiconductor body and the mirror layer.

Abstract: A silicon carbide substrate capable of reducing on-resistance and improving yield of semiconductor devices is made of single-crystal silicon carbide, and sulfur atoms are present in one main surface at a ratio of not less than 60×1010 atoms/cm2 and not more than 2000×1010 atoms/cm2, and oxygen atoms are present in the one main surface at a ratio of not less than 3 at % and not more than 30 at %.

Abstract: A package may include a plurality of stacked semiconductor devices (chips) is disclosed. Each chip may include through vias (through silicon vias—TSV) that can provide an electrical connection between chips and between chips and external connections, such as solder connections or solder balls. Electro static discharge (ESD) protection circuitry may be placed on a bottom chip in the stack even when through vias connect circuitry on a top chip in the stack exclusive of the bottom chip. In this way, ESD protection circuitry may be placed in close proximity to the ESD event occurring at an external connection. In particular, every chip in the stack of semiconductor chips may have circuitry electrically connected to the external connection and by placing ESD protection circuitry on the bottom chip closest to the electrical connection, instead of on all chips ESD protection may be more area efficient.

Abstract: An area sensor of the present invention has a function of displaying an image in a sensor portion by using light-emitting elements and a reading function using photoelectric conversion devices. Therefore, an image read in the sensor portion can be displayed thereon without separately providing an electronic display on the area sensor. Furthermore, a photoelectric conversion layer of a photodiode according to the present invention is made of an amorphous silicon film and an N-type semiconductor layer and a P-type semiconductor layer are made of a polycrystalline silicon film. The amorphous silicon film is formed to be thicker than the polycrystalline silicon film. As a result, the photodiode according to the present invention can receive more light.

Abstract: A gas detection apparatus according to an embodiment includes: a collection unit collecting a detection target gas containing a gas molecule to be detected; a detector including a plurality of detection cells each including a sensor unit and an organic probe disposed at the sensor unit, the organic probe capturing the gas molecule collected by the collection unit; a discriminator discriminating the gas molecule by a signal pattern based on an intensity difference of detection signals generated with the gas molecule being captured by the organic probes of the plurality of detection cells; and a reactivation unit applying heat to the organic probe which has the captured gas molecule to be desorbed the gas molecule from the organic probe.

Abstract: A solid-state imaging device is provided. The solid-state imaging device includes a semiconductor substrate containing a plurality of photoelectric conversion elements. A color filter layer includes a first color filter component and a second color filter component separated from each other and disposed above the semiconductor substrate. A microlens structure includes a first microlens element and a second microlens element separated from each other and disposed on the first and second color filter components respectively. The solid-state imaging device also includes a gap filled with air. The gap is disposed between the first and second color filter components and also between the first and second microlens elements.

Abstract: A display panel including a first substrate, a second substrate and a display medium is provided. The first substrate includes a base substrate, a gate, an active layer, a source, a drain, and a shielding structure. The gate is disposed on the base substrate. The active layer is electrically insulated from and disposed correspondingly to the gate. The source and the drain are electrically connected to the active layer. The shielding structure is disposed on the active layer and covers at least part of the active layer. The shielding structure includes a metal layer and an anti-reflection structure. The display medium is disposed between the first substrate and the second substrate.

Abstract: A gate electrode of a field effect transistor is formed. Next, an offset spacer film with a double-layer structure including a silicon oxide film as a lower-layer film and a silicon nitride film as an upper-layer film is formed on a sidewall surface of the gate electrode. The silicon nitride film serves as a supply source of an element for terminating dangling bonds of silicon in a device formation region. Next, treatment for leaving the offset spacer film intact or treatment for removing the silicon nitride film of the offset spacer film is performed. Thereafter, a sidewall insulating film is formed on the sidewall surface of the gate electrode.

Abstract: In some embodiments, a method and/or a system may include an integrated circuit. The integrated circuit may include a semiconductor die. The integrated circuit may include a plurality of wiring layers. At least one metal-insulator-metal (MIM) capacitor may be formed within the plurality of wiring layers. The integrated circuit may include a circuit. The circuit may include at least an inductor and a voltage regulator which, with the MIM capacitor, forms a voltage regulator for the semiconductor die. The circuit may be coupled substantially below at least a portion of the MIM capacitor in the plurality of layers. The circuit may be electrically coupled to the capacitor through the plurality of wiring layers. The integrated circuit may include a plurality of electrical connectors, the plurality of electrical connectors coupled to the second surface at points separate from an area of the second surface that is occupied by the circuit.

Abstract: A semiconductor memory device includes a first portion including a semiconductor element, a second portion surrounding the semiconductor element. The second portion includes a stack of conductive layers and insulating layers, and at least one groove through the conductive layers and the insulating layers.

Abstract: Tapered source and drain contacts for use in an epitaxial FinFET prevent short circuits and damage to parts of the FinFET during contact processing, thus improving device reliability. The inventive contacts feature tapered sidewalls and a pedestal where electrical contact is made to fins in the source and drain regions. The pedestal also provides greater contact area to the fins, which are augmented by extensions. Raised isolation regions define a valley around the fins. During source/drain contact formation, the valley is lined with a conformal barrier that also covers the fins themselves. The barrier protects underlying local oxide and adjacent isolation regions against gouging while forming the contact. The valley is filled with an amorphous silicon layer that protects the epitaxial fin material from damage during contact formation. A simple tapered structure is used for the gate contact.

Abstract: A field effect transistor comprising a source including a plurality of electrode projections with spaces in between. A drain includes a plurality of electrode projections each located in one of the spaces between the electrode projections of the source thereby forming a drain-source electrode connection area of alternating drain and source projections. A gate is spaced apart from the drain-source electrode area thereby forming a channel between the gate and the drain-source electrode connection area wherein the gate runs parallel to the channel. A plurality of nano-structures is located in the drain-source electrode area thereby to form an electrical connection between the electrode projections of the drain and source in the drain-source electrode connection area. The invention extends to a gas detector including a plurality of field effect transistors as described above located on a substrate.

Abstract: A curable composition according to the present invention for sealing optical semiconductor includes components (A), (B), and (C). Another curable composition according to the present invention for sealing optical semiconductor further includes a component (D) in addition to the components (A), (B) and (C). The component (A) is a compound containing at least one functional group selected from the group consisting of epoxy groups, oxetanyl groups, vinyl ether groups, and (meth)acryloyl groups. The component (B) is a cycloaliphatic epoxy compound. The component (C) is a curing catalyst including a cationic component and an anionic component and generating an acid upon application of light or heat, where the cationic component contains an aromatic ring, and the anionic component contains a central element selected from boron and phosphorus. The component (D) is conductive fiber-bearing particles each including a particulate substance and a fibrous conductive substance lying on or over the particulate substance.

Abstract: A semiconductor structure includes an isolation feature formed in the semiconductor substrate and a first fin-type active region. The first fin-type active region extends in a first direction. A dummy gate stack is disposed on an end region of the first fin-type active region. The dummy gate stack may overlie an isolation structure. In an embodiment, any recess such as formed for a source/drain region in the first fin-type active region will be displaced from the isolation region by the distance the dummy gate stack overlaps the first fin-type active region.