Patents Examined by Michael Sun
  • Patent number: 10831479
    Abstract: A single architected instruction to move data is executed. The executing includes moving data of a specified length from a source location to a destination location in a right-to-left sequence to provide a predictable result. A predictable result is provided, even though a portion of the destination location is contained within the source location from which the data is being moved.
    Type: Grant
    Filed: February 20, 2019
    Date of Patent: November 10, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Timothy Slegel, John R. Ehrman, Dan Greiner, Anthony Saporito, Aaron Tsai
  • Patent number: 10824428
    Abstract: Systems, methods, and apparatuses relating to performing hashing operations on packed data elements are described.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: November 3, 2020
    Assignee: Intel Corporation
    Inventors: Regev Shemy, Zeev Sperber, Wajdi Feghali, Vinodh Gopal, Amit Gradstein, Simon Rubanovich, Sean Gulley, Ilya Albrekht, Jacob Doweck, Jose Yallouz, Ittai Anati
  • Patent number: 10826720
    Abstract: A switching device is a switching device mounted on a vehicle and includes a plurality of communication ports connectable to cables for Ethernet communication, a circuit operated by using power supplied via each of the communication ports, an acquisition unit that acquires a measurement result for noise of the power supplied via each of the communication ports, and a determination unit that performs determination processing for determining whether or not power to be supplied via a corresponding one of the communication ports is to be output to the circuit based on the measurement result for noise acquired by the acquisition unit.
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: November 3, 2020
    Assignees: Sumitomo Electric Industries, Ltd., AutoNetworks Technologies, Ltd., Sumitomo Wiring Systems, Ltd.
    Inventors: Akihito Iwata, Hirofumi Urayama, Akihiro Ogawa, Takeshi Hagihara, Yasuhiro Yabuuchi
  • Patent number: 10789198
    Abstract: Methods and apparatus for data transmissions over an inter-processor communication (IPC) link between two (or more) independently operable processors. In one embodiment, the IPC link is configured to enable an independently operable processor to transact data to another independently operable processor, while obviating transactions (such as via direct memory access) by encapsulating a payload within a data structure. For example, a host processor may insert the payload into a transfer descriptor (TD), and transmit the TD to a peripheral processor. The host processor may also include a head index and/or a tail index within a doorbell message sent to the peripheral processor, obviating another access of memory. The peripheral processor may perform similar types of transactions via a completion descriptor (CD) sent to the host processor. In some variants, the peripheral may be a Bluetooth-enabled device optimized for low-latency, low-power, and/or low-throughput transactions.
    Type: Grant
    Filed: June 24, 2019
    Date of Patent: September 29, 2020
    Assignee: Apple Inc.
    Inventors: Vladislav Petkov, Saurabh Garg, Karan Sanghi, Haining Zhang
  • Patent number: 10789196
    Abstract: Efficient communication between storage controllers can be performed. A storage system includes one or more backend switches that connect a first processor, a second processor, and one or more storage devices to each other. Each backend switch identifies a destination of a frame by referring to the frame received from the first processor. In a case where the destination of the frame is the second processor, each backend switch translates a first address, included in the frame, for specifying a location on the second memory in an address space of the first processor, into a second address for specifying the location on the second memory in an address space of the second processor, and transfers the frame including the second address to the second storage controller.
    Type: Grant
    Filed: July 29, 2019
    Date of Patent: September 29, 2020
    Assignee: Hitachi, Ltd.
    Inventors: Katsuya Tanaka, Kentaro Shimada, Akira Yamamoto, Sadahiro Sugimoto
  • Patent number: 10789181
    Abstract: In some embodiments a transceiver is configured to wirelessly transfer data between a host computing device and one or more peripheral devices over a communication path using a communication data construct comprising a packet structure arranged in a repetitive communication structure. The repetitive communication structure can include a transmit time window within which the host transmits data to the one or more connected peripheral devices and a receive time window within which the host receives data from the one or more connected peripheral devices. A duration of the receive time window is set based on a predetermined communication report rate between the host computing device and the one or more connected peripheral devices. A new peripheral device is added as a connected peripheral device when the new peripheral device transmits a request to the host to be added as a connected peripheral device and the receive time window has time available to add the new peripheral device.
    Type: Grant
    Filed: May 22, 2019
    Date of Patent: September 29, 2020
    Assignee: Logitech Europe S.A.
    Inventors: Philippe Chazot, Jiri Holzbecher, Frédéric Fortin, Fabrice Sauterel
  • Patent number: 10783099
    Abstract: The present disclosure relates to a framework application for device access software. The framework application can be installed on a host. At least one driver can be integrated into the framework application, said driver being designed for access to an associated field bus component of a field bus network. For each integrated driver, the framework application has a standard interface, via which data can be exchanged between the driver and the framework application. For at least some of the integrated drivers, the framework application has one or more proprietary interfaces in addition to the standard interface, via which proprietary interfaces data can be exchanged between the respective drivers and the framework application. Information regarding additional functionalities that are supported by the driver or by an associated field bus component can be transferred from the driver to the framework application via at least one of the proprietary interfaces.
    Type: Grant
    Filed: October 10, 2017
    Date of Patent: September 22, 2020
    Assignee: Endress+Hause Process Solutions AG
    Inventors: Ingomar Sotriffer, Michael Mayer, Jan Pflug
  • Patent number: 10782931
    Abstract: A control system includes a data access circuit and a control circuit. The system coordinates an asynchronous FIFO process between a write circuit operating according to a first clock and a read circuit operating according to a second clock. The data access circuit controls the write circuit to write data into a memory buffer and controls the read circuit to read the data from the memory buffer. The control circuit generates a write index according to the first clock and a read index according to the second clock. The control circuit calculates multiple water levels according to the write index and the read index and obtains a median water level. The control circuit controls the access circuit to execute the asynchronous FIFO process at a time point corresponding to the median water level, so that a data exchange is performed via the memory buffer.
    Type: Grant
    Filed: May 23, 2019
    Date of Patent: September 22, 2020
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventor: Lien-Hsiang Sung
  • Patent number: 10782977
    Abstract: Fault tolerant and fault detecting multi-threaded processors are described. Instructions from a program are executed by both a master thread and a slave thread and execution of the master thread is prioritized. If the master thread stalls or reaches a memory write after having executed a sequence of instructions, the slave thread executes a corresponding sequence of instructions, where at least the first and last instructions in the sequence are the same as the sequence executed by the master thread. When the slave thread reaches the point at which execution of the master thread stopped, the contents of register banks for both the threads are compared, and if they are the same, execution by the master thread is allowed to continue, and any buffered speculative writes are committed to the memory system.
    Type: Grant
    Filed: August 10, 2018
    Date of Patent: September 22, 2020
    Assignee: MIPS Tech, LLC
    Inventors: Timothy Charles Mace, Ryan C Kinter
  • Patent number: 10776527
    Abstract: A security device includes an interface and a processor. The interface is configured for connecting to a bus that serves one or more peripheral devices, at least one of the peripheral devices being a memory device. The processor is connected to the bus in addition to the peripheral devices, and is configured to hold a definition that distinguishes between authorized and unauthorized transactions with the memory device, to identify on the bus a transaction in which a bus-master device attempts to access the memory device, and to initiate a responsive action in response to identifying that the transaction is unauthorized in accordance with the definition.
    Type: Grant
    Filed: September 12, 2019
    Date of Patent: September 15, 2020
    Assignee: NUVOTON TECHNOLOGY CORPORATION
    Inventors: Ziv Hershman, Yoel Hayon, Natan Keren, Moshe Alon
  • Patent number: 10761771
    Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller. The controller acquires, from a host, write data having the same first size as a data write unit of the nonvolatile memory and obtained by dividing write data associated with one write command having a first identifier indicating a first write destination block in a plurality of write destination blocks into a plurality of write data or combining write data associated with two or more write commands having the first identifier. The controller writes the acquired write data having the first size to the first write destination block by a first write operation.
    Type: Grant
    Filed: March 13, 2019
    Date of Patent: September 1, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Shinichi Kanno, Hideki Yoshida, Naoki Esaka, Hiroshi Nishimura
  • Patent number: 10761885
    Abstract: An apparatus and method are provided for executing thread groups. The apparatus comprises scheduling circuitry for selecting for execution a first thread group from a plurality of thread groups, and thread processing circuitry that is responsive to the scheduling circuitry to execute active threads of the first thread group in dependence on a common program counter shared between the active threads. In response to an exit event occurring for the first thread group, the thread processing circuitry determines whether a program counter check condition is present, and this can be used to trigger program counter checking circuitry to perform a program counter check operation to update the common program counter and an active thread indication for the first thread group.
    Type: Grant
    Filed: July 25, 2018
    Date of Patent: September 1, 2020
    Assignee: ARM Limited
    Inventors: Isidoros Sideris, Eugenia Cordero-Crespo, Amir Kleen
  • Patent number: 10754658
    Abstract: An apparatus includes an arithmetic circuit that performs a pipeline operation on first data as an input; and a determination circuit that determines, based on pipeline operation results, whether to perform the pipeline operation by inputting, to the arithmetic circuit, second data different from the first data, wherein when the determination circuit has determined that the pipeline operation is to be performed by inputting the second data to the arithmetic circuit, the arithmetic circuit suspends the pipeline operation using the second data thereof, and performs the pipeline operation with the first data input until the second data is input, and when the second data is input, the arithmetic circuit resumes the pipeline operation using the second data.
    Type: Grant
    Filed: July 27, 2018
    Date of Patent: August 25, 2020
    Assignee: FUJITSU LIMITED
    Inventor: Yutaka Tamiya
  • Patent number: 10747536
    Abstract: A data processing system provides a loop-end instruction for use at the end of a program loop body specifying an address of a beginning instruction of said program loop body. Loop control circuitry (1000) serves to control repeated execution of the program loop body upon second and subsequent passes through the program loop body using loop control data provided by the loop-end instruction without requiring the loop-end instruction to be explicitly executed upon each pass.
    Type: Grant
    Filed: March 21, 2017
    Date of Patent: August 18, 2020
    Assignee: ARM Limited
    Inventors: Alasdair Grant, Thomas Christopher Grocutt, Simon John Craske
  • Patent number: 10740264
    Abstract: A synchronous differential memory interconnect may include a bidirectional differential data signal bus, a unidirectional differential command and address bus, and a differential clock signal. Memory read and write data may be transmitted over the data signal bus in a serial fashion.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: August 11, 2020
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Melvin K. Benedict, Reza Bacchus, Mujeeb Rehman
  • Patent number: 10740787
    Abstract: Methods and systems are disclosed to monitor a media device via a universal serial bus (“USB”) port. An example method includes obtaining a voltage output by a UBS port of the media device and determining if the voltage exceeds a threshold. If the voltage exceeds the threshold, the example method includes determining the media device is in an on state. If the voltage does not exceed the threshold, the example method includes determining the media device is in an off state.
    Type: Grant
    Filed: October 20, 2017
    Date of Patent: August 11, 2020
    Assignee: The Nielsen Company (US), LLC
    Inventors: Mark Cave, Joseph Volpatti
  • Patent number: 10720195
    Abstract: The present disclosure is directed to efficient memory activation at runtime. A memory module (e.g., a memory riser) being added to a device would typically cause the device to enter system management mode (SMM) to activate the memory module. However, activation (e.g., memory module initialization, hardware training and system reconfiguration) in SMM may substantially delay the resumption of normal operations. Consistent with the present disclosure, at least the memory module initialization and hardware training portions of the activation may be performed by an operating system (OS) in the device, allowing normal device operation to continue during the activation. The OS portion of the activation may generate configuration data. In at least one embodiment, the configuration data may be applied for use in SMM. For example, a system management interrupt (SMI) handler may apply the configuration data during a quiescent period (e.g., a period of inactivity) that occurs during SMM.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: July 21, 2020
    Assignee: Intel Corporation
    Inventors: Zhijun Liu, Jian Tang
  • Patent number: 10713156
    Abstract: Methods of mapping memory regions to processes based on thermal data of memory regions are described. In some embodiments, a memory controller may receive a memory allocation request. The memory allocation request may include a logical memory address. The method may further include mapping the logical memory address to an address in a memory region of the memory system based on thermal data for memory regions of the memory system. Additional methods and systems are also described.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: July 14, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Robert Walker, David A. Roberts
  • Patent number: 10713056
    Abstract: A non-limiting example of a computer-implemented method for implementing wide vector execution for an out-of-order processor includes entering, by the out-of-order processor, a single thread mode. The method further includes partitioning, by the out-of-order processor, a vector register file into a plurality of register files, each of the plurality of register files being associated with a vector execution unit, the vector execution units forming a wide vector execution unit. The method further includes receiving, by a vector scalar register of the out-of-order processor, a wide vector instruction. The method further includes processing, by the wide vector execution unit, the wide vector instruction.
    Type: Grant
    Filed: November 8, 2017
    Date of Patent: July 14, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Silvia M. Mueller, Mauricio J. Serrano, Balaram Sinharoy
  • Patent number: 10713052
    Abstract: Disclosed embodiments relate to a prefetcher for delinquent irregular loads. In one example, a processor includes a cache memory, fetch and decode circuitry to fetch and decode instructions from a memory; and execution circuitry including a binary translator (BT) to respond to the decoded instructions by storing a plurality of decoded instructions in a BT cache, identifying a delinquent irregular load (DIRRL) among the plurality of decoded instructions, determining whether the DIRRL is prefetchable, and, if so, generating a custom prefetcher to cause the processor to prefetch a region of instructions leading up to the prefetchable DIRRL.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: July 14, 2020
    Assignee: INTEL CORPORATION
    Inventors: Karthik Sankaranarayanan, Stephen J. Tarsa, Gautham N. Chinya, Helia Naeimi