Patents Examined by Michael T. Tran
  • Patent number: 11514963
    Abstract: A SOT-MRAM cell, comprising at least one magnetic tunnel junction (MTJ) comprising a tunnel barrier layer between a pinned ferromagnetic layer and a free ferromagnetic layer; a SOT line, extending substantially parallel to the plane of the layers and contacting a first end of said at least one MTJ; at least a first source line connected to one end of the SOT line; at least a first bit line and a second bit line, wherein the SOT-MRAM cell comprises one MTJ, each bit line being connected to the other end of the MTJ; or wherein the SOT-MRAM cell comprises two MTJs, each MTJ being connected to one of the first bit line and second bit line.
    Type: Grant
    Filed: December 17, 2020
    Date of Patent: November 29, 2022
    Assignee: Antaios
    Inventors: Marc Drouard, Julien Louche
  • Patent number: 11516042
    Abstract: In-vehicle detection system includes nonvolatile memory, a controller (SoC) that reads and writes data from and in nonvolatile memory, and detector that outputs detection information to SoC. SoC changes a control signal of nonvolatile memory in accordance with the output of detector.
    Type: Grant
    Filed: July 8, 2019
    Date of Patent: November 29, 2022
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventor: Kunisato Yamaoka
  • Patent number: 11507761
    Abstract: In one example in accordance with the present disclosure a device is described. The device includes at least two memristive cells. Each memristive cell includes a memristive element to store one component of a complex weight value. The device also includes a real input multiplier coupled to the memristive element to multiply an output signal of the memristive element with a real component of an input signal. An imaginary input multiplier of the device is coupled to the memristive element to multiply the output signal of the memristive element with an imaginary component of the input signal.
    Type: Grant
    Filed: February 25, 2016
    Date of Patent: November 22, 2022
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Brent Buchanan, Le Zheng
  • Patent number: 11502096
    Abstract: A memory device includes a first well, a second well, a first active area, a second active area, a third active area, a first poly layer and a second poly layer. The first well is of a first conductivity type. The second well is of a second conductivity type different from the first conductivity type. The first active area is of the second conductivity type and is formed on the first well. The second active area is of the first conductivity type and is formed on the first well and between the first active area and the second well. The third active area is of the first conductivity type and is formed on the second well. The first poly layer is formed above the first well and the second well. The second poly layer is formed above the first well.
    Type: Grant
    Filed: August 4, 2021
    Date of Patent: November 15, 2022
    Assignee: eMemory Technology Inc.
    Inventors: Chia-Jung Hsu, Wein-Town Sun
  • Patent number: 11495278
    Abstract: According to one embodiment, a memory device includes first and second wiring lines, memory cells between first and second wiring lines, first and second common wiring lines, a first selecting circuit between one ends of the first wiring lines and the first common wiring line, and a second selecting circuit between the other ends of the first wiring lines and the first common wiring line. A path between the first wiring line and the first common wiring line through the first selecting circuit and a path between the first wiring line and the first common wiring line through the second selecting circuit are defined as first and second paths, one of the first and second paths is set to an electrically conductive state.
    Type: Grant
    Filed: March 15, 2021
    Date of Patent: November 8, 2022
    Assignee: KIOXIA CORPORATION
    Inventors: Yoshiaki Osada, Kosuke Hatsuda
  • Patent number: 11488670
    Abstract: Devices and techniques temperature sensitive NAND programming are disclosed herein. A device controller can receive a command to write data to a component of the device. A temperature can be obtained in response to the command, and the temperature can be combined with a temperature compensation value to calculate a verification level. The command can then be executed in accordance with the verification level.
    Type: Grant
    Filed: February 22, 2021
    Date of Patent: November 1, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Xiangang Luo, Jianmin Huang, Jung Sheng Hoei, Harish Reddy Singidi, Ting Luo, Ankit Vinod Vashi
  • Patent number: 11488644
    Abstract: A semiconductor device capable of performing high-speed read or high-reliability read is provided. A reading method of a NAND flash memory includes: pre-charging a sensing node through a voltage-supply node; discharging the sensing node to the voltage-supply node for a prescribed operation; recharging the sensing node by the voltage-supply node after the prescribed operation; and discharging a NAND string and sensing a memory cell.
    Type: Grant
    Filed: May 14, 2021
    Date of Patent: November 1, 2022
    Assignee: Winbond Electronics Corp.
    Inventors: Sho Okabe, Makoto Senoo
  • Patent number: 11488968
    Abstract: An IC structure comprises a substrate, a first SRAM cell, and a second SRAM cell. The first SRAM cell is formed over the substrate and comprises a first N-type transistor. The second SRAM cell is formed over the substrate and comprises a second N-type transistor. A gate structure of first N-type transistor of the first SRAM cell has a different work function metal composition than a gate structure of the second N-type transistor of the second SRAM cell.
    Type: Grant
    Filed: July 12, 2021
    Date of Patent: November 1, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Jhon-Jhy Liaw
  • Patent number: 11487454
    Abstract: A method for memory block management includes identifying a first group of bit lines corresponding to memory blocks of a 3-dimensional memory array. The method also includes biasing the first group of bit lines to a first voltage using respective bit line biasing transistors. The method also includes identifying, for each memory block, respective sub-memory blocks corresponding to word lines of each memory block that intersect the first group of bit lines. The method also includes logically grouping memory addresses of memory cells for each respective sub-memory block associated with the first group of bit lines.
    Type: Grant
    Filed: December 5, 2019
    Date of Patent: November 1, 2022
    Assignee: SanDisk Technologies LLC
    Inventors: Masatoshi Nishikawa, Hardwell Chibvongodze
  • Patent number: 11488650
    Abstract: A memory processing unit architecture can include a plurality of memory regions and a plurality of processing regions interleaved between the plurality of memory regions. The plurality of processing regions can be configured to perform computation functions of a model such as an artificial neural network. Data can be transferred between the computation functions in respective memory processing regions. In addition, the memory regions can be utilized to transfer data between a computation function in one processing region and a computation function in another processing region adjacent to the given memory region.
    Type: Grant
    Filed: April 6, 2020
    Date of Patent: November 1, 2022
    Assignee: MemryX Incorporated
    Inventors: Mohammed A. Zidan, Jacob Christopher Botimer, Chester Liu, Fan-hsuan Meng, Timothy Alan Wesley, Zhengya Zhang, Wei Lu
  • Patent number: 11488647
    Abstract: Aspects of the present disclosure are directed to magnetic tunnel junction (MTJ) structures comprising multiple MTJ bits connected in series. For example, a magnetic tunnel junction (MTJ) stack according to the present disclosure may include at least a first MTJ bit and a second MTJ bit stacked above the first MTJ bit, and a resistance state of the MTJ stack may be read by passing a single read current through both the first MTJ bit and the second MTJ bit.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: November 1, 2022
    Assignee: Everspin Technologies, Inc.
    Inventors: Jijun Sun, Frederick Mancoff, Jason Janesky, Kevin Conley, Lu Hui, Sumio Ikegawa
  • Patent number: 11482271
    Abstract: Memory devices and systems with configurable die refresh stagger, and associated methods, are disclosed herein. In one embodiment, a memory system includes two or more memory dies. At least one memory die includes a fuse array storing refresh information that specifies a refresh group of the memory die. In these and other embodiments, at least one memory die includes a refresh group terminal and refresh group detect circuitry electrically connected to the refresh group terminal. The at least one memory die is configured to detect a refresh group of the memory die and to delay its refresh operation by a time delay corresponding to the refresh group. In this manner, refresh operations of the two or more memory dies can be staggered to reduce peak current demand of the memory system.
    Type: Grant
    Filed: April 19, 2021
    Date of Patent: October 25, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Dale H. Hiscock, Michael Kaminski, Joshua E. Alzheimer, John H. Gentry
  • Patent number: 11482290
    Abstract: A controller including a test manager configured to output a program command for performing a program operation of a memory block and a suspend command for stopping the program operation, and a memory interface configured to transmit the program command to a memory device including the memory block, and transmit the suspend command to the memory device after a set time elapses. The test manager outputs a read command for reading memory cells included in the memory block, the memory interface calculates a count value by counting data output from the memory device in response to the read command, and the test manager generates status information on the memory block according to the count value.
    Type: Grant
    Filed: March 22, 2021
    Date of Patent: October 25, 2022
    Assignee: SK hynix Inc.
    Inventors: Dong Uk Lee, Hae Chang Yang, Hun Wook Lee
  • Patent number: 11475956
    Abstract: A method of operating a nonvolatile memory device which includes at least one memory block is provided. The method includes providing a plurality of word-lines with a voltage during a word-line set-up period, precharging a plurality of driving lines with a voltage during a word-line development period, detecting a voltage drop of a sensing node during a sensing period, and detecting leakage based on the voltage drop.
    Type: Grant
    Filed: April 19, 2021
    Date of Patent: October 18, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Chaehoon Kim, Junyoung Ko, Sangwan Nam, Minjae Seo, Jiwon Seo, Hojun Lee
  • Patent number: 11475943
    Abstract: A storage unit includes a latch, and the latch provides a first storage bit. The storage unit further includes a first MOS transistor. A gate of the first MOS transistor is connected to the first storage bit, a source of the first MOS transistor is connected to a first read line, and a drain of the first MOS transistor is connected to a second read line. In a first state, the first read line is a read word line, and the second read line is a read bit line; or in a second state, the second read line is a read word line, and the first read line is a read bit line.
    Type: Grant
    Filed: April 9, 2021
    Date of Patent: October 18, 2022
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Sijie Chi, Bingwu Ji, Tanfu Zhao, Yunming Zhou
  • Patent number: 11474890
    Abstract: The present technology relates to a memory system and a method of operating the memory system. The memory system includes a memory device including a plurality of semiconductor memories, and a controller for controlling the memory device to perform a test program operation and a threshold voltage distribution monitoring operation on each of the plurality of semiconductor memories during an operation. The controller sets operation performance parameters of each of the semiconductor memories based on monitoring information obtained as a result of the threshold voltage distribution monitoring operation.
    Type: Grant
    Filed: October 28, 2019
    Date of Patent: October 18, 2022
    Assignee: SK hynix Inc.
    Inventor: Jong Wook Kim
  • Patent number: 11468927
    Abstract: A semiconductor storage device includes a memory cell array, and a peripheral circuit that is connected to the memory cell array, and that inputs and outputs user data in response to an input of a command set including command data and address data. The peripheral circuit includes a command register, an address register, and a queue register. The command register includes an n-bit first register column capable of storing n-bit data forming the command data. The address register includes an n-bit second register column capable of storing n-bit data forming the address data. The queue register includes a plurality of third register columns, each capable of storing at least (n+1) bit data, and each third register column is capable of storing the n-bit data forming the command data or the n-bit data forming the address data.
    Type: Grant
    Filed: February 26, 2021
    Date of Patent: October 11, 2022
    Assignee: KIOXIA CORPORATION
    Inventor: Yuuta Sano
  • Patent number: 11462267
    Abstract: A system may include a multi-lead memristor. The multi-lead memristor may include a first lead, a second lead, a third lead, a first memristor material, and a second memristor material. The second lead may be positioned between the first lead and the third lead. The first memristor material may be positioned between the first lead and the second lead. The second memristor material may be positioned between the second lead and the third lead.
    Type: Grant
    Filed: December 7, 2020
    Date of Patent: October 4, 2022
    Assignee: Rockwell Collins, Inc.
    Inventors: Kyle B. Snyder, Nathaniel P. Wyckoff, Brandon C. Hamilton, Bruce Rowenhorst, Steven J. Wiebers
  • Patent number: 11462277
    Abstract: Embodiments are provided that include a memory device having a memory array including a plurality of access lines and data lines. The memory device further includes a circuit coupled to the plurality of access lines and configured to provide consecutive pulses to a selected one of the plurality of access lines. Each pulse of the consecutive pulses includes a first voltage and a second voltage. The first voltage is greater in magnitude than the second voltage, and the first voltage is applied for a shorter duration than the second voltage.
    Type: Grant
    Filed: April 30, 2021
    Date of Patent: October 4, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Toru Tanzawa
  • Patent number: 11462282
    Abstract: A semiconductor memory device includes a first word line formed over a first active region. In some embodiments, a first metal line is disposed over and perpendicular to the first word line, where the first metal line is electrically connected to the first word line using a first conductive via, and where the first conductive via is disposed over the first active region. In some examples, the semiconductor memory device further includes a second metal line and a third metal line both parallel to the first metal line and disposed on opposing sides of the first metal line, where the second metal line is electrically connected to a source/drain region of the first active region using a second conductive via, and where the third metal line is electrically connected to the source/drain region of the first active region using a third conductive via.
    Type: Grant
    Filed: April 1, 2020
    Date of Patent: October 4, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsin-Wen Su, Kian-Long Lim, Wen-Chun Keng, Chang-Ta Yang, Shih-Hao Lin