Abstract: An attenuator with a simple circuit configuration is and accurate attenuation includes four transistors connected in parallel between a connecting point on a main line and a ground. Since the transistors are individually brought into an “ON” state and an “OFF” state to function as “resistors” or “capacitors”, a desired attenuation be obtained by combinations of the ON and OFF states of the respective transistors.

Abstract: An n-bit quantizer of a downstream modulator stage is configured to produce an n-bit quantized signal from an analog signal having a range. The n-bit quantizer divides the range into 2n subranges. A first subrange of the 2n subranges is bounded by a lowest value of the range, a second subrange of the 2n subranges is bounded by a highest value of the range, and at least one remaining subrange of the 2n subranges is positioned between the first and the second subranges. The first and the second subranges each measure greater than {1/[2(2n−1)]} of the total range. Each of the at least one remaining subrange measures less than [1/(2n−1)] of the total range. A first gain of an integrator of the downstream modulator stage is set so that the downstream modulator stage is stable.

Abstract: The waveguide polarizer is a device for microwave antenna systems consisting of a waveguide section, with circular cross-section, being equipped with two terminal flanges for connection to other circular guides. A certain number of elliptical irises are arranged inside at regular intervals, resting on parallel planes and all oriented in the same way, i.e. with their longer axes all belonging to the same axial plane.

Abstract: The system includes a unipolar A/D converter, which samples analog signal inputs thereto, the A/D converter being used in a protective relay for electric power systems. The unipolar A/D converter is responsive to input voltage values and current values from the power line to produce corresponding digital signals. The A/D converter has a ground pin voltage reference at least as negative as the most negative point of the input signal to be processed.

Abstract: An impedance matching circuit includes a conductor line having an input port and an output port, a ground conductor, a tunable dielectric material positioned between a first section of the conductor line and the ground conductor, a non-tunable dielectric material positioned between a second section of the conductor line and the ground conductor, and means for applying a DC voltage between the conductor line and the ground conductor. The impedance matching circuit may alternatively include a first planar ground conductor, a second planar ground conductor, a strip conductor having an input port and an output port, and positioned between the first and second planar ground conductors to define first and second gaps, the first gap being positioned between the strip conductor and the first planar ground conductor and the second gap being positioned between the strip conductor and the second planar ground conductor.

Abstract: An configurable integrated-circuit device includes a plurality of regions that each contain electronic circuitry. The configurable integrated-circuit device also includes common circuitry adapted to provide at least one signal to at least two regions of the plurality of regions. The common circuitry and the at least two regions are positioned within the configurable integrated-circuit device so as to improve the latencies of the at least one signal to each of the at least two regions.

Abstract: An apparatus for receiving an input clock signal to an integrated circuit device is disclosed. In an exemplary embodiment of the invention, the apparatus includes a CMOS receiver configured to receive the input clock signal and a PECL receiver configured to receive the input clock signal. The PECL receiver shares a common output node with the CMOS receiver. A receiver selection mechanism is coupled to the CMOS receiver and the PECL receiver, with the receiver selection mechanism alternatively activating or deactivating the CMOS receiver and the PECL receiver.

Abstract: A programmable logic device has subregions of programmable logic grouped together in logic regions. The subregions in each region share several control signals, which can be selected either from relatively global conductors on the device or from data inputs to the region. The control signals allow synchronous or asynchronous clearing of a register in each subregion. The control signals also allow synchronous loading of the register in each subregion, and the data loaded can be either one of the data inputs to the subregion (so-called lonely register operation) or a signal produced by the logic of the subregion.

Abstract: A method of processing audio input signals comprising 1-bit, Sigma-Delta Modulated (SDM) signals is disclosed including the steps of combining the audio input signals to form a combined audio input signal; and utilising a Sigma-Delta Modulator to convert the combined audio input signal to a corresponding Sigma-Delta Modulated output signal. The method can include a linear mix of the audio input signals and each audio input signal can multiplied by a corresponding gain factor before being added together with other of the audio input signals. The Sigma-Delta Modulator can include a noise shaping filter designed to amplify components of the audio input signals below a predetermined threshold frequency and the combining step can include utilising a negative feedback of the combined audio input signal. The noise shaping filter can utilise a series of integrating circuits as a means to decrease the sensitivity of the filter to errors in its coefficients.

Abstract: A logic array includes a first logic plane, a second logic plane, and a third logic plane. The first logic plane has a first plurality of intermediate outputs, and the second logic plane has a second plurality of intermediate outputs. The third logic plane has first and second opposing sides and is adapted to receive the first and second pluralities of intermediate outputs. The first plurality of intermediate outputs intersect the third logic plane through the first side, and the second plurality of intermediate outputs intersect the third logic plane through the second side. A method for increasing the density of a logic array includes providing a first logic plane, a second logic plane, and a third logic plane. The first logic plane has a first plurality of intermediate outputs, and the second logic plane has a second plurality of intermediate outputs. The first plurality of intermediate outputs and the second plurality of intermediate outputs are interleaved in the third logic plane.