Abstract: Various implementations described herein are directed to a method of integrated circuit design and fabrication. In the implementation of a memory integrated circuit, the floorplan of the integrated circuit comprises memory blocks, where instantiations of the memory blocks are optimized to satisfy timing specifications while minimizing power consumption or not significantly contributing to leakage current.

Abstract: Apparatuses, systems, methods, and computer program products are disclosed for changing storage parameters. An integrated circuit (IC) memory element receives a command to change a value of a parameter associated with the IC memory element. A parameter includes a setting for one or more storage operations of an IC memory element. An IC memory element receives one or more data sets with a command. A data set includes an identifier associated with a parameter to be changed and a new value for the parameter. Each of one or more data sets is received at a same data rate as a command. An IC memory element writes, for each of one or more data sets, a new value for a parameter to a storage location associated with the parameter.

Abstract: Apparatus include an array of memory cells, a controller to perform access operations on the array of memory cells, a clock signal node, a counter having an input selectively connected to the clock signal node, and a clock generator having an output connected to the input of the counter.

Abstract: According to one embodiment, a semiconductor storage device includes a memory cell array having memory cell capable of holding N-bit data; and a sense amplifier comprising a first latch holding information on a threshold distribution, a second latch holding write data, and a third latch holding lower information of the N-bit data, and supplying a first to a fourth voltages to the memory cell to write the data to the memory cell using the first to fourth voltages. The sense amplifier supplies the first to third voltages to the memory cell based on information in the second and the third latches, and based on a result of transfer of the information held by the first latch to the second latch, supplies the fourth voltage or the first voltage to the memory cell.

Abstract: A method of obtaining a dot product includes applying a number of first voltages to a corresponding number of row lines within a memristive cross-bar array to change the resistive values of a corresponding number of memristors located a junctions between the row lines and a number of column lines. The first voltages define a corresponding number of values within a matrix, respectively. The method further includes applying a number of second voltages to a corresponding number of the row lines within the memristive cross-bar array. The second voltages define a corresponding number of vector values. The method further includes collecting the output currents from the column lines. The collected output currents define the dot product.

Abstract: A non-volatile semiconductor storage device includes a gate insulating film formed on a semiconductor substrate, a gate electrode formed on the gate insulating film, and first and second spaced apart doped regions formed below the gate insulating film and the gate electrode in the semiconductor substrate, wherein a grounded region of the first and second spaced apart doped regions is grounded via a contact.

Abstract: The disclosed technology generally relates to magnetic memory and more particularly to voltage-controlled magnetic memory, and to methods of using same. In one aspect, a magnetic memory comprises a first magnetic stack including a first gate dielectric layer formed between a first gate electrode and a first free ferromagnetic layer. The magnetic memory additionally comprises a second magnetic stack including a second gate dielectric layer formed between a second gate electrode and a second free ferromagnetic layer. The first free ferromagnetic layer and the second free ferromagnetic layer of the magnetic memory are magnetically coupled, contiguous and are positioned at an oblique angle relative to each other, and the first gate electrode and the second gate electrode are electrically isolated from each other.

Abstract: A semiconductor device may include a valid command generation circuit and a training control circuit. The valid command generation circuit may be configured to latch an internal chip selection signal and an internal control signal in synchronization with a division clock signal to generate a latch chip selection signal and a latch control signal. The valid command generation circuit may be configured to generate a valid command for executing a predetermined function from the latch control signal. The training control circuit may be configured to generate a training result signal from the latch chip selection signal or the latch control signal based on a flag.

Abstract: A semiconductor device with a memory unit of which the variations in the operation timing are reduced is provided. For example, the semiconductor device is provided with dummy bit lines which are arranged collaterally with a proper bit line, and column direction load circuits which are sequentially coupled to the dummy bit lines. Each column direction load circuit is provided with plural NMOS transistors fixed to an off state, predetermined ones of which have the source and the drain suitably coupled to any of the dummy bit lines. Load capacitance accompanying diffusion layer capacitance of the predetermined NMOS transistors is added to the dummy bit lines, and corresponding to the load capacitance, the delay time from a decode activation signal to a dummy bit line signal is set up. The dummy bit line signal is employed when setting the start-up timing of a sense amplifier.

Abstract: Higher word line voltages facilitate write operations in spin-torque magnetic memory devices, but overdriving the gate of a selection transistor with such higher word line voltages can damage the selection transistor if the gate-to-source voltage for the selection transistor is too high. Therefore in order to support the word line voltage needed on the gate of the select transistor for an up-current write operation without exceeding limits on the gate-to-source voltage for the select transistor, the gate of the selection transistor can be driven in a two-step process. The gate of the selection transistor is first driven to a lower voltage within the limits of the gate-to-source voltage for the transistor when the source of the transistor is grounded or at a voltage near ground. A voltage is then applied across the memory cell, which results in the source of the selection transistor being raised above its initial ground or near-ground state.

Abstract: A memory control circuit unit, a memory storage device and a signal receiving method. In one exemplary embodiment, a memory interface circuit of the memory control circuit unit receives a first signal from a volatile memory and adjusts a voltage value of the first signal to a voltage range in response to an internal impedance of the memory interface circuit, where a central value of the voltage range is not equal to a default voltage value, and the default voltage value is one half a sum of a voltage value of a supply voltage of the memory interface circuit and a voltage value of a reference ground voltage. In addition, the memory interface circuit further generates an input signal according to a voltage correspondence between the first signal and an internal reference voltage.

Abstract: A method and apparatus for using neighboring sampling points in a memory subsystem calibration is disclosed. In one embodiment, a memory subsystem includes a memory and a memory controller coupled thereto. A calibration unit in the memory controller is configured to perform calibrations of a data strobe signal and a reference voltage to determine eye openings for signals conveyed between the memory and the memory controller. Performing the calibration includes determining a number of different calibration points and computing initial scores for each of the calibration points. The method further includes calculating adjusted scores for each calibration point. For a given calibration point, the adjusted score includes weighted values of one or more calibration points that are adjacent thereto. The method further includes selecting a calibration point having the highest adjusted score as the calibrated value.

Abstract: Voltage monitors include a predelay cell having an input responsive to a first clock signal. This cell is configured to generate a predelayed clock signal at an output thereof. A serially-connected string of data delay cells is provided, which has an input responsive to the predelayed clock signal. A serially-connected string of clock delay cells is provided, which has an input responsive to a second clock signal that is synchronized to the first clock signal. A plurality latches are provided. The latches have respective data inputs, which are responsive to first periodic signals generated at respective outputs of the serially-connected string of data delay cells, and respective clock/sync terminals, which are responsive to second periodic signals generated at respective outputs of the serially-connected string of clock delay cells. The latches enable loading of a delay code value, which indicates power supply voltage variation.

Abstract: An associative memory that can be integrated with standard computer memory flexibly reduces its parallelism to match the memory bus speed thereby providing substantial increases in memory density possible by a multiplexing of sense amplifiers that otherwise dominate the memory structure. Apparent parallel operation is provided by an accumulator that reassembles the multiplex data. Higher memory density makes dual use of the associative memory as a content addressable memory and random-access memory possible.

Abstract: The present disclosure relate a method of operating a semiconductor memory device including at least two memory blocks sharing one block word line. The method including applying an erase voltage to a source line commonly coupled to the memory blocks, one of which is a selected memory block and applying a first voltage to the block word line and a third voltage to a global word line of an unselected memory block of the memory blocks when the erase voltage is applied to the source line, wherein the first voltage is higher than a turn-on voltage to turn on a pass transistor coupled to the block word line, and wherein the third voltage floats a local word line included in the unselected memory block according to a level of the first voltage.

Abstract: An apparatus used in a self-referenced read of a memory bit cell includes circuitry including a plurality of transistors that includes an NMOS-follower transistor for applying a read voltage to a first end of the bit cell. An offset current is applied by an offset current transistor. A transmission gate allows for isolation of a capacitor used to store a sample voltage corresponding to the read voltage applied across the memory bit cell.

Abstract: In one example embodiment, an analysis application is used to optimize sensor placement by implementing a two-part optimization solution procedure, involving generating a contribution database, and determining an optimized sensor location set using the contribution database. The optimized sensor location set may indicate locations that maximize coverage of dynamic integrity, which is quantified by as a ratio of detectable damage scenarios to all damage scenarios used by the analysis application.

Abstract: A comparison circuit may be provided. The comparison circuit may include a number of first logic circuits and a number of second logic circuits. The first logic circuits and second logic circuits may be configured to compare logic levels of a plurality of input signals with each other to generate a comparison signal having a first logic level if the number of input signals have an even number of input signals at a second logic level.

Abstract: A non-volatile memory device includes a memory array having memory cells arranged in wordlines and receiving a supply voltage. A row decoder includes an input and pre-decoding module, which is configured to receive address signals and generate pre-decoded address signals at low voltage, in the range of the supply voltage. A driving module is configured to generate biasing signals for biasing the wordlines of the memory array starting from decoded address signals, which are a function of the pre-decoded address signals, at high voltage and in the range of a boosted voltage higher than the supply voltage. A processing module is configured to receive the pre-decoded address signals and to jointly execute an operation of logic combination and an operation of voltage boosting of the pre-decoded address signals for generation of the decoded address signals.

Abstract: According to one embodiment, a semiconductor memory device includes a memory cell array, a data storage circuit and a control circuit. The data storage circuit holds first data to be written into the memory cell and holds 1 bit data calculated from the first data. The control circuit writes the data of n bits into the memory cell in a first write operation and then executes a second write operation. The control circuit carries out the following control in the second write operation. It reads data stored in the memory cell in the first write operation. It restores the first data based on the data read from the memory cell and the 1 bit data held in the data storage circuit. It writes the restored first data into the memory cell.