Abstract: A digital audio radio system that employs transmitting multiple time-separated versions or legs of the same or substantially the same source signal to accommodate signal blockage problems while using no or little additional bit data rate. In one embodiment, a first leg transmits only right channel data and a second leg transmits only left channel data when no blockage occurs, the two legs can be combined to provide a complete signal and perfect reception. If one of the legs is blocked, then a cloning technique is used to clone the existing channel as the non-existing channel to provide either a combination of two right channels or two left channels. In another embodiment, a first leg transmits a sequence of the even frames including both right and left channel data and leaves the odd frames blank, and a second leg transmits a sequence of the odd frames including both the right and left channel data and leaves the even frames blank.

Abstract: An input signal is supplied to a tapped-delay line adaptive filter to produce tap signals which are equally divided into groups. The tap signals are selectively coupled on a per group basis through a switch to coefficient generators where tap-weight coefficients are produced. The selected tap signals are weighted respectively by the coefficients and summed together to produce a correction signal, which is combined with an output signal which is a replica of the input signal. The coefficients are updated with a residual error of the correction signal. Using the coefficients, the hopping order for selecting a tap group and the dwell time of the tap group are determined. Total power of the selected tap signals is monitored. When the monitored power is lower than a threshold value, the determination of the hopping order and dwell time is disabled, coefficient updating is disabled, and the residual error is nullified for fast convergence.

Abstract: A method for configuring the receiver with an IF delay value that indicates the timing of symbol transitions in a received signal processed by the receiver. The receiver recovers a timing that has the same period as the symbol period, but which is out of phase with the received symbols. The received symbols are members of a constellation with elements that have purely I or purely Q components. A symbol-quality signal is generated by constructing the quantity .vertline..vertline.I.vertline.-.vertline.Q.vertline..vertline.. This quantity is a maximum when the detected symbols are aligned with the expected points in the symbol constellation, and decreases if the detected symbols are rotated away from these constellation points. The method determines an optimal delay value by which the symbol clock should be shifted from the recovered timing by using the symbol-quality signal to evaluate test delays and to successively refine them until the optimal delay value is found.

Abstract: A universal modem has a software-configurable modulator/demodulator which commodates different modulation formats such as those associated with terrestrial, cable, phone line, satellite and wireless communications to be transmitted and received through a single device in which the modem has reconfigurable logic to accommodate the format of the signals being received or transmitted. Note that the modulator or demodulator can be used separately or the two units can be combined and used for transceivers, with either the same software configuring both the modulator and demodulator, or with different software used for the two units. In the receive mode, the universal modem detects the modulation format of the incoming signal and reconfigures the logic of its software-configurable demodulator to output demodulated digital data for further processing.

Abstract: In a process for the coherent demodulation of a reception signal, several coefficients of the channel impulse response are determined beforehand. The coefficients are divided into at least two gain taps and at least one loss tap. The loss taps are utilized for a feedback filter to eliminate a corresponding signal component. The signal cleared up in this manner is estimated in a log-likelihood equalizer on the basis of gain taps. The process is characterized in that neither filter training nor high mathematical effort are required for determining the equalizer coefficients. There is also no error floor for the high frequency band signal. The quantity of operations required per symbol in the detection phase is comparatively small.

Abstract: A normalization circuit for preventing divergence of the normalizing voltage of a coupler used for diversity operation in a communication system includes: a phase detector for generating a phase detection signal corresponding to first and second phase differences of the signals received from first and second inputs; a normalizer including a reference voltage generator for normalizing the phase detection signal so as to alternatively output one of either a constant voltage value, or a reference voltage value in the event that the constant voltage value is less than the reference voltage value; a phase shifter for multiplying and adding output of the normalizer by and with the first and second phase differences; and an adder for adding the output of the phase shifter to the signals received from the second input.

Abstract: A programmable apparatus is disclosed for generating a frequency modulated signal at a selected center frequency in accordance with digital data of at least first and second data levels. The modulating apparatus comprises a modulator having an input and an output and is responsive to an input modulation signal applied to its input for generating at its output the frequency modulated signal at a center frequency dependent on a quiescent voltage appearing at its input. A circuit is provided for sampling and storing a value of the quiescent voltage. An addressable memory stores a plurality of offsets. A programmable adding circuit adds a downloaded offset voltage to the stored value of the quiescent voltage to output a high modulation voltage. A programmable subtracting circuit subtracts a downloaded offset voltage from the stored value of the quiescent voltage to provide a low modulation voltage.

Abstract: A digital implementation for a carrier detector. The detector determines if the carrier frequency at any instant is within a predetermined frequency band. The detector further determines if the detected frequency remains within the predetermined frequency band for a predetermined period of time. The detector also provides an indication that there has not been any loss of carrier for another predetermined period of time.

Abstract: A transceiver (5) for an asymmetric communication system such as asymmetric digital subscriber line (ADSL) includes a configuration register (71) defining operation at either a central office (CO) or a remote terminal (RT). The configuration register (71) includes a control bit (72) for selecting either CO or RT mode. The transceiver (5) includes a signal processing module (70) configured according to the state of the control bit (72). For example, a digital interface (70) converts transmit data into transmit symbols and converts received symbols into receive data. The digital interface (70) uses a large memory (158) as a buffer in the transmit path and a small memory (160) as a buffer in the receive path in CO mode. In RT mode, the digital interface (70) uses the small memory (160) in the transmit path and the large memory (158) in the receive path. The selective configuration allows a single integrated circuit to be used in both CO and RT equipment.

Abstract: In a discrete tone system, a base station receives a transmission burst from a remote unit being installed that includes delay compensation pilot tones that are uniformly spread throughout the transmission bandwidth. The arrival time transmission burst is not synchronized with the other remote units transmitting to the base station. The base station measures the phase delay of each tone and calculates the delay of the remote unit from the slope of the line of phase angle versus tone frequency. The base station transmits a signal to the remote unit that includes the magnitude and direction of the delay, which allows the remote unit to adapt the timing of its transmission to be synchronized with the other remote units.

Abstract: The invention relates to a data reception device for receiving packetized data in the form of a differential signal. This device comprises a data reception section that generates a digital signal an the basis of the differential signal; a decode section that generates a bit synchronization signal and serial binary data based on this digital signal; a link detection section that detects whether or not a link has been guaranteed, based on this digital signal, and outputs a link signal; and a polarity determination section that determines whether polarities have been identified correctly, based on this serial binary data, the bit synchronization signal, and the link signal.

Abstract: In order to correct nonlinearities of an amplifier which receives a radio signal and produces an amplified radio signal representing an input complex digital signal, a predistortion table, associating a value of a predistorted complex digital signal with each value of the input complex digital signal, is stored, and the predistorted complex signal is modulated in order to obtain the radio signal addressed to the amplifier. In an adaptation period, a fraction of the amplified radio signal is demodulated in order to obtain a demodulated complex signal which is compared with the input complex signal, with which the predistorted complex signal modulated in said adaptation period is associated, in order to update the predistortion table. The predistortion table is updated on the basis of mean values calculated from blocks of samples of the input complex signal and of the demodulated complex signal, which are stored in the adaptation period.

Abstract: A method and device for encoding and transmitting a clock signal, a supply voltage and bidirectional digital data from a master circuit to a slave circuit, including the steps of: holding a first conductor at a first voltage with respect to a second conductor; periodically raising the first conductor to a second voltage with respect to the second conductor, a fixed period after a previous raising to the second voltage; holding the first conductor at the second voltage for one of a number of predetermined periods, then returning the first conductor to the first voltage, the voltage of the first conductor not falling below the first voltage; controlling the predetermined periods to each have one of a number of fixed durations, each duration having a logical significance.

Abstract: The digital matched filter according to the present invention comprises a storage circuit for accumulating received signals by an A/D converter without shifting the signals, an address signal generating circuit for controlling an address for accumulating output from the A/D converter there, a reference data generating circuit for generating spread code for receiving, a ring-formed shift register for shifting output from the reference data generating circuit, a multiplying circuit for multiplying output from the storage circuit not executing shifting by output from the shift register, an adding circuit for adding output from the multiplying circuit, and a timing signal generating circuit for controlling timing for the operations described above.

Abstract: An improved DBS receiver front end architecture having a voltage controlled oscillator for frequency synthesis. The voltage controlled oscillator includes a tank circuit having an adjustable resonance frequency which may be varied over an octave. A tuning oscillator drives the tank circuit and provides a signal having that resonance frequency to a range extender which provides a tuning frequency. When enabled, the range extender doubles the input frequency, and when disabled, simply passes the input frequency through. A feedback path provides a control voltage to the tank circuit to adjust the resonance frequency and thereby cause the tuning frequency to be a multiple of a reference frequency. The range extender extends the tuning frequency range over two octaves without a loss of frequency resolution. Broadly speaking, the present invention contemplates a DBS receiver front end which includes a tuner chip and a demodulator/decoder chip.

Abstract: A system and method for frequency dehopping of spread spectrum communication signals includes a downconverter having two mixer stages, each mixer stage providing coarse frequency dehopping. The local oscillator injection frequency of each mixer stage is selectable by way of a plurality of relatively easily generated tones. The output of the second mixer stage is sampled by an analog-to-digital converter to enable fine tuning dehopping to be performed in the digital domain and subsequently demodulated in a demodulator circuit.

Abstract: A data and clock recovery circuit includes a front end circuit for receiving a data signal encoded with a Manchester or other bi-phase level code having a sequence of bit frames, and for outputting a recovered data signal and a recovered clock signal in accordance with transitions in the data signal that overlap with a window signal. A window generation circuit generates the window signal in accordance with a delay control signal, and includes circuitry that delays and transforms the recovered clock signal into the window signal. A delay control circuit generates and adjusts the delay control signal. A phase comparison circuit compares the recovered clock signal with leading and lagging portions of the window signal, and generates signals that adjust the delay control signal when the recovered clock signal overlaps with either of the leading and lagging portions of the signal.

Abstract: Known is a digital communication system comprising wireless terminals for voice and non-voice data communication. In order to get a flexible mixed voice and non-voice data communication system terminals for mixed real time voice and reliable non-voice data communication are provided in which set-up channels are dynamically assigned to non-voice or to mixed voice and non-voice communications without first releasing the assigned communication resources. Herewith, at a higher level layer such as an application layer very fast switching over is achieved while other devices in the system are fully unaware of such switching over. In multimedia communications, such a fast switching over is particularly advantageous.

Abstract: In an intermittent receiving apparatus (10) for intermittently receiving a carrier signal having a carrier frequency (f.sub.R) and carrying data as an intermittent received carrier signal so as to alternate between a reception state for a reception time interval (T.sub.R) and a nonreception state for a nonreception time interval (T.sub.NR), an oscillation circuit (16) oscillates a reference signal having a reference frequency (f.sub.REF) equal to the reproduced clock frequency (F.sub.BTR). A clock supply circuit (20) intermittently supplies an output clock signal for a predetermined time duration including the reception time interval to a clock reproduction circuit (15) on the basis of the reference signal.

Abstract: In the method for parameterizing at least one receiving device and a receiving device for a radio station, a plurality of decorrelated signals are received by an intelligent antenna device. Antenna weighting factors for suppressing received disturbances and channel coefficients for balancing out the differences in transit time of different signal components of a received signal are determined simultaneously. During a training sequence, test data present in the receiving device is rated in a channel model with channel coefficients and received test data is rated with antenna weighting factors and superposed to form antenna data or model variables. The minimizing of the deviation of antenna data and model variables is performed with the exclusion of the trivial solution. The method is suitable in particular for base stations in mobile radio systems.