Patents Examined by Michelle L Taeuber
-
Patent number: 10496305Abstract: Storage management is performed by detecting installation of at least one new physical tape drive in a storage system. The storage system may include a plurality of tape drives. The plurality of tape drives include physical tape drives and virtual tape drives. Based on the detection, a unique name of at least one virtual tape drive is transferred to the at least one new physical tape drive.Type: GrantFiled: April 28, 2014Date of Patent: December 3, 2019Assignee: Hewlett Packard Enterprise Development LPInventors: Christopher Anthony Grant Hillier, Curtis C Ballard
-
Patent number: 10496326Abstract: Methods, systems, and apparatus, including an apparatus for transferring data using multiple buffers, including multiple memories and one or more processing units configured to determine buffer memory addresses for a sequence of data elements stored in a first data storage location that are being transferred to a second data storage location. For each group of one or more of the data elements in the sequence, a value of a buffer assignment element that can be switched between multiple values each corresponding to a different one of the memories is identified. A buffer memory address for the group of one or more data elements is determined based on the value of the buffer assignment element. The value of the buffer assignment element is switched prior to determining the buffer memory address for a subsequent group of one or more data elements of the sequence of data elements.Type: GrantFiled: January 4, 2019Date of Patent: December 3, 2019Assignee: Google LLCInventors: Olivier Temam, Harshit Khaitan, Ravi Narayanaswami, Dong Hyuk Woo
-
Patent number: 10482038Abstract: Memory systems may include a programmable bit control unit suitable for defining read-write properties to locations in a base address register (BAR) memory, a read-write switch suitable for receiving a memory access request, and identifying whether the memory access request is a read access or a write access, and an access control unit suitable for receiving the memory access request from the read-write switch when the memory access request is identified as a write access, determining a read-write property associated with the write access, and processing the write access to a location in the BAR memory with a defined read-write property that is the same as the determined read-write property associated with the write request.Type: GrantFiled: July 25, 2016Date of Patent: November 19, 2019Assignee: SK hynix Inc.Inventors: Xianfeng Rui, Ka Wing Cheung, Ryan Yu, Ananthanarayanan Nagarajan
-
Patent number: 10452538Abstract: Disclosed are systems and methods for determining task scores reflective of memory access statistics in NUMA systems. An example method may comprise: determining, by a processing device, a first memory access score of a task with respect to a first node of a Non-Uniform Memory Access (NUMA) system; adjusting the first memory access score using memory access scores of the task with respect to one or more nodes of the NUMA system; and migrating, in view of the adjusting, at least one of: the task or a memory page associated with the task.Type: GrantFiled: January 21, 2015Date of Patent: October 22, 2019Assignee: Red Hat, Inc.Inventors: Henri Han van Riel, Vivek Goyal
-
Patent number: 10430326Abstract: Differential data access. A method for storing and reading data elements to and from a memory is provided. The method includes storing a data element as a base word in a first precision, storing at least one delta word including additional information related to a second precision version of the stored data element, and reading the base word and the at least one delta word of the stored data element to access the data element in the second precision.Type: GrantFiled: December 21, 2016Date of Patent: October 1, 2019Assignee: International Business Machines CorporationInventors: Christoph M. Angerer, Heiner Giefers, Raphael Polig
-
Patent number: 10430325Abstract: Differential data access. A method for storing and reading data elements to and from a memory is provided. The method includes storing a data element as a base word in a first precision, storing at least one delta word including additional information related to a second precision version of the stored data element, and reading the base word and the at least one delta word of the stored data element to access the data element in the second precision.Type: GrantFiled: December 14, 2015Date of Patent: October 1, 2019Assignee: International Business Machines CorporationInventors: Christoph M Angerer, Heiner Giefers, Raphael Polig
-
Patent number: 10417128Abstract: Techniques are described for memory coherence in a multi-core system with a heterogeneous memory architecture comprising one or more hardware-managed caches and one or more software-managed caches. According to one embodiment, a set of one or more buffers are allocated in memory, and each respective buffer is associated with a respective metadata tag. The metadata tag may be used to store metadata that identifies a state associated with the respective buffer. The multi-core system may enforce coherence for the one or more hardware-managed caches and the one or more software-managed caches based on the metadata stored in the metadata tag for each respective buffer in the set of one or more buffers. The multi-core system may read the metadata to determine whether a particular buffer is in a hardware-managed or a software-managed cacheable state. Based on the current state of the particular buffer, the multi-core system may perform coherence operations.Type: GrantFiled: May 6, 2015Date of Patent: September 17, 2019Assignee: Oracle International CorporationInventors: Andrea Di Blas, Aarti Basant, Arun Raghavan, Nipun Agarwal
-
Patent number: 10372365Abstract: Some embodiments provide a method for configuring unit memories of a forwarding element. The method configures a first pool of unit memories to implement several match entries that each include a set of match conditions and an address for an action entry to read when the set of match conditions are met. The method configures a second pool of unit memories to implement several action entries. Each unit memory in the second pool includes a set of action entries that are collectively assigned a virtual memory address. The method moves a particular set of action entries from a first unit memory in the second pool to a second unit memory in the second pool. The particular set of action entries retains a same virtual memory address after moving to the second unit memory.Type: GrantFiled: December 14, 2015Date of Patent: August 6, 2019Assignee: BAREFOOT NETWORKS, INC.Inventor: Patrick Bosshart
-
Patent number: 10365834Abstract: According to one embodiment, a controller executes a first process such that writing is performed in an order of page numbers in the memory chip. The first process includes a second process to be executed in an order of group units. The second process includes a process of writing data to the lower pages of the memory chips belonging to the banks in one group, and subsequently writing data to the upper pages of the memory chips belonging to the banks in the group.Type: GrantFiled: February 1, 2017Date of Patent: July 30, 2019Assignee: TOSHIBA MEMORY CORPORATIONInventors: Yoshihisa Kojima, Katsuhiko Ueki
-
Patent number: 10268416Abstract: A memory-to-memory copy operation control system includes a processor configured to receive an instruction to perform a memory-to-memory copy operation and a memory module network in communication with the processor. The memory module network has a plurality of memory modules that include a proximal memory module in direct communication with the processor and one or more additional memory modules in communication with the processor via the proximal memory module. The system also includes a memory controller in communication with the processor and the network of memory modules. The processor is configured to issue a first command causing data to be copied from a first memory module to a second memory module without sending the data to the processor or the memory controller.Type: GrantFiled: October 28, 2015Date of Patent: April 23, 2019Assignee: Advanced Micro Devices, Inc.Inventors: Nuwan Jayasena, David A. Roberts
-
Patent number: 10248328Abstract: A computer system comprises a processor, a memory module and input/output devices. The memory module includes a circuit board, a volatile memory unit mounted on the circuit board, a non-volatile memory unit mounted on the circuit board and a control circuit mounted on the circuit board. The volatile memory unit comprises DRAM devices, and the non-volatile memory unit comprises flash memory. The processor is configured to execute an operating system (OS) and an application program and to present a memory address space to the application program. The memory address space including a memory mapped input/output (MMIO) space mapped to the I/O devices, a pseudo MMIO (PMMIO) space mapped to the non-volatile memory unit, and a DRAM space mapped to the volatile memory unit, the PMMIO space including a system main memory local storage (MMLS) area and a memory channel storage area, wherein the DRAM space is partitioned into memory pages, and the MCS space is partitioned into storage blocks.Type: GrantFiled: July 31, 2017Date of Patent: April 2, 2019Assignee: Netlist, Inc.Inventors: Hyun Lee, Sheng Wang
-
Patent number: 10216780Abstract: Embodiments of the present invention relate to a centralized table aging module that efficiently and flexibly utilizes an embedded memory resource, and that enables and facilitates separate network controllers. The centralized table aging module performs aging of tables in parallel using the embedded memory resource. The table aging module performs an age marking process and an age refreshing process. The memory resource includes age mark memory and age mask memory. Age marking is applied to the age mark memory. The age mask memory provides per-entry control granularity regarding the aging of table entries.Type: GrantFiled: August 11, 2017Date of Patent: February 26, 2019Assignee: Cavium, LLCInventors: Weihuang Wang, Gerald Schmidt, Tsahi Daniel, Mohan Balan
-
Patent number: 10198350Abstract: A memory module comprises a volatile memory subsystem configured to coupled to a memory channel in computer system and capable of serving as main memory for the computer system, a non-volatile memory subsystem providing storage for the computer system, and a module controller coupled to the volatile memory subsystem, the non-volatile memory subsystem, and the C/A bus. The module controller reads first data from the non-volatile memory subsystem in response to a Flash access request received via the memory channel, and causes at least a portion of the first data to be written into the volatile memory subsystem in response to a dummy write memory command received via the C/A bus. The module control device includes status registers accessible by the computer system via the memory bus.Type: GrantFiled: May 7, 2015Date of Patent: February 5, 2019Assignee: NETLIST, INC.Inventor: Hyun Lee
-
Patent number: 10198214Abstract: A method of operating a memory system, which includes a memory controller and at least one non-volatile memory, includes storing, in the memory system, temperature-dependent performance level information received from a host disposed external to the memory system, setting an operation performance level of the memory system to a first performance level, operating the memory controller and the at least one non-volatile memory device according to the first performance level, detecting an internal temperature of the memory system, and changing the operation performance level of the memory system to a second performance level that is different from the first performance level. The operation performance level is changed by the memory controller of the memory system, and changing the operation performance level is based on the temperature-dependent performance level information and the detected internal temperature.Type: GrantFiled: January 21, 2015Date of Patent: February 5, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hyun-Seok Kim, Dae-Ho Kim, Yong-Geun Oh, Sung-Jin Moon
-
Patent number: 10175912Abstract: Methods, systems, and apparatus, including an apparatus for transferring data using multiple buffers, including multiple memories and one or more processing units configured to determine buffer memory addresses for a sequence of data elements stored in a first data storage location that are being transferred to a second data storage location. For each group of one or more of the data elements in the sequence, a value of a buffer assignment element that can be switched between multiple values each corresponding to a different one of the memories is identified. A buffer memory address for the group of one or more data elements is determined based on the value of the buffer assignment element. The value of the buffer assignment element is switched prior to determining the buffer memory address for a subsequent group of one or more data elements of the sequence of data elements.Type: GrantFiled: July 5, 2017Date of Patent: January 8, 2019Assignee: Google LLCInventors: Olivier Temam, Harshit Khaitan, Ravi Narayanaswami, Dong Hyuk Woo