Abstract: A semiconductor package includes a first semiconductor die, an encapsulant body of electrically insulating mold compound that encapsulates the first semiconductor die, a plurality of power leads that protrude out of the encapsulant body and form power connections with the first semiconductor die, and a signal lead that protrudes out of the encapsulant body and forms a signal connection with the first semiconductor die, wherein the signal lead comprises a lead adapter retention feature that is configured to form an interlocked connection with a lead adapter that is fitted over an outer end of the signal lead.

Abstract: A device includes a first semiconductor strip and a second semiconductor strip extending longitudinally in a first direction, where the first semiconductor strip and the second semiconductor strip are spaced apart from each other in a second direction. The device also includes a power supply line located between the first semiconductor strip and the second semiconductor strip. A top surface of the power supply line is recessed in comparison to a top surface of the first semiconductor strip. A source feature is disposed on a source region of the first semiconductor strip, and a source contact electrically couples the source feature to the power supply line. The source contact includes a lateral portion contacting a top surface of the source feature, and a vertical portion extending along a sidewall of the source feature towards the power supply line to physically contact the power supply line.

Abstract: A method includes forming a plurality of dielectric layers, forming a plurality of redistribution lines in the plurality of dielectric layers, etching the plurality of dielectric layers to form an opening, filling the opening to form a through-dielectric via penetrating through the plurality of dielectric layers, forming an insulation layer over the through-dielectric via and the plurality of dielectric layers, forming a plurality of bond pads in the dielectric layer, and bonding a device to the insulation layer and a portion of the plurality of bond pads through hybrid bonding.

Abstract: A semiconductor device includes a pair of fin structures on a semiconductor substrate, each including a vertically stacked plurality of channel layers, a dielectric fin extending in parallel to and between the fin structures, and a gate structure on and extending perpendicularly to the fin structures, the gate structure engaging with the plurality of channel layers. The dielectric fin includes a fin bottom and a fin top over the fin bottom. The fin bottom has a top surface extending above a bottom surface of a topmost channel layer. The fin top includes a core and a shell, the core having a first dielectric material, the shell surrounding the core and having a second dielectric material different from the first dielectric material.

Abstract: An electronic product having a first capacitor and a second capacitor, where the electronic product includes a semi-conductor substrate having a bottom electrode region of the first capacitor and a bottom electrode region of the second capacitor; a first dielectric layer having a first thickness arranged above the bottom electrode region of the first capacitor; a second dielectric layer having a second thickness arranged above the bottom electrode region of the second capacitor, the first thickness and the second thickness being different; a top electrode region of the first capacitor arranged above the bottom electrode of the first capacitor and above the first dielectric layer; and a top electrode region of the second capacitor arranged above the bottom electrode of the second capacitor and above the second dielectric layer.

Abstract: A power module includes a base plate, a casing, a substrate unit, a terminal plate, a first resin layer, and a second resin layer. The substrate unit includes a substrate fixed on the base plate, a dam part, a semiconductor chip, a metal member, and a wire. The dam part is formed along an edge of the substrate. The wire includes an electrode plate connection portion, and a chip connection portion. The first resin layer is located inward of the dam part. The chip connection portion and the electrode plate connection portion are located inside the first resin layer. The second resin layer is located on the first resin layer. The upper surface of the metal member is located inside the second resin layer. An elastic modulus of the second resin layer is less than that of the first resin layer.

Abstract: A semiconductor structure and a method for manufacturing same are provided. The semiconductor structure includes: a doped conductive layer, doped with dopant ions; a metal conductive layer, located above the doped conductive layer; a nitrogen-containing dielectric layer, located above the metal conductive layer; a first molybdenum nitride layer, located between the doped conductive layer and the metal conductive layer and configured to be electrically connected to the doped conductive layer and the metal conductive layer; and a second molybdenum nitride layer, located between the metal conductive layer and the nitrogen-containing dielectric layer, where an atomic ratio of nitrogen atoms in the second molybdenum nitride layer is greater than an atomic ratio of nitrogen atoms in the first molybdenum nitride layer.

Abstract: A display device includes a light-emitting element layer including a plurality of light-emitting elements including light-emitting elements configured to emit lights of luminescent colors different from each other, each light-emitting element being provided with a first electrode, a function layer including a light-emitting layer, and a second electrode in this order, the second electrode includes metal nanowires, and the light-emitting element layer is provided with a pixel bank segmenting the metal nanowires at least for each luminescent color.

Abstract: The disclosure provides a thin film transistor (TFT) array substrate provided with a display area and a bending area, including a substrate layer and a functional layer disposed on the substrate layer, wherein the functional layer includes a plurality of insulating layers and a plurality of metal layers. In the bending area, the metal layers include a first metal layer, a second metal layer, and a second gate layer. The first metal layer is disposed on a side end of a filling layer and connects to the second gate layer by a through hole. The second metal layer is disposed on an insulating layer on an outer side of the first metal layer.

Abstract: A display apparatus is disclosed. The display apparatus includes a sensor layer including a plurality of sensors, a pixel layer disposed on the sensor layer and including a plurality of pixel areas and a plurality of pixels in the pixel areas, and an opaque layer disposed between the sensor layer and the pixel layer and including holes corresponding to at least one of the pixel areas.

Abstract: An OLED display panel and an OLED display device are disclosed. In the OLED display panel, a ratio of a width of a side of a first pixel opening adjacent to a pixel electrode layer to a length of a lateral surface of the first pixel opening is greater than a ratio of a width of a side of a second pixel opening adjacent to the pixel electrode layer to a length of a lateral surface of the second pixel opening, such that the nonuniform brightness between a first display area and a second display area is improved or even eliminated.

Abstract: The embodiments of the present application belong to the technical field of semiconductor manufacturing, and relate to a semiconductor structure manufacturing method and a semiconductor structure. The semiconductor structure manufacturing method includes: the substrate is provided with a plurality of active area structures and a plurality of first hole structures arranged at intervals, first bonding pad structures are formed in the first hole structures, and the first bonding pad structures are electrically connected to the active area structures; and second bonding pad structures are formed on the first bonding pad structures, and the second bonding pad structures are connected to the first bonding pad structures, and connected to a capacitor structure.

Abstract: A dual magnetic tunnel junction (DMTJ) is disclosed with a PL1/TB1/free layer/TB2/PL2/capping layer configuration wherein a first tunnel barrier (TB1) has a substantially lower resistance x area (RA1) product than RA2 for an overlying second tunnel barrier (TB2) to provide an acceptable net magnetoresistive ratio (DRR). Moreover, magnetizations in first and second pinned layers, PL1 and PL2, respectively, are aligned antiparallel to enable a lower critical switching current than when in a parallel alignment. An oxide capping layer having a RACAP is formed on PL2 to provide higher PL2 stability. The condition RA1<RA2 and RACAP<RA2 is achieved when TB1 and the oxide capping layer have one or both of a smaller thickness and a lower oxidation state than TB2, are comprised of conductive (metal) channels in a metal oxide or metal oxynitride matrix, or are comprised of a doped metal oxide or doped metal oxynitride layer.

Abstract: A semiconductor memory includes a bit line extending in a first direction, first and second active patterns, which are alternately disposed in the first direction and on the bit line, and each of which includes a horizontal portion and a vertical portion, first word lines disposed on the horizontal portions of the first active patterns to cross the bit line, second word lines disposed on the horizontal portions of the second active patterns to cross the bit line, and an intermediate structure provided in a first gap region between the first and second word lines or in a second gap region between the vertical portions of the first and second active patterns. The first and second active patterns, which are adjacent to each other, may be disposed to be symmetric with respect to each other.

Abstract: The present disclosure relates to a semiconductor structure. The semiconductor structure includes a lower electrode over a substrate, a first capacitor dielectric layer over the lower electrode, an intermediate electrode over the first capacitor dielectric layer, and a second capacitor dielectric layer is over the intermediate electrode. An upper electrode is over the second capacitor dielectric layer. The upper electrode is completely confined over the intermediate electrode. A first protection layer is completely confined over the intermediate electrode. The first protection layer covers opposing sidewalls of the upper electrode and upper surfaces of the intermediate electrode and the upper electrode.

Abstract: A wafer-level package for micro-acoustic devices and a method of manufacture is provided. The package comprises a base wafer with electric device structures. A frame structure is sitting on top of the base wafer enclosing particular device areas for the micro-acoustic devices. A cap wafer provided with a thin polymer coating is bonded to the frame structure to form a closed cavity over each device area and to enclose within the cavity the device structures arranged on the respective device area.

Abstract: The invention provides methods and devices for fabricating printable semiconductor elements and assembling printable semiconductor elements onto substrate surfaces. Methods, devices and device components of the present invention are capable of generating a wide range of flexible electronic and optoelectronic devices and arrays of devices on substrates comprising polymeric materials. The present invention also provides stretchable semiconductor structures and stretchable electronic devices capable of good performance in stretched configurations.

Abstract: A semiconductor device package is described that includes a power consuming device (such as an SOC device). The power consuming device may include one or more current consuming elements. A passive device may be coupled to the power consuming device. The passive device may include a plurality of passive elements formed on a semiconductor substrate. The passive elements may be arranged in an array of structures on the semiconductor substrate. The power consuming device and the passive device may be coupled using one or more terminals. The passive device and power consuming device coupling may be configured in such a way that the power consuming device determines functionally the way the passive device elements will be used.

Abstract: A semiconductor power device includes a substrate; a buffer structure formed on the substrate; a barrier structure formed on the buffer structure; a channel layer formed on the barrier structure; and a barrier layer formed on the channel layer; wherein the barrier structure includes a first functional layer on the buffer structure, a second functional layer formed between the first functional layer and the buffer structure, a first back-barrier layer on the first functional layer, and an interlayer between the first back-barrier layer and the first functional layer; wherein a material of the first back-barrier layer includes Alx1Ga1-x1N, a material of the first functional layer includes Alx2Ga1-x2N, a material of the interlayer includes Alx3Ga1-x3N, a material of the second functional layer includes Alx4Ga1-x4N, wherein 0<x1?1, 0?x2?1, 0?x3?1, 0?x4<1, and x1?x2; and wherein the first functional layer includes a first thickness, the second functional layer includes a second thickness, and the second thic

Abstract: An interface interconnect structure is provided for efficient heat dissipation of a power electronic device. The structure includes a first low temperature solder layer and a second low temperature solder layer, a metal-foam metal composite material is placed between the first low temperature solder layer and the second low temperature solder layer. The metal-foam metal composite material has designability in structure and performance. The thermal conductivity and coefficient of thermal expansion (CTE) of the thermal interface interconnect structure can be configured according to the selected encapsulating materials for a power electronic device, thereby achieving bisynchronous improvement in the heat dissipation efficiency and the CTE matching degree between the encapsulating materials.