Abstract: A display device includes subpixels each comprising an emission area, electrodes which are disposed in the emission area, extend in a first direction, and are spaced apart in a second direction intersecting the first direction, a first insulating layer disposed on the electrodes, a first bank, and light emitting elements. The first bank includes a first bank part disposed on the first insulating layer and surrounding the emission area, and a second bank part connected to the first bank part and disposed in the emission area. The light emitting elements are disposed on the electrodes spaced apart in the second direction. A height of the second bank part of the first bank is lower than a height of the first bank part of the first bank.

Abstract: A light emitting apparatus includes: an electrically insulating base member having, in a top plan view, a first edge, a second edge opposite the first edge, a third edge, and a fourth edge opposite the third edge, wherein the first and second edges of the base member extend in a first direction, and the third and fourth edges of the base member extend in a second direction; first and second electrically conductive pattern portions formed on an upper surface of the base member; at least one light emitting device that is electrically connected to the first and second electrically conductive pattern portions; a transparent member disposed on the at least one light emitting device; and a resin portion that surrounds the transparent member in the top plan view, and that partially covers the first and second electrically conductive pattern portions.

Abstract: A display device and a manufacturing method thereof are provided. A display device includes: a substrate; a first electrode and a second electrode on the substrate, the first electrode and the second electrode being arranged on a same layer to be spaced apart from each other; a first insulating layer on the first electrode and the second electrode; and a light emitting element on the first insulating layer. The first insulating layer includes a groove concave toward the substrate, and the light emitting element is in the groove.

Abstract: The device has a first support element forming a first thermal dissipation surface and carrying a first power component; a second support element forming a second thermal dissipation surface and carrying a second power component, a first contacting element superimposed to the first power component; a second contacting element superimposed to the second power component; a plurality of leads electrically coupled with the power components through the first and/or the second support elements; and a thermally conductive body arranged between the first and the second contacting elements. The first and the second support elements and the first and the second contacting elements are formed by electrically insulating and thermally conductive multilayers.

Abstract: A method for manufacturing a display array includes the following steps: providing a substrate and forming a semiconductor stacked layer on the substrate; forming an insulating layer and a plurality of electrode pads on an outer surface of the semiconductor stacked layer, the insulating layer and the electrode pads directly contacting the semiconductor stacked layer, wherein the insulating layer has a plurality of openings spaced apart from each other; and transferring the semiconductor stacked layer, the insulating layer and the electrode pads from the substrate to a driving backplane, wherein the electrode pads are respectively electrically connected to the driving backplane through the openings of the insulating layer to form a plurality of light emitting regions in the semiconductor stacked layer as the electrode pads and the semiconductor stacked layer are energized by the driving backplane.

Abstract: A method of manufacturing a semiconductor device including: (a) loading a substrate into a process chamber; (b) supplying a processing gas including H2O-containing radicals to the substrate; (c) supplying a gas including a halogen element; (d) supplying a gas including one or both of an oxygen element and a nitrogen element after (c); (e) repeating (c) and (d); and (f) repeating (b) and (e).

Abstract: Methods for tuning effective work functions of gate electrodes in semiconductor devices and semiconductor devices formed by the same are disclosed. In an embodiment, a semiconductor device includes a channel region over a semiconductor substrate; a gate dielectric layer over the channel region; and a gate electrode over the gate dielectric layer, the gate electrode including a first work function metal layer over the gate dielectric layer, the first work function metal layer including aluminum (Al); a first work function tuning layer over the first work function metal layer, the first work function tuning layer including aluminum tungsten (AlW); and a fill material over the first work function tuning layer.

Abstract: A magnetoresistive random access memory (MRAM) structure includes a magnetic tunnel junction (MTJ), and a top electrode which contacts an end of the MTJ. The top electrode includes a top electrode upper portion and a top electrode lower portion. The width of the top electrode upper portion is larger than the width of the top electrode lower portion. A bottom electrode contacts another end of the MTJ. The top electrode, the MTJ and the bottom electrode form an MRAM.

Abstract: A device includes a first semiconductor strip and a second semiconductor strip extending longitudinally in a first direction, where the first semiconductor strip and the second semiconductor strip are spaced apart from each other in a second direction. The device also includes a power supply line located between the first semiconductor strip and the second semiconductor strip. A top surface of the power supply line is recessed in comparison to a top surface of the first semiconductor strip. A source feature is disposed on a source region of the first semiconductor strip, and a source contact electrically couples the source feature to the power supply line. The source contact includes a lateral portion contacting a top surface of the source feature, and a vertical portion extending along a sidewall of the source feature towards the power supply line to physically contact the power supply line.

Abstract: A semiconductor apparatus includes: a first conductor plate; a second conductor plate separated from the first conductor plate; a plurality of semiconductor devices having back surface electrodes connected to the first conductor plate; a relay substrate mounted on the second conductor plate and including a plurality of first relay pads and a second relay pad connected to the plurality of first relay pads; a plurality of metal wires respectively connecting control electrodes of the plurality of semiconductor devices to the plurality of first relay pads; a first conductor block connected to front surface electrodes of the plurality of semiconductor devices; a second conductor block connected to the second relay pad; and a sealing material sealing the first and second conductor plates, the plurality of semiconductor devices, the relay substrate, the metal wire, and the first and second conductor blocks, the sealing material includes a first principal surface and a second principal surface opposed to each other,

Abstract: A power semiconductor apparatus includes a power semiconductor element having low and high potential side electrodes and a sense electrode, high and low potential side conductors electrically connected with the high potential side electrodes, respectively, a sense wiring electrically connected with the sense electrode, and a first metal portion facing the low potential side conductor or the low potential side conductor across the sense wiring. When viewed from an array direction of the sense wiring and the first metal portion, the sense wiring has a facing portion facing the high or low potential side conductor, the first metal portion forms a recess in a part overlapping the facing portion, and a depth of the recess is formed such that a distance between a bottom of the recess and the sense wiring is larger than a distance between the sense wiring and the high or low potential side conductor.

Abstract: A semiconductor device includes a wiring board, a semiconductor chip, and a connecting member provided between a surface of the wiring board and a functional surface of the semiconductor chip. The connecting member extends a distance between the wiring board surface and the functional surface. A sealing material seals a gap space between the wiring board and the semiconductor chip. An electrode is formed at the wiring board surface and arranged outside of an outer periphery of the sealing material. A lateral distance between an outer periphery of the semiconductor chip and the outer periphery of the sealing material is between 0.1 mm and a lateral distance from the outer periphery of the semiconductor chip to the electrode.

Abstract: A display device includes: a substrate having a component area, a main display area, and a peripheral area, the peripheral area surrounding the component area and the main display area; an auxiliary pixel group disposed in the component area and including an auxiliary subpixel pixel electrode, an auxiliary subpixel intermediate layer, and an auxiliary subpixel opposite electrode; and a main pixel group disposed in the main display area and including a main subpixel pixel electrode, a main subpixel intermediate layer, and a main subpixel opposite electrode, wherein the auxiliary subpixel opposite electrode extends in the component area to have a stripe shape and is connected to the main subpixel opposite electrode in the main display area.

Abstract: A power module includes a spacer block, a thermally conductive substrate coupled to one side of the spacer block, and a semiconductor device die coupled to an opposite side of the spacer block. The spacer block includes a solid spacer block and an adjacent flexible spacer block. An inner portion of the device die is coupled to the solid spacer block, and an outer portion of the semiconductor device die is coupled to the adjacent flexible spacer block.

Abstract: A bipolar transistor includes a collector. The collector is formed by: a first portion of the collector which extends under an insulating trench, and a second portion of the collector which crosses through the insulating trench. The first and second portions of the collector are in physical contact.

Abstract: Embodiments described herein generally relate to sub-pixel circuits that may be utilized in a display such as an organic light-emitting diode (OLED) display. The device includes substrate, pixel-defining layer (PDL) structures disposed over the section of the substrate, inorganic or metal overhang structures disposed on an upper surface of the PDL structures, and a plurality of sub-pixels. The PDL structures include a trench disposed in the top surface of the PDL structure. Each sub-pixel includes an anode, an OLED material disposed over and in contact with the anode, and a cathode disposed over the OLED material. The inorganic or metal overhang structures have an overhang extension that extends laterally over the trench. An encapsulation layer is disposed over the cathode and extends under at least a portion of the inorganic or metal overhang structures and along a top surface of the PDL structures.

Abstract: An OLED is disclosed that includes an enhancement layer having optically active metamaterials, or hyperbolic metamaterials, which transfer radiative energy from the organic emissive material to a non-radiative mode, wherein the enhancement layer is disposed over the organic emissive layer opposite from the first electrode, and is positioned no more than a threshold distance away from the organic emissive layer, wherein the organic emissive material has a total non-radiative decay rate constant and a total radiative decay rate constant due to the presence of the enhancement layer, and the threshold distance is where the total non-radiative decay rate constant is equal to the total radiative decay rate constant; and an outcoupling layer disposed over the enhancement layer, wherein the outcoupling layer scatters radiative energy from the enhancement layer to free space.

Abstract: A method for forming a direct hybrid bond and a device resulting from a direct hybrid bond including a first substrate having a first set of metallic bonding pads, preferably connected to a device or circuit, capped by a conductive barrier, and having a first non-metallic region adjacent to the metallic bonding pads on the first substrate, a second substrate having a second set of metallic bonding pads capped by a second conductive barrier, aligned with the first set of metallic bonding pads, preferably connected to a device or circuit, and having a second non-metallic region adjacent to the metallic bonding pads on the second substrate, and a contact-bonded interface between the first and second set of metallic bonding pads capped by conductive barriers formed by contact bonding of the first non-metallic region to the second non-metallic region.

Abstract: A light sensing device includes a substrate, a gate electrode, a semiconductor layer, a dielectric layer, a first source/drain electrode, a second source/drain electrode, and a reset electrode. The gate electrode is over the substrate. The semiconductor layer is over the substrate and at least partially overlapping the gate electrode. The dielectric layer spaces the gate electrode from the semiconductor layer. The first source/drain electrode and the second source/drain electrode are respectively connected to the semiconductor layer. The semiconductor layer has a first region and a second region between the first source/drain electrode and the second source/drain electrode, the first region overlaps the gate electrode, and the second region does not overlap the gate electrode. The reset electrode is in contact with the semiconductor layer.

Abstract: Various embodiments include methods of fabricating an array of self-aligned vertical solid state devices and integrating the devices to a system substrate. The method of fabricating a self-aligned vertical solid state device comprising: providing a semiconductor substrate, depositing a plurality of device layers on the semiconductor substrate, depositing an ohmic contact layer on an upper surface of one of the plurality of device layers, wherein the device layers comprises an active layer and a doped conductive layer, forming a patterned thick conductive layer on the ohmic contact layer; and selectively etching down the doped conductive layer that does not substantially etch the active layer.