Abstract: The present disclosure relates to a display device, and more particularly, to a high-performance display device by which high transmittance is secured and efficiency is enhanced in a manner of using a mixture of an organic matter and an alkaline earth metal as a cathode and facilitating patterning.

Abstract: The present disclosure provides a semiconductor device and a method of forming the same. In an embodiment, the semiconductor device includes a fin extending from a substrate, a gate structure over the channel region, a first spacer extending along a sidewall of the lower portion of the gate structure, and a second spacer extending along a sidewall of the upper portion of the gate structure. The fin includes a channel region and a source/drain (S/D) region adjacent to the channel region. The gate structure includes an upper portion and a lower portion. The second spacer is disposed on a top surface of the first spacer. The first spacer is formed of a first dielectric material and the second spacer is formed of a second dielectric material different from the first dielectric material.

Abstract: The present technology provides a semiconductor device and a method of manufacturing the same. The semiconductor device includes a channel structure, insulating structures surrounding the channel structure and stacked to be spaced apart from each other, interlayer insulating films surrounding the insulating structures, respectively, and a gate electrode extending from between the interlayer insulating films to between the insulating structures and surrounding the channel structure. The insulating structures may include protrusion portions extending to cover edges of the interlayer insulating films facing the channel structure, and the gate electrode may extend between the protrusion portions which are adjacent to each other.

Abstract: To provide a display device having a reduced non-display area, the display device including: a substrate including a display area, the display area including a first area and a second area; a first pixel electrode in the first area, and a second pixel electrode in the second area; a pixel-defining layer on the substrate and including a first opening and a second opening, the first opening exposing at least a portion of the first pixel electrode, and the second opening exposing at least a portion of the second pixel electrode; a first intermediate layer on the at least a portion of the first pixel electrode, and a second intermediate layer on the at least a portion of the second pixel electrode; a first opposite electrode on the first intermediate layer; and a second opposite electrode on the first opposite electrode and the second intermediate layer.

Abstract: Disclosed herein are techniques for reducing the pitch between light-emitting diodes (LEDs) in an array of LEDs. According to an aspect of the invention, a method includes forming a plurality of stacks of layers on a surface of a semiconductor, with a p contact at an interface between each stack and a p-type layer of the semiconductor. The semiconductor is etched to form a plurality of mesa shapes corresponding to the plurality of stacks. A dielectric is formed on at least a portion of each mesa shape and at least a portion of each stack. A reflector is formed on at least a portion of the dielectric and at least a portion of the semiconductor to provide an n contact at an interface between the reflector and an n-type layer of the semiconductor. The reflector is physically separated from the p contact for each stack.

Abstract: An optoelectronic component and a manufacturing method are disclosed. In an embodiment an optoelectronic component includes an optoelectronic semiconductor chip, a housing having a top side and two protrusions on the top side projecting beyond the top side and a transparent structure, wherein the optoelectronic semiconductor chip is arranged between the protrusions, and wherein the transparent structure is at least partially arranged on the top side of the housing between the protrusions and partially above the optoelectronic semiconductor chip.

Abstract: A method of manufacturing a semiconductor device includes embedding electrodes in insulating layers exposed to the joint surfaces of a first substrate and a second substrate, subjecting the joint surfaces of the first substrate and the second substrate to chemical mechanical polishing, to form the electrodes into recesses recessed as compared to the insulating layer, laminating insulating films of a uniform thickness over the entire joint surfaces, forming an opening by etching in at least part of the insulating films covering the electrodes of the first substrate and the second substrate, causing the corresponding electrodes to face each other and joining the joint surfaces of the first substrate and the second substrate to each other, heating the first substrate and the second substrate joined to each other, causing the electrode material to expand and project through the openings, and joining the corresponding electrodes to each other.

Abstract: A semiconductor device and a method of fabricating a semiconductor device, the device including a semiconductor substrate that includes a trench defining an active region; a buried dielectric pattern in the trench; a silicon oxide layer between the buried dielectric pattern and an inner wall of the trench; and a polycrystalline silicon layer between the silicon oxide layer and the inner wall of the trench, wherein the polycrystalline silicon layer has a first surface in contact with the semiconductor substrate and a second surface in contact with the silicon oxide layer, and wherein the second surface includes a plurality of silicon grains that are uniformly distributed.

Abstract: An opto-electronic device includes: a first electrode; an organic layer disposed over the first electrode; a nucleation promoting coating disposed over the organic layer; a nucleation inhibiting coating covering a first region of the opto-electronic device; and a conductive coating covering a second region of the opto-electronic device.

Abstract: A semiconductor device of embodiments includes an insulating substrate, a first main terminal, a second main terminal, an output terminal, a first metal layer connected to the first main terminal, a second metal layer connected to the second main terminal, a third metal layer disposed between the first metal layer and the second metal layer and connected to the output terminal, a first semiconductor chip and a second semiconductor chip provided on the first metal layer, a third semiconductor chip and a fourth semiconductor chip provided on the third metal layer, and a conductive member on the second metal layer. Then, the second metal layer includes a slit. The conductive member is provided between the end portion of the second metal layer and the slit.

Abstract: A display panel includes an emitting part including a light emitting element and a transmitting part adjacent to the emitting part and including a low adhesion part including a carbon compound. The low adhesion pattern includes fluorine (F).

Abstract: [Object] It is possible to further improve reliability. [Solution] There is provided a display device including: a pixel unit which is configured with a plurality of pixel circuits arranged in a matrix, each of the pixel circuits including a light emitting element and a driving circuit for driving the light emitting element; scanning lines which are interconnections connected to the respective pixel circuits and are provided to extend in a first direction and correspond to respective rows of a plurality of the pixel circuits; and signal lines which are interconnections connected to the respective pixel circuits and are provided to extend in a second direction orthogonal to the first direction and correspond to respective columns of a plurality of the pixel circuits. One of the scanning lines and the signal lines, provided for the one pixel circuit, which is larger in number is positioned in a lower-level interconnection layer.

Abstract: A display substrate, a manufacturing method thereof, and a display device are provided. The display substrate includes: a base substrate; an anode structure, disposed on the base substrate; a light emitting layer, disposed on a side of the anode structure away from the base substrate; and a cathode layer, disposed on a side of the light emitting layer away from the base substrate, the anode structure includes a reflective layer and an inorganic layer disposed on a side of the reflective layer away from the base substrate, the cathode layer includes a transflective layer, and the inorganic layer is configured to adjust a distance between the reflective layer and the transflective layer.

Abstract: A method of manufacturing a vertical memory device includes forming a first sacrificial layer on a substrate, the first sacrificial layer including a first insulating material, forming a mold including an insulation layer and a second sacrificial layer alternately and repeatedly stacked on the first sacrificial layer, the insulation layer and the second sacrificial layer including second and third insulating materials, respectively, different from the first insulating material, forming a channel through the mold and the first sacrificial layer, forming an opening through the mold and the first sacrificial layer to expose an upper surface of the substrate, removing the first sacrificial layer through the opening to form a first gap, forming a channel connecting pattern to fill the first gap, and replacing the second sacrificial layer with a gate electrode.

Abstract: A semiconductor device with high heat dissipation efficiency includes a base structure, a semiconductor chip, a heat dissipating structure, and a package body. The semiconductor chip is disposed on the base structure and has a first surface distant from the base structure. The heat dissipating structure includes a buffer layer and a first heat spreader. The buffer layer is disposed on the first surface of the semiconductor chip and a coverage rate thereof on the first surface is at least 10%. The first heat spreader is disposed on the buffer layer and bonded to the first surface of the semiconductor chip through the buffer layer. The package body encloses the semiconductor chip and the heat dissipating structure, and the package body and the buffer layer have the same heat curing temperature.

Abstract: A display substrate has a display area and a peripheral area. The display substrate includes a base substrate; an insulating layer on the base substrate and in at least the peripheral area; a plurality of light emitting elements on the base substrate and in the display area; an encapsulating layer on a side of the plurality of light emitting elements distal to the base substrate to encapsulate the plurality of light emitting elements; and a dam layer on a side of the insulating layer distal to the base substrate. The encapsulating layer includes a first inorganic encapsulating sublayer extending from the display area into the peripheral area. The display substrate has a groove extending into the first insulating layer in the peripheral area, and substantially surrounding the display area. The first inorganic encapsulating sublayer extends into at least a portion of the groove.

Abstract: A semiconductor device in which occurrence of peeling between a filling member and a metal terminal is suppressed is obtained. The semiconductor device includes: an insulating substrate having a front surface and a back surface, and having a semiconductor element joined to the front surface; a base plate joined to the back surface of insulating substrate; a case member surrounding insulating substrate; a filling member having an upper surface, covering insulating substrate, and filling a region surrounded by base plate and case member; and a metal member having a plate shape that leans toward an upper surface side of filling member inside filling member, has one end joined to the front surface of insulating substrate and another end separated from an inner wall of case member, and is exposed from the upper surface of filling member.

Abstract: The present publication discloses a micromechanical structure including at least one active element, the micromechanical structure comprising a substrate, at least one layer formed on the substrate forming the at least part of the at least one active element, mechanical contact areas through which the micromechanical structure can be connected to other structures like printed circuit boards and like. In accordance with the invention the micromechanical structure includes weakenings like trenches around the mechanical contact areas for eliminating the thermal mismatch between the active element of the micromechanical structure and the other structures.

Abstract: Photonic devices and methods having an increased quantum effect length are provided. In some embodiments, a photonic device includes a substrate having a first surface. A cavity extends into the substrate from the first surface to a second surface. A semiconductor layer is disposed on the second surface in the cavity of the substrate, and a cover layer is disposed on the semiconductor layer. The semiconductor layer is configured to receive incident radiation through the substrate and to totally internally reflect the radiation at an interface between the semiconductor layer and the cover layer.

Abstract: A semiconductor nanostructure and an epitaxial semiconductor material portion are formed on a front surface of a substrate, and a planarization dielectric layer is formed thereabove. Recess cavities are formed to expose a first active region and the epitaxial semiconductor material portion. A metallic cap structure is formed on the first active region, and a sacrificial metallic material portion is formed on the epitaxial semiconductor material portion. A connector via cavity is formed by anisotropically etching the sacrificial metallic material portion and an underlying portion of the epitaxial semiconductor material portion while the metallic cap structure is masked with a hard mask layer. A connector via structure is formed in the connector via cavity. Front-side metal interconnect structures are formed on the connector via structure and the metallic cap structure, and a backside via structure is formed through the substrate on the connector via structure.