Patents Examined by Minh Loan Tran
  • Patent number: 10535777
    Abstract: Nanoribbon Field Effect Transistors (FETs) offer significant performance increases and energy consumption decreases relative to traditional metal oxide semiconductor (MOS) transistors. Various embodiments are directed to nanoribbon FETs having III-N channel materials and methods of forming the same. An integrated circuit (IC) structure can include a first layer on a substrate. The first layer can include a group III semiconductor material and nitrogen. The IC structure can include recessed source and drain regions formed on the first layer using planar epitaxy. The IC structure can include a second layer between the recessed source and drain. A gate wraps around at least part of the second layer.
    Type: Grant
    Filed: March 29, 2018
    Date of Patent: January 14, 2020
    Assignee: Intel Corporation
    Inventors: Marko Radosavljevic, Han Wui Then, Sansaptak Dasgupta
  • Patent number: 10536761
    Abstract: A portable electronic device may have acoustic ports such as microphone and speaker ports. Acoustic devices such as microphones and speakers may be associated with the acoustic ports. An acoustic port may have an opening between an interior and exterior of the portable electronic device. The opening may be covered by a metal mesh. An acoustic fabric may be interposed between the metal mesh and the opening. The opening may be formed from a hole in a glass member having outer and inner chamfers. A microphone boot may be provided that forms front and rear radial seals with a housing of the device and a microphone unit respectively. The microphone boot may also form multiple face seals with the microphone unit. A speaker for the speaker port may be enclosed in a sealed speaker enclosure. The speaker enclosure may have a pressure-equalizing vent slit covered with an acoustic mesh.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: January 14, 2020
    Assignee: Apple Inc.
    Inventors: Adam Mittleman, Richard P. Howarth, Chad Seguin
  • Patent number: 10535782
    Abstract: A bidirectional Zener diode of the present invention includes a semiconductor substrate of a first conductivity type, a first electrode and a second electrode which are defined on the semiconductor substrate, and a plurality of diffusion regions of a second conductivity type, which are defined at intervals from one another on a surface portion of the semiconductor substrate, to define p-n junctions with the semiconductor substrate, and the plurality of diffusion regions include diode regions which are electrically connected to the first electrode and the second electrode, and pseudo-diode regions which are electrically isolated from the first electrode and the second electrode.
    Type: Grant
    Filed: March 14, 2019
    Date of Patent: January 14, 2020
    Assignee: ROHM CO., LTD.
    Inventor: Hiroki Yamamoto
  • Patent number: 10522662
    Abstract: A method of forming a semiconductor device structure is provided. The method includes forming a fin structure protruding from a substrate and forming a first liner layer to cover a top surface and a sidewall of the fin structure. The first liner layer is patterned by performing a wet etching process, so as to remain a portion of the first liner layer that covers the top surface of the fin structure and a portion of the sidewall of the fin structure. The remained portion of the first liner layer is used as an etch mask to remove a portion of the fin structure from the sidewall of the fin structure, so as to form a lateral recess in the fin structure.
    Type: Grant
    Filed: June 22, 2018
    Date of Patent: December 31, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-Neng Lin, Shian-Wei Mao
  • Patent number: 10510613
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a contact over an active gate structure and methods of manufacture. The structure includes: an active gate structure composed of conductive material located between sidewall material; an upper sidewall material above the sidewall material, the upper sidewall material being different material than the sidewall material; and a contact structure in electrical contact with the conductive material of the active gate structure. The contact structure is located between the sidewall material and between the upper sidewall material.
    Type: Grant
    Filed: January 23, 2018
    Date of Patent: December 17, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Jiehui Shu, Xusheng Wu, Haigou Huang, John H. Zhang, Pei Liu, Laertis Economikos
  • Patent number: 10510926
    Abstract: An embodiment relates to an ultraviolet light-emitting device, a method for manufacturing an ultraviolet light-emitting device, a light-emitting device package and an illumination apparatus. The ultraviolet light-emitting device includes a first conductive-type semiconductor layer; an active layer comprising a plurality of quantum walls and a plurality of quantum wells and disposed on the first conductive-type semiconductor layer; a second conductive-type first semiconductor layer disposed on the active layer; an electron blocking layer disposed between the active layer and the second conductive-type first semiconductor layer; and a second conductive-type second semiconductor layer disposed between the last quantum wall of the active layer and the electron blocking layer, wherein the second conductive-type second semiconductor layer includes a p-type Alx1Ga1-x1N layer (0?x1?1) and a p-type InyAlx2Ga1-y-x2N layer (0?x2?1, 0?y?1, 0?x2+y?1).
    Type: Grant
    Filed: July 25, 2016
    Date of Patent: December 17, 2019
    Assignee: LG INNOTEK CO., LTD.
    Inventors: Chan Keun Park, Sul Hee Kim
  • Patent number: 10510605
    Abstract: An embodiment method includes providing a wafer including a first integrated circuit die, a second integrated circuit die, and a scribe line region between the first integrated circuit die and the second integrated circuit die. The method further includes forming a kerf in the scribe line region and after forming the kerf, using a mechanical sawing process to fully separate the first integrated circuit die from the second integrated circuit die. The kerf extends through a plurality of dielectric layers into a semiconductor substrate.
    Type: Grant
    Filed: July 24, 2018
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Fu-Chen Chang, Cheng-Lin Huang, Wen-Ming Chen
  • Patent number: 10510844
    Abstract: Provided is a semiconductor device includes a first semiconductor layer provided on a first main surface of the semiconductor substrate, a plurality of first semiconductor regions selectively provided at upper layer parts of the semiconductor layer, a second semiconductor region selectively provided at an upper layer part of each of the first semiconductor regions, a second semiconductor layer provided on a JFET region corresponding to the first semiconductor layer between the first semiconductor regions, and configured to cover at least a part of the JFET region, a gate insulating film covering the first semiconductor regions and the second semiconductor layer, a third semiconductor layer provided on the second semiconductor layer, a gate electrode provided on the gate insulating film, an interlayer insulating film covering the gate electrode and the gate insulating film, a contact hole penetrating through the gate insulating film and the interlayer insulating film, at least the second semiconductor region b
    Type: Grant
    Filed: June 22, 2017
    Date of Patent: December 17, 2019
    Assignee: Mitsubishi Electric Corporation
    Inventors: Munetaka Noguchi, Toshiaki Iwamatsu
  • Patent number: 10505006
    Abstract: A method includes depositing a silicon layer over a first oxide layer that overlays a first silicon substrate. The method further includes depositing a second oxide layer over the silicon layer to form a composite substrate. The composite substrate is bonded to a second silicon substrate to form a micro-electro-mechanical system (MEMS) substrate. Holes within the second silicon substrate are formed by reaching the second oxide layer of the composite substrate. The method further includes removing a portion of the second oxide layer through the holes to release MEMS features. The MEMS substrate may be bonded to a CMOS substrate.
    Type: Grant
    Filed: July 24, 2018
    Date of Patent: December 10, 2019
    Assignee: InvenSense, Inc.
    Inventors: Bongsang Kim, Jongwoo Shin, Joseph Seeger, Logeeswaran Veerayah Jayaraman, Houri Johari-Galle
  • Patent number: 10497816
    Abstract: The semiconductor device of the present invention includes a first conductivity type semiconductor layer made of SiC, a Schottky electrode formed to come into contact with at least a portion of a surface of the semiconductor layer, a field region surrounding the Schottky electrode, an annular trench formed on the field region and surrounding the Schottky electrode and a second conductivity type layer formed under a portion of the Schottky electrode outside at least the portion of the surface of the semiconductor layer.
    Type: Grant
    Filed: July 25, 2018
    Date of Patent: December 3, 2019
    Assignee: ROHM CO., LTD.
    Inventors: Masatoshi Aketa, Yuta Yokotsuji
  • Patent number: 10497626
    Abstract: A method of forming a semiconductor device includes forming a gate dielectric layer on a substrate; forming a barrier layer over the gate dielectric layer; treating the barrier layer to roughen an outer surface of the barrier layer, resulting in a treated barrier layer; and forming a metal layer over the treated barrier layer.
    Type: Grant
    Filed: August 13, 2018
    Date of Patent: December 3, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yen-Ting Chen, Chia-Lin Hsu
  • Patent number: 10497775
    Abstract: Decoupling structures are provided. The decoupling structures may include first conductive patterns, second conductive patterns and a unitary supporting structure that structurally supports the first conductive patterns and the second conductive patterns. The decoupling structures may also include a common electrode disposed between ones of the first conductive patterns and between ones of the second conductive patterns. The first conductive patterns and the common electrode are electrodes of a first capacitor, and the second conductive patterns and the common electrode are electrodes of a second capacitor. The unitary supporting structure may include openings when viewed from a plan perspective. The first conductive patterns and the second conductive patterns are horizontally spaced apart from each other with a separation region therebetween, and none of the openings extend into the separation region.
    Type: Grant
    Filed: February 5, 2019
    Date of Patent: December 3, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong-Min Lee, Jongryul Jun, Eun A Kim, Jung-Bum Lim
  • Patent number: 10497655
    Abstract: A packaged semiconductor device includes an insulating material forming a side surface of the packaged semiconductor device. An integrated-circuit chip is embedded in the insulating material and includes a communication circuit. A wiring system is embedded in the insulating material and electrically couples the integrated-circuit chip with a plurality of package contact elements. A first communication pad is formed in the side surface and is operatively coupled to the communication circuit to enable signal exchange through the first communication pad.
    Type: Grant
    Filed: February 6, 2018
    Date of Patent: December 3, 2019
    Assignee: STMicroelectronics S.r.l.
    Inventors: Federico Giovanni Ziglioli, Alberto Pagani
  • Patent number: 10497624
    Abstract: A method of manufacturing a semiconductor device includes forming a first semiconductor layer having a first composition over a semiconductor substrate, and forming a second semiconductor layer having a second composition over the first semiconductor layer. Another first semiconductor layer having the first composition is formed over the second semiconductor layer. A third semiconductor layer having a third composition is formed over the another first semiconductor layer. The first semiconductor layers, second semiconductor layer, and third semiconductor layer are patterned to form a fin structure. A portion of the third semiconductor layer is removed thereby forming a nanowire comprising the second semiconductor layer, and a conductive material is formed surrounding the nanowire. The first semiconductor layers, second semiconductor layer, and third semiconductor layer include different materials.
    Type: Grant
    Filed: March 29, 2018
    Date of Patent: December 3, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shao-Ming Yu, Tung Ying Lee, Wei-Sheng Yun, Fu-Hsiang Yang
  • Patent number: 10497749
    Abstract: An electronic device is provided to comprise a semiconductor memory unit that comprises: a substrate including active regions, which are extended in a second direction and disposed from each other in a first direction; a plurality of gates extended in the first direction and across with the active regions; a lower contact disposed in both sides of gates and coupling the active regions in the first direction; an upper contact of the lower contact overlapping with the active region out of the active regions in a side of each gate, and overlapping with the active regions in the other side of each gate; and first and second interconnection lines coupled to the upper contact, extended in the second direction, and being alternately disposed from each other in the first direction, wherein the upper contact of a side of the gates has a zigzag shape in a first oblique direction.
    Type: Grant
    Filed: September 25, 2017
    Date of Patent: December 3, 2019
    Assignee: SK hynix Inc.
    Inventor: Hee-Sung Kang
  • Patent number: 10490588
    Abstract: Various embodiments of the present technology may comprise a method and apparatus for an image sensor with a thermal equalizer for distributing heat. The method and apparatus may comprise a thermal equalizer disposed between a sensor die and a circuit die to prevent uneven heating of the pixels in the sensor die. The method and apparatus may comprise a thermal equalizer integrated within the circuit die.
    Type: Grant
    Filed: September 16, 2016
    Date of Patent: November 26, 2019
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Larry Duane Kinsman, Swarnal Borthakur, Marc Allen Sulfridge
  • Patent number: 10490686
    Abstract: A photoconductor for emitting and/or receiving electromagnetic waves is provided. The photoconductor comprises a material region comprising a first and a second section, wherein the second section provides a higher density of charge carrier trapping centers and/or recombination centers than the first section, and a confinement generating a sub-band structure of the charge carrier energy states in the material region. The first and the second section are arranged and configured in such a manner that a maximum of the carrier probability density of the sub-band ground state is located in one of these sections and a maximum of the carrier probability density of an excited sub-band state is located in the respective other section.
    Type: Grant
    Filed: February 25, 2014
    Date of Patent: November 26, 2019
    Assignee: FRAUNHOFER-GESELLSCHAFT ZUR FÖRDERUNG DER ANGEWANDTEN FORSCHUNG E.V.
    Inventors: Roman Dietz, Björn Globisch, Thorsten Göbel, W. Ted Masselink, Mykhaylo Semtsiv
  • Patent number: 10490719
    Abstract: Light emitting die (300) comprising a plurality of light emitting elements (310A, 310B), each having a pair of bond pads (N1,P1 and N2,P2), wherein at least two diagonally opposite bond pads of adjacent light emitting elements on a die have their facing corners truncated (330) to enable a direct diagonal coupling of a complementary pair of diagonally opposite bond pads when the die is monted on a substrate on which an interconnection pattern is formed. By enabling diagonal as well as lateral coupling of the bond pads of multiple light emitting elements of a die, the multiple light emitting elements may be arranged in a variety of series and/or parallel configurations, thereby facilitating the use of the same die at different nominal operating voltages with a single interconnect layer on the substrate upon which the die is mounted.
    Type: Grant
    Filed: October 19, 2016
    Date of Patent: November 26, 2019
    Assignee: Lumileds Holding B.V.
    Inventors: Wen Yu, Oleg B. Shchekin, Franklin Wall, Kuochou Tai, Mohiuddin Mala, Robert Zona, Jeffrey Kmetec, Alexander Nickel
  • Patent number: 10468432
    Abstract: A method is presented for incorporating a metal-ferroelectric-metal (MFM) structure in a cross-bar array in back end of the line (BEOL) processing. The method includes forming a first electrode, forming a ferroelectric layer in direct contact with the first electrode, forming a second electrode in direct contact with the ferroelectric layer, such that the first electrode and the ferroelectric layer are perpendicular to the second electrode to form the cross-bar array, and biasing the second electrode to adjust domain wall movement within the ferroelectric layer.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: November 5, 2019
    Assignee: International Business Machines Corporation
    Inventors: Jin Ping Han, Ramachandran Muralidhar, Paul M. Solomon, Dennis M. Newns, Martin M. Frank
  • Patent number: 10468625
    Abstract: A novel light-emitting device that is highly convenient or reliable is provided. A method for manufacturing a novel light-emitting device that is highly convenient or reliable is also provided. Further, a novel light-emitting device, a method for manufacturing a novel light-emitting device, or a novel device is provided. The present inventor has conceived the structure in which a first insulating film and a light-emitting element are provided between a first support having certain isotropy and a second support.
    Type: Grant
    Filed: October 5, 2016
    Date of Patent: November 5, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Tatsuya Sakuishi