Patents Examined by Minh Loan Tran
  • Patent number: 10361162
    Abstract: Methodologies and an apparatus for enabling magnetic shielding of stand alone MRAM are provided. Embodiments include placing MRAM dies and logic dies on a first surface of a mold frame; forming a top magnetic shield over top and side surfaces of the MRAM dies; forming a mold cover over the MRAM dies, FinFET dies and mold frame; removing the mold frame to expose a bottom surface of the MRAM dies and FinFET dies; and forming a bottom magnetic shield over the bottom surface of the MRAM dies.
    Type: Grant
    Filed: January 23, 2018
    Date of Patent: July 23, 2019
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Bharat Bhushan, Juan Boon Tan, Boo Yang Jung, Wanbing Yi, Danny Pak-Chum Shum
  • Patent number: 10355193
    Abstract: A quantum bit (qubit) flip chip assembly may be formed when a qubit it formed on a first chip and an optically transmissive path is formed on a second chip. The two chips may be bonded using solder bumps. The optically transmissive path may provide optical access to the qubit on the first chip.
    Type: Grant
    Filed: November 28, 2017
    Date of Patent: July 16, 2019
    Assignee: International Business Machines Corporation
    Inventors: Sami Rosenblatt, Jason S. Orcutt, Martin O. Sandberg, Markus Brink, Vivekananda P. Adiga, Nicholas T. Bronn
  • Patent number: 10355034
    Abstract: The present disclosure provides a low-temperature polycrystalline silicon array substrate which includes a substrate, a groove disposed on the substrate, a buffer layer disposed on the substrate, and a polycrystalline silicon active layer disposed on the buffer layer, the groove is located at a channel of a thin film transistor, and the buffer layer covers the groove to form an air layer in the groove. The present disclosure further provides a manufacturing method of a low-temperature polycrystalline silicon array substrate, mainly including: manufacturing a groove at a channel of a thin film transistor on a substrate; depositing a metal sacrificial layer on the substrate, and etching the metal sacrificial layer except the groove through an etching process; sequentially forming a buffer layer and an amorphous silicon layer on the substrate; and removing the metal sacrificial layer in the groove to form an air layer in the groove.
    Type: Grant
    Filed: October 13, 2017
    Date of Patent: July 16, 2019
    Assignee: Wuhan China Star Optoelectronics Technology Co., Ltd.
    Inventor: Tao Wang
  • Patent number: 10340425
    Abstract: A light emitting diode including a light blocking layer is disclosed. The light emitting diode includes: a substrate including an upper surface and side surfaces; a semiconductor stack disposed under the substrate and including a first conductivity type semiconductor layer, a second conductivity type semiconductor layer, and an active layer interposed between the first conductivity type semiconductor layer and the second conductivity type semiconductor layer; and a light blocking layer covering the upper surface and the side surfaces of the substrate to define a light emitting surface on the upper surface of the substrate. The size of a light emitting surface of the light emitting diode can be easily controlled using the light blocking layer.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: July 2, 2019
    Assignee: Seoul Viosys Co., Ltd.
    Inventors: Jong Min Jang, Chang Yeon Kim, Jae Hee Lim
  • Patent number: 10333013
    Abstract: A photoelectric semiconductor nanowire device and a method for manufacturing the same. The photoelectric semiconductor nanowire device includes a semiconductor nanowire doped with a dopant of a first conductivity type and including crystal semiconductor segments which include at least one porous semiconductor segment and are connected to opposite ends of the porous semiconductor segment. A first electrode and a second electrode respectively are disposed in the crystal semiconductor segments around the porous semiconductor segment to provide an electrical connection. The crystal semiconductor segment includes a crystal semiconductor, and the porous semiconductor segment includes a porous semiconductor. The semiconductor nanowire provides a current according to the intensity of an external light when the external light is irradiated to the porous semiconductor segment.
    Type: Grant
    Filed: April 24, 2018
    Date of Patent: June 25, 2019
    Assignee: Korea University Research and Business Foundation
    Inventors: Hu-Cheol Lee, Hong-Gyu Park, Min-Soo Hwang, Jungkil Kim
  • Patent number: 10332998
    Abstract: Transistors including doped heteroepitaxial III-N source/drain crystals. In embodiments, transistors including a group IV or group III-V channel crystal employ n+ doped III-N source/drain structures on either side of a gate stack. Lateral tensile strain of the channel crystal may result from lattice mismatch between the channel crystal and the III-N source/drain crystals. In embodiments, an amorphous material is employed to limit growth of III-N material to only a single channel crystal facet, allowing a high quality monocrystalline source/drain to form that is capable of sustaining significant stress. In some embodiments, an n+ III-N source/drain crystal is grown on a (110) or (111) surface of a silicon channel crystal fabricated into a fin structure to form a tensile strained NMOS finFET.
    Type: Grant
    Filed: December 24, 2015
    Date of Patent: June 25, 2019
    Assignee: Intel Corporation
    Inventors: Sansaptak Dasgupta, Han Wui Then, Marko Radosavljevic
  • Patent number: 10332749
    Abstract: A method includes forming a plurality of first core features and one frame feature encircling the first core features. The first core features extend along a first direction and are arranged along a second direction perpendicular to the first direction, and each of the first core features is spaced apart from the frame feature by a first gap along the first direction. The method also includes forming a spacer layer filling the first gaps and forming a plurality of individual recesses entirely separated from each other. The method also includes forming a plurality of second core features in the individual recesses, wherein the second core features are entirely separated from each other and are spaced apart from the frame feature by the spacer layer. The method then removes the spacer layer to form a plurality of openings between the first core features, the second core features and the frame feature.
    Type: Grant
    Filed: November 9, 2018
    Date of Patent: June 25, 2019
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Chiang-Lin Shih, Shing-Yih Shih
  • Patent number: 10326055
    Abstract: A light emitting device includes a first conductive-type layer, an active layer, and a second conductive-type layer; a first electrode on a first surface of the first conductive-type layer, the first electrode having a multilayer structure including Pt; a first pad on the first electrode, the first pad disposed on an edge of the first surface of the first conductive-type layer in a cross-sectional view; and a second electrode and a second pad on a second surface of the second conductive-type layer, the second electrode having a metal layer including Ti. In addition, the first pad include Au, further the second electrode is unitary with the second pad, and also the second electrode includes a reflective layer configured to reflect light from the active layer.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: June 18, 2019
    Assignee: LG INNOTEK CO., LTD.
    Inventor: Myung Cheol Yoo
  • Patent number: 10325919
    Abstract: Various embodiments of the present application are directed to a method for forming an integrated circuit (IC), and the associated integrated circuit. In some embodiments, a stack of gate dielectric precursor layers is formed on a plurality of logic sub-region and is then selectively removed from at least two logic sub-regions. Then, a gate dielectric precursor layer is formed, and a plasma treatment process and an annealing process are subsequently performed. The gate dielectric precursor layer is then selectively removed from a low-voltage logic sub-region, but not a high-voltage logic sub-region. By removing the stack of gate dielectric precursor layers from the low-voltage logic sub-region prior to performing the plasma treatment process and the annealing process, less gate dielectric precursor material is treated, annealed, and removed from the low-voltage logic sub-region. Thus, the resulting residues are reduced, and the defects introduced by the residues are also reduced or eliminated.
    Type: Grant
    Filed: June 22, 2018
    Date of Patent: June 18, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Li-Feng Teng, Wei Cheng Wu
  • Patent number: 10325980
    Abstract: Power devices using refilled trenches with permanent charge at or near their sidewalls. These trenches extend vertically into a drift region.
    Type: Grant
    Filed: June 21, 2018
    Date of Patent: June 18, 2019
    Assignee: MaxPower Semiconductor Inc.
    Inventors: Mohamed N. Darwish, Jun Zeng, Richard A. Blanchard
  • Patent number: 10312377
    Abstract: Transistors including one or more semiconductor fins formed on a substrate. The one or more semiconductor fins are thinner in a channel region than in source and drain regions and have rounded corners. There is a gate stack on the channel region of the one or more semiconductor fins.
    Type: Grant
    Filed: October 12, 2016
    Date of Patent: June 4, 2019
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, RENESAS ELECTRONICS CORPORATION
    Inventors: Veeraraghavan S. Basker, Shogo Mochizuki, Tenko Yamashita, Chun-Chen Yeh
  • Patent number: 10312350
    Abstract: A method for manufacturing a semiconductor device includes forming a stacked configuration of a plurality of silicon germanium layers and a plurality of silicon layers on a semiconductor substrate, wherein the stacked configuration comprises a repeating arrangement of a silicon layer stacked on a silicon germanium layer, patterning the stacked configuration into a plurality of patterned stacks spaced apart from each other, and etching exposed sides of the plurality of silicon germanium layers to remove portions of the silicon germanium layers from lateral sides of each of the plurality of silicon germanium layers, wherein a concentration of germanium is varied between each of the plurality of silicon germanium layers to compensate for variations in etching rates between the plurality of silicon germanium layers to result in remaining portions of each of the plurality of silicon germanium layers having the same or substantially the same width as each other.
    Type: Grant
    Filed: November 28, 2017
    Date of Patent: June 4, 2019
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Xin Miao, Wenyu Xu, Chen Zhang
  • Patent number: 10312472
    Abstract: A display panel includes a pixel array layer and a light-blocking layer. The pixel array layer has a plurality of pixel blocks, and each pixel block has a first side. The light-blocking layer disposed above the pixel array layer and has a plurality of first light-blocking belts corresponding to the pixel blocks. The first light-blocking belt at least partially extends along the first side of its corresponding pixel block. Accordingly, the outgoing light emitted at a larger angle from the pixel blocks can be at least partially blocked.
    Type: Grant
    Filed: June 5, 2018
    Date of Patent: June 4, 2019
    Assignee: AU OPTRONICS CORPORATION
    Inventors: Yi-Hong Chen, Chung-Chia Chen, Meng-Ting Lee
  • Patent number: 10304834
    Abstract: A semiconductor device and a method of fabricating a semiconductor device, the device including a substrate; an active pattern spaced apart from the substrate and extending in a first direction; and a gate structure on the active pattern and extending in a second direction crossing the first direction, wherein a lower portion of the active pattern extends in the first direction and includes a first lower surface that is sloped with respect to an upper surface of the substrate.
    Type: Grant
    Filed: March 29, 2018
    Date of Patent: May 28, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sangmoon Lee, Jungtaek Kim, Yihwan Kim, Woo Bin Song, Dongsuk Shin, Seung Ryul Lee
  • Patent number: 10305034
    Abstract: In order to improve the number rewrites by improving the dielectric breakdown resistance of an ion conducting layer in a variable resistance element, this variable resistance element is provided with: a first electrode that contains at least copper; a second electrode that contains at least Ru, nitrogen and a first metal; and an ion conducting layer that is positioned between the first electrode and the second electrode.
    Type: Grant
    Filed: June 8, 2016
    Date of Patent: May 28, 2019
    Assignee: NEC CORPORATION
    Inventors: Munehiro Tada, Naoki Banno, Koichiro Okamoto
  • Patent number: 10304933
    Abstract: A transistor includes a trench defined in a semiconductor substrate. A gate electrode is disposed in the trench and insulated from a sidewall of the trench by a gate dielectric. A shield electrode is disposed in the trench below the gate electrode and insulated from the gate electrode and the sidewall of the trench by a shield dielectric. The shield dielectric includes solid dielectric portions and a cavity disposed between the shield electrode and the sidewall of the trench.
    Type: Grant
    Filed: April 24, 2018
    Date of Patent: May 28, 2019
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Sangsu Woo, Jongho Park, SeWoon Kim, SangYong Lee, Youngkwon Kang
  • Patent number: 10297505
    Abstract: A method of manufacturing a semiconductor device includes forming a first insulating film over a first fin structure and a second insulating film over a second fin structure, coating a protective layer over the second insulating film, removing the first insulating film to expose a portion of the first fin structure, and forming a first oxide film over the exposed portion of the first fin structure using a non-aqueous solvent-based chemical.
    Type: Grant
    Filed: January 23, 2018
    Date of Patent: May 21, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kuo-Sheng Chuang, You-Hua Chou, Yusuke Oniki
  • Patent number: 10297456
    Abstract: A dielectric structure for a nitride semiconductor device and a method of forming the same. A semiconductor device includes at least one semiconductor layer. The at least one semiconductor layer includes a gallium nitride semiconductor material. The semiconductor device also includes an oxidized layer disposed over the at least one semiconductor layer. The oxidized layer includes an oxidized form of the gallium nitride semiconductor of the at least one semiconductor layer. A silicon oxide layer is disposed over the oxidized layer. A gate is disposed over the silicon oxide layer.
    Type: Grant
    Filed: March 29, 2017
    Date of Patent: May 21, 2019
    Assignee: Massachusetts Institute of Technology
    Inventors: Bernard A. Alamariu, Omair I. Saadat, Tomas Apostol Palacios
  • Patent number: 10290686
    Abstract: An aspect of the present invention is directed to a display device including: an array substrate arranged with a plurality of pixels each having a light-emitting element are arranged; a first resin layer covering the plurality of pixels and having a first surface subjected to an alignment process; polarizers disposed over the first surface and aligned according to the alignment process; and a counter substrate disposed over the first resin layer.
    Type: Grant
    Filed: July 21, 2017
    Date of Patent: May 14, 2019
    Assignee: Japan Display Inc.
    Inventor: Daisuke Kato
  • Patent number: 10283666
    Abstract: Manufacture of multi-junction solar cells, and devices thereof, are disclosed. The architectures are also adapted to provide for a more uniform and consistent fabrication of the solar cell structures, leading to improved yields, greater efficiency, and lower costs. Certain solar cells may be from a different manufacturing process and further include one or more compositional gradients of one or more semiconductor elements in one or more semiconductor layers, resulting in a more optimal solar cell device. A multi-junction cell may include a back surface field layer, a tunneling junction layer, a first active cell, and a second active cell.
    Type: Grant
    Filed: August 18, 2017
    Date of Patent: May 7, 2019
    Assignee: EpiWorks, Inc.
    Inventors: David Ahmari, Swee Lim, Shiva Rai, David Forbes