Patents Examined by Mohamed M Gebril
  • Patent number: 10515023
    Abstract: This disclosure is directed to a system for address mapping and translation protection. In one embodiment, processing circuitry may include a virtual machine manager (VMM) to control specific guest linear address (GLA) translations. Control may be implemented in a performance sensitive and secure manner, and may be capable of improving performance for critical linear address page walks over legacy operation by removing some or all of the cost of page walking extended page tables (EPTs) for critical mappings. Alone or in combination with the above, certain portions of a page table structure may be selectively made immutable by a VMM or early boot process using a sub-page policy (SPP). For example, SPP may enable non-volatile kernel and/or user space code and data virtual-to-physical memory mappings to be made immutable (e.g., non-writable) while allowing for modifications to non-protected portions of the OS paging structures and particularly the user space.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: December 24, 2019
    Assignee: Intel Corporation
    Inventors: Ravi L. Sahita, Gilbert Neiger, Vedvyas Shanbhogue, David M. Durham, Andrew V. Anderson, David A. Koufaty, Asit K. Mallick, Arumugam Thiyagarajah, Barry E. Huntley, Deepak K. Gupta, Michael Lemay, Joseph F. Cihula, Baiju V. Patel
  • Patent number: 10515017
    Abstract: A computing system comprises at least one processing unit, at least one memory controller in communication with the processing unit, and a main memory in communication with the processing unit through the memory controller. A memory hierarchy of the computing system includes at least one cache, the memory controller, and the main memory. The memory hierarchy is divided into a plurality of memory pools. The main memory comprises a set of memory modules split in ranks each having a rank address defined by a set of rank address bits. Each rank has a set of memory devices comprising one or more banks each having a bank address defined by a set of bank address bits. A plurality of threads execute on the processing unit, and are assigned to the memory pools based on one or more memory partitioning techniques, including bank partitioning, rank partitioning, or memory controller partitioning.
    Type: Grant
    Filed: February 23, 2017
    Date of Patent: December 24, 2019
    Assignee: Honeywell International Inc.
    Inventors: Pavel Zaykov, Lucie Matusova
  • Patent number: 10466936
    Abstract: According to an embodiment, storage configurations are identified for storing items, such as database tables, partitions, or any other types of objects or data structures, within a desired storage area, such as an in-memory data store or any other limited storage resource. Each of the storage configurations is assigned to a particular item of the items. Each of the storage configurations associates the assigned particular item with one or more storage configuration options. Storage recommendations are generated for at least a set of the storage configurations. A different storage recommendation exists for each storage configuration in the set of the storage configurations. The storage recommendation associates the storage configuration with a range of possible storage sizes for a particular storage area of a system. Based on the storage recommendations, recommended system configurations a generated for different possible storage sizes of the particular storage area.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: November 5, 2019
    Assignee: Oracle International Corporation
    Inventors: John Raitto, Uri Shaft
  • Patent number: 10452596
    Abstract: Some embodiments include apparatuses and methods having an interface to communicate with a host, memory cells, and a control unit coupled to the interface to associate a portion of the memory cells with a logical address range based on control information provided to the interface from the host. The control unit is configured to cause the portion of the memory cells to operate in a configuration mode indicated by the control information from the host. Each memory cell in the portion of the memory cells is operable to store at most one bit of information if the configuration mode is a first configuration mode and to store more than one bit of information if the configuration mode is a second configuration mode.
    Type: Grant
    Filed: October 29, 2015
    Date of Patent: October 22, 2019
    Assignee: Micron Technology, Inc.
    Inventor: George F Carey
  • Patent number: 10452317
    Abstract: A method includes maintaining, by a storage unit, a plurality of source name based addressing maps regarding encoding data slice storage by a plurality of storage units. The method further includes receiving, by the storage unit, an access request for an encoded data slice having a source name corresponding to a DSN address. The method further includes accessing, by the storage unit, the source name based address maps to determine whether the encoded data slice is effected by the DAP redistribution operation. The method further includes, when the encoded data slice is effected by the DAP redistribution operation, determining, by the storage unit, to execute the access request, proxy the access request, or deny the access request. The method further includes, when the determination is to execute the access request, executing, by the storage unit, the access request for the encoded data slice.
    Type: Grant
    Filed: December 15, 2017
    Date of Patent: October 22, 2019
    Assignee: PURE STORAGE, INC.
    Inventors: Jason K. Resch, Wesley B. Leggette, Manish Motwani
  • Patent number: 10445010
    Abstract: In a method of throttling temperature of a nonvolatile memory device including a memory cell array, a current temperature of the nonvolatile memory device may be detected periodically. The current temperature may be compared with a reference temperature. Whether an external input/output command, which is provided by a memory controller, exists may be determined when the current temperature is lower than the reference temperature. An input/output operation, which corresponds to the external input/output command, may be performed on the memory cell array when the external input/output command exists. A desired and/or alternatively predetermined internal input/output operation may be performed on the memory cell array regardless of a command from the memory controller when the external input/output command does not exist.
    Type: Grant
    Filed: February 23, 2017
    Date of Patent: October 15, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-Won Jeong, Hee-Woong Kang
  • Patent number: 10417121
    Abstract: In general, techniques are described for monitoring memory usage in computing devices. A computing device comprising a memory and a control unit that executes a kernel of an operating system having kernel sub-systems may implement the techniques. A memory manager kernel subsystem, in response to requests for amounts of the memory from other one kernel sub-systems, allocates memory blocks from the memory. The memory manager, in response to requests to de-allocate one or more of the allocated memory blocks, determines the corresponding requested amounts of memory and sizes of the de-allocated blocks. The memory manager then generates memory usage information based on the determined requested amounts of memory and the determined ones of the two or more different sizes. The memory usage information specifies usage of the memory in terms of the two or more different sizes of the allocated plurality of memory blocks.
    Type: Grant
    Filed: December 19, 2011
    Date of Patent: September 17, 2019
    Assignee: Juniper Networks, Inc.
    Inventors: Suhas Suhas, William N. Pohl, Amit Ranpise
  • Patent number: 10416900
    Abstract: Technologies for addressing data in a memory include an apparatus that includes a memory and a controller. The memory is to store sub-blocks of data in a data table and a pointer table of locations of the sub-blocks in the data table. The controller is to manage the storage and lookup of data in the memory. Further, the controller is to store a sub-block pointer in the pointer table to a location of a sub-block in the data table and store a second pointer that references an entry where the sub-block pointer is stored in the pointer table.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: September 17, 2019
    Assignee: Intel Corporation
    Inventors: Jawad B. Khan, Vinodh Gopal, Sanjeev N. Trika
  • Patent number: 10394468
    Abstract: A method for execution by a storage unit of a dispersed storage network (DSN) includes receiving a data slice for storage. A first bin that includes the data slice is generated and stored in a first location of a memory device of the storage unit, and a bin pointer that includes a reference to the first location is generated. A revision of the data slice is later received, and a second bin that includes the revised data slice is generated and stored in a second location of the memory device. A modified bin pointer is generated by editing the bin pointer to include a reference to the second location. A back pointer that references the first location is generated in response to commencing writing of the revised data slice. The back pointer is deleted in response to determining that the revised data slice has reached a finalized write stage.
    Type: Grant
    Filed: February 23, 2017
    Date of Patent: August 27, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Andrew D. Baptist, Manish Motwani, Praveen Viraraghavan, Ilya Volvovski
  • Patent number: 10387308
    Abstract: The present disclosure provides a method and apparatus for online reducing cache devices from a cache. The cache includes a first cache device and a second cache device, the method comprising: keeping the cache and the second cache device in an enabled state; labeling the first cache device as a to-be-reduced device so as to block a new data page from being promoted to the first cache device; removing a cached data page from the first cache device; removing the cached input output (IO) historical information from the first cache device; and removing the first cache device from the cache. There is also provided a corresponding apparatus.
    Type: Grant
    Filed: September 19, 2016
    Date of Patent: August 20, 2019
    Assignee: EMC IP Holding Company LLC
    Inventors: Xinlei Xu, Liam Xiongcheng Li, Jian Gao, Lifeng Yang, Ruiyong Jia
  • Patent number: 10372351
    Abstract: An apparatus includes a non-volatile memory and a controller coupled to the non-volatile memory. The controller includes an interface configured to send control information to a host device. The control information is associated with first parity information. The controller further includes a circuit configured to determine second parity information associated with the control information. The controller is configured to terminate and optionally rollback an operation associated with the control information in response to the first parity information differing from the second parity information. The terminated optionally rolled-back operation associated with the control information may be a non-blocking control sync operation.
    Type: Grant
    Filed: February 23, 2017
    Date of Patent: August 6, 2019
    Assignee: Western Digital Technologies, Inc.
    Inventors: Marina Frid, Igor Genshaft
  • Patent number: 10372609
    Abstract: An embodiment of a semiconductor package apparatus may include technology to determine if a memory request for a second level memory results in a miss with respect to a first level memory, determine if a range of the second level memory corresponding to the memory request is unwritten, if the memory request results in the miss with respect to the first level memory, and blank a corresponding range of the first level memory if the range of the second level memory corresponding to the memory request is determined to be unwritten. Other embodiments are disclosed and claimed.
    Type: Grant
    Filed: September 14, 2017
    Date of Patent: August 6, 2019
    Assignee: Intel Corporation
    Inventor: Sagi Weiss
  • Patent number: 10365974
    Abstract: Examples include the acquisition of objects names for portion index objects. Some examples include acquisition, from a remote object storage system, of a list of object names for a plurality of portion index objects, stored in the remote object storage system. In some examples, for each of the portion index objects, the acquired object name includes an identifier of an associated deduplicated backup item and information identifying a data range of the associated deduplicated backup item that is represented by metadata of the portion index object.
    Type: Grant
    Filed: September 16, 2016
    Date of Patent: July 30, 2019
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Andrew Todd, Richard Phillip Mayo
  • Patent number: 10359951
    Abstract: A method, computer program product, computing system, and system for snapshotless backup are described. The method may include receiving, via a backup agent, an indication of a virtual machine to be backed up in a backup archive file. The backup agent may run outside of the virtual machine. The virtual machine may be hosted by a virtualization host device. The method may further include identifying, via the backup agent, a virtual disk associated with the virtual machine indicated to be backed up. The method may also include tracking, via a virtualization host agent running on the virtualization host device outside the virtual machine, changes to the virtual disk associated with the virtual machine on a sector level basis. The method may additionally include reading the virtual disk and transmitting sectors from the virtual disk to the backup archive file on a first pass.
    Type: Grant
    Filed: June 30, 2014
    Date of Patent: July 23, 2019
    Assignee: ACRONIS INTERNATIONAL GmbH
    Inventors: Yuri Per, Maxim V. Lyadvinsky, Serguei M. Beloussov, Dmitry Egorov, Alexey Borodin
  • Patent number: 10346048
    Abstract: An electronic system includes: a key value storage device, configured to transfer user data, including: a non-volatile memory array, an interface circuit, coupled to the non-volatile memory array, configured to receive a key value transfer command, a volatile memory, coupled to the interface circuit and the non-volatile memory array, configured to transfer the user data with the interface circuit or the non-volatile memory array, and a device processor, coupled to the interface circuit, configured to manage the non-volatile memory array, the volatile memory, and the interface circuit by a key value index tree to access the user data; and wherein: the interface circuit, connected to a device coupling structure, configured to receive the key value transfer command; and the device processor is configured to address the non-volatile memory array, the volatile memory, or both concurrently based on a key value transfer.
    Type: Grant
    Filed: October 29, 2015
    Date of Patent: July 9, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sushma Devendrappa, James Liu, Changho Choi, Sun Xiling
  • Patent number: 10318198
    Abstract: Provides a bin-type heap where bin sizes can be easily customized to the exact requirements of a specific system by means of a bin size array, thus resulting in greater efficiency and better performance. Also provides enhanced debugging support and self-healing. Intended primarily for embedded and similar systems, which require high performance, deterministic operation, efficient memory utilization, high reliability, and which are characterized by limited block size requirements and ample available idle time.
    Type: Grant
    Filed: February 23, 2017
    Date of Patent: June 11, 2019
    Inventor: Ralph Crittenden Moore
  • Patent number: 10318414
    Abstract: A memory system include a memory device including a plurality of blocks, each of the blocks having a plurality of pages, and a controller suitable for determining valid pages from among the plurality of pages based on data temperature, and performing a garbage collection process based on a number of valid pages and data temperature of the valid pages.
    Type: Grant
    Filed: October 29, 2015
    Date of Patent: June 11, 2019
    Assignee: SK hynix Inc.
    Inventors: Jason Bellorado, Xiangyu Tang
  • Patent number: 10310749
    Abstract: A computer-implemented method for predicting failure of a disk that is configured to store digital data is provided. The method includes receiving health status data from a monitor that measures health status of the disk, the health status data including factor values associated with a plurality of respective disk failure factors, receiving an overall factor weight assigned to each disk failure factor, wherein the overall factor weight indicates the contribution of that factor in predicting a failure of the disk, and receiving, for each disk failure factor, a weight factor assigned to each bin of a set of bins, wherein each bin has an assigned range of factor values, the weight factor assigned to each bin indicating a probability of disk failure based on empirical results.
    Type: Grant
    Filed: September 16, 2016
    Date of Patent: June 4, 2019
    Assignee: NetScout Systems Texas, LLC
    Inventor: Fnu Akshara
  • Patent number: 10296460
    Abstract: The disclosed embodiments relate to a method for controlling prefetching in a processor to prevent over-saturation of interfaces in the memory hierarchy of the processor. While the processor is executing, the method determines a bandwidth utilization of an interface from a cache in the processor to a lower level of the memory hierarchy. Next, the method selectively adjusts a prefetch-dropping high-water mark for occupancy of a miss buffer associated with the cache based on the determined bandwidth utilization, wherein the miss buffer stores entries for outstanding demand requests and prefetches that missed in the cache and are waiting for corresponding data to be returned from the lower level of the memory hierarchy, and wherein when the occupancy of the miss buffer exceeds the prefetch-dropping high-water mark, subsequent prefetches that cause a cache miss are dropped.
    Type: Grant
    Filed: June 29, 2016
    Date of Patent: May 21, 2019
    Assignee: Oracle International Corporation
    Inventors: Suraj Sudhir, Yuan C. Chou
  • Patent number: 10261900
    Abstract: A transmission device (300) comprising a data cache system is provided with a data acquisition part (315) for acquiring volume data indicating the volume of transactionable products or services transmitted from a server. The transmission device (300) is provided with a saving part (320) for saving the acquired volume data in an information memory (390) as cache data, and a request acquisition part (330) for acquiring requests seeking volume output. The transmission device (300) is provided with a determination part (350) for determining whether or not the cache data is valid based on the elapsed time from when the cache data was received or saved and the volume indicated by the cache data, when a request is acquired. When the determination is that the cache data is invalid, the data acquisition part (315) receives new volume data from the server, and the saving part (320) saves the new volume data as new cache data in the information memory (390).
    Type: Grant
    Filed: March 29, 2013
    Date of Patent: April 16, 2019
    Assignee: Rakuten, Inc.
    Inventor: SeungHee Lee