Abstract: A light-emitting module and a light-emitting diode are provided. The light-emitting diode includes an epitaxial light-emitting structure to generate a light beam with a broadband blue spectrum. A spectrum waveform of the broadband blue spectrum has a full width at half maximum (FWHM) larger than or equal to 30 nm. The spectrum waveform has a plurality of peak inflection points, and a difference between two wavelength values to which any two adjacent ones of the peak inflection points respectively correspond is less than or equal to 18 nm.

Abstract: A semiconductor light-emitting device includes a substrate, a connection structure disposed on the substrate, a semiconductor light-emitting unit disposed on the connection structure, and first and second electrodes. The connection structure includes an insulating layer formed with a through hole, a first electrically connecting layer disposed on the insulating layer and electrically connected to the first electrode, and a second electrically connecting layer disposed between the substrate and the insulating layer and extending through the through hole to be electrically connected to the second electrode. A projection of the second electrode on the insulating layer covers a portion of the insulating layer.

Abstract: A quantum dot light-emitting device including first electrode and a second electrode, a quantum dot layer between the first electrode and the second electrode, a first electron transport layer and a second electron layer disposed between the quantum dot layer and the second electrode. The second electron transport layer is disposed between the quantum dot layer and the first electron transport layer, wherein each of the first electron transport layer and the second electron transport layer includes an inorganic material. A lowest unoccupied molecular orbital energy level of the second electron transport layer is shallower than a lowest unoccupied molecular orbital energy level of the first electron transport layer, and a lowest unoccupied molecular orbital energy level of the quantum dot layer is shallower than a lowest unoccupied molecular orbital energy level of the second electron transport layer. An electronic device including the quantum dot light-emitting device.

Abstract: A method of manufacturing a carrying substrate is provided. At least one circuit component is disposed on a first circuit structure. An encapsulation layer is formed on the first circuit structure and encapsulates the circuit component. A second circuit structure is formed on the encapsulation layer and electrically connected to the circuit component. The circuit component is embedded in the encapsulation layer via an existing packaging process. Therefore, the routing area is increased, and a package substrate requiring a large size has a high yield and low manufacturing cost.

Abstract: A semiconductor device includes a semiconductor substrate having a first lattice constant, a dopant blocking layer disposed over the semiconductor substrate, the dopant blocking layer having a second lattice constant different from the first lattice constant, and a buffer layer disposed over the dopant blocking layer, the buffer layer having a third lattice constant different from the second lattice constant. The semiconductor device also includes a plurality of channel members suspended over the buffer layer, an epitaxial feature abutting the channel members, and a gate structure wrapping each of the channel members.

Abstract: An approach for representing both positive and negative weights in neuromorphic computing is disclosed. The approach leverages a double gate FeFET (ferroelectric field effect transistor) device. The device leverages a double-gate FeFET with four terminals (two separate gates and source and drain) and ferroelectric gate dielectric. The device may have a junction-less channel. A synaptic weight is programmed by biasing one of the two gates. The store weight is sensed via a current flow from source to drain. A pre-defined bias is applied to the other gate during the sensing, such that a reference current is subtracted from the drain current. The net current for sensing is current from the synaptic devices subtracted by the pre-defined reference current.

Abstract: Provided is a light-emitting device including an organic light-emitting element and a control unit that controls the organic light-emitting element. The organic light-emitting element includes a first electrode, a second electrode, and an organic light-emitting layer which is disposed between the first electrode and the second electrode and in which separation of charges occurs due to incidence of excited light. The control unit changes a potential difference between the first electrode and the second electrode so that recoupling of the charges occurs, in a second period after passage of a delay period from a first period in which the excited light is incident to the organic light-emitting layer.

Abstract: Semiconductor devices and methods of manufacture are provided wherein a metallization layer is located over a substrate, and a power grid line is located within the metallization layer. A signal pad is located within the metallization layer and the signal pad is surrounded by the power grid line. A signal external connection is electrically connected to the signal pad.

Abstract: A bipolar junction transistor (BJT) may include a substrate defining a collector region therein. A first superlattice may be on the substrate including a plurality of stacked groups of first layers, with each group of first layers including a first plurality of stacked base semiconductor monolayers defining a first base semiconductor portion, and at least one first non-semiconductor monolayer constrained within a crystal lattice of adjacent first base semiconductor portions. Furthermore, a base may be on the first superlattice, and a second superlattice may be on the base including a second plurality of stacked groups of second layers, with each group of second layers including a plurality of stacked base semiconductor monolayers defining a second base semiconductor portion, and at least one second non-semiconductor monolayer constrained within a crystal lattice of adjacent second base semiconductor portions. An emitter may be on the second superlattice.

Abstract: A power module, including: a first conductor, disposed at a first reference plane; a second conductor, disposed at a second reference plane, wherein projections of the first and second conductors on the first reference plane have a first overlap area; a third conductor, disposed at a third reference plane; a plurality of first switches and a plurality of second switches, wherein at least one of the first switches and at least one of the second switches that are located on a left side are alternatively disposed, at least one of the first switches and at least one of the second switches that are located on a right side are alternately disposed, and the left side and the right side of the first overlap area are oppositely disposed. Heat sources of the power module are evenly distributed and its parasitic inductance is low.

Abstract: A method includes forming isolation regions extending into a semiconductor substrate. A semiconductor strip is between the isolation regions. The method further includes recessing the isolation regions so that a top portion of the semiconductor strip protrudes higher than top surfaces of the isolation regions to form a semiconductor fin, measuring a fin width of the semiconductor fin, generating an etch recipe based on the fin width, and performing a thinning process on the semiconductor fin using the etching recipe.

Abstract: The present disclosure relates generally to structures in semiconductor devices and methods of forming the same. More particularly, the present disclosure relates to high electron mobility transistor (HEMT) devices having a silicided polysilicon layer. The present disclosure may provide an active region above a substrate, source and drain electrodes in contact with the active region, a gate above the active region, the gate being laterally between the source and drain electrodes, a polysilicon layer above the substrate, and a silicide layer on the polysilicon layer. The active region includes at least two material layers with different band gaps. The polysilicon layer may be configured as an electronic fuse, a resistor, or a diode.

Abstract: A light-emitting device includes: a plurality of first electrodes respectively disposed in a first subpixel, a second subpixel, and a third subpixel; a second electrode facing the plurality of first electrodes; a first emission layer disposed in the first subpixel to emit a first-color light; a second emission layer disposed in the second subpixel to emit a second-color light; a first layer disposed between the second electrode and each of the first emission layer and the second emission layer, and integrated with the first subpixel, the second subpixel, and the third subpixel; a hole transport region disposed between the plurality of first electrodes and each of the first layer, the first emission layer, and the second emission layer; a first auxiliary layer disposed between the hole transport region and the first emission layer; and a first intermediate layer disposed between the first auxiliary layer and the first emission layer.

Abstract: Various embodiments of the present disclosure are directed towards a microelectromechanical system (MEMS) device. The MEMS device includes a dielectric structure disposed over a first semiconductor substrate, where the dielectric structure at least partially defines a cavity. A second semiconductor substrate is disposed over the dielectric structure. The second semiconductor substrate includes a movable mass, where opposite sidewalls of the movable mass are disposed between opposite sidewall of the cavity. An anti-stiction structure is disposed between the movable mass and the dielectric structure, where the anti-stiction structure is a first silicon-based semiconductor.

Abstract: A solid-state imaging device including a first substrate having a pixel unit formed thereon and including a first semiconductor substrate and a first multi-layered wiring layer stacked, a second substrate having a circuit formed thereon and including a second semiconductor substrate and a second multi-layered wiring layer, the circuit having a predetermined function, and a third substrate having a circuit formed thereon and including a third semiconductor substrate and a third multi-layered wiring layer. The first substrate and the second substrate are bonded together such that that the first multi-layered wiring layer and the second semiconductor substrate are opposed to each other. The solid-state imaging device includes a first coupling structure and a second coupling structure. The first coupling structure electrically couples a circuit of the first substrate and the circuit of the second substrate.

Abstract: The present invention provides an organic electroluminescent device including an electron-leakage suppression layer and a hole-leakage suppression layer adjusted to have predetermined physical properties, in portions of a hole transporting area and an electron transporting area disposed on opposite sides of a light emitting layer, respectively, thereby reducing leakage of electrons and holes and thus improved in terms of characteristics such as a low driving voltage, high luminous efficiency, and long lifespan.

Abstract: An electronic device comprises an array of memory cells comprising a channel material laterally proximate to tiers of alternating conductive materials and dielectric materials. The channel material comprises a heterogeneous semiconductive material varying in composition across a width thereof. Related electronic systems and methods are also disclosed.

Abstract: Layered structures described herein include electronic devices with 2-dimensional electron gas between polar-oriented cubic rare-earth oxide layers on a non-polar semiconductor. Layered structure includes a semiconductor device, comprising a III-N layer or rare-earth layer, a polar rare-earth oxide layer grown over the III-N layer or rare-earth layer, a gate terminal deposited or grown over the polar rare-earth oxide layer, a source terminal that is deposited or epitaxially grown over the layer, and a drain terminal that is deposited or grown over the layer.

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming first nanostructures and second nanostructures over a semiconductor substrate. The method also includes forming a dielectric fin between the first nanostructures and the second nanostructures. The method further includes forming a metal gate stack wrapped around the first nanostructures, the second nanostructures, and the dielectric fin. In addition, the method includes forming an insulating structure penetrating into the metal gate stack and aligned with the dielectric fin.

Abstract: A digital isolator according to an embodiment includes a first electrode, a first insulating part, a second electrode, a second insulating part, and a first dielectric part. The first insulating part is located under the first electrode. The second electrode is located under the first insulating part. The second insulating part is located around the first electrode along a first plane perpendicular to a first direction. The first direction is from the second electrode toward the first electrode. The first dielectric part is located between the first electrode and the second insulating part in a second direction along the first plane. The first dielectric part contacts the first electrode. A relative dielectric constant of the first dielectric part is greater than a relative dielectric constant of the first insulating part.