Abstract: A device verification method, a UVM verification platform, an electronic apparatus, and a storage medium are provided. The method includes: determining a transaction class corresponding to a device under test, and instantiating a first interface in a callback function; sending input data to the device under test based on a bus protocol, and sequentially adding the input data to an array of the first interface according to addresses of the input data; instantiating a second interface in a monitor device, and sequentially adding output data to an array of the second interface according to addresses of the output data; and comparing the input data and the output data that have same addresses in the array of the first interface and the array of the second interface, and outputting a verification result of the device under test according to a comparison result.

Abstract: A voltage supply circuit includes a charging circuit, a window adjustment circuit, a driving voltage adjustment circuit, a sampling and feedback circuit and a storage circuit. The charging circuit includes a modulation input terminal for receiving a control voltage; and an energy supply terminal for selectively outputting a charging energy according to the control voltage. The window adjustment circuit is used to adjust the control voltage according to a sampling output voltage corresponding to an output voltage signal, and output the control voltage. The driving voltage adjustment circuit is used to keep the control voltage within a clamping voltage according to the output voltage signal. The sampling and feedback circuit is used to generate the output voltage signal according to a voltage at the energy supply terminal. The storage circuit is used to store the charging energy to pull up the voltage at the energy supply terminal.

Abstract: Provided are a method and system for visualization of a 3D electronic device. The method includes: a structural and/or electrical characteristic of the electronic device is simulated to obtain first visualization data, the electronic device including a semiconductor device and/or an integrated circuit and the first visualization data including 3D grid position information of the electronic device and/or a physical quantity at a grid point; the 3D grid position information and/or physical quantity at the grid point in the first visualization data are/is converted into second visualization data suitable for virtual 3D displaying according to a data type; and the second visualization data is rendered in a virtual space to display a structure and/or physical quantity of the electronic device in the virtual space.

Abstract: A method of managing second use batteries incudes communicating an external load demand to battery management modules (BMMs) of first use batteries and second use batteries; communicating, by each of the BMMs, the state of health (SoH) of the respective first or second use battery to the other BMMs; by the BMMs of the first use batteries with highest SoH, engaging the first use batteries to meet the external load demand, wherein the highest SoH is determined by the BMMs by ranking the SoH of each battery relative to the other batteries; and by the BMMs of the second use batteries, setting a discharge limit for each of the second use batteries based on the SoH of the respective second use battery, and controlling the second use batteries to supply currents not to exceed the discharge limits of the respective second use batteries to load-share with the first use batteries.

Abstract: A quantum bit control apparatus, including a control signal generator, optoelectronic detectors, a quantum chip, and a shielding apparatus, the optoelectronic detectors are disposed in the shielding apparatus, and an inner part of the shielding apparatus is in a vacuum state. The control signal generator is disposed in a first temperature area, and is configured to generate optical control signals and send the N optical control signals to the optoelectronic detectors. The optoelectronic detectors are disposed in a second temperature area having a temperature lower than of the first temperature area. The N optoelectronic detectors are configured to convert the received optical control signals into electronically controlled signals and send the electronically controlled signals to the quantum chip. The quantum chip is disposed in the second temperature area, and controls a quantum bit in the quantum chip based on the electronically controlled signals.

Abstract: Examples described herein provide a computer-implemented method that includes identifying, by a processing device, a victim/aggressor pair of nets for an integrated circuit. The method further includes severing nets of the victim/aggressor pair of nets. The method further includes swapping severed segments of the nets. The method further includes rerouting the nets subsequent to swapping the severed segments of the nets.

Abstract: The present invention relates to a method for activating a secondary battery. The present invention comprises: a primary charging step of charging a secondary battery including a positive electrode, a negative electrode, a separator, and an electrolyte; a room temperature-aging step of storing, at a room temperature, the secondary battery that has undergone the primary charging step; and a high temperature-aging step of storing, at a high temperature, the secondary battery that has undergone the room temperature-aging step, wherein charging/discharging is performed by alternately applying + current and ? current to the secondary battery at the end of the primary charging step. The method for activating a secondary battery according to the present invention includes alternately applying + current and ? current to the secondary battery at the end of the primary charging step to stabilize an SEI film, thereby shortening a following-up aging time.

Abstract: The invention relates to a power system for a vehicle, the power system for a vehicle, the power system comprising a plurality of supercapacitors, a plurality of batteries, at least one electronic load and a master controller, arranged so that at least one battery is connected with at least one supercapacitor, such that power from the at least one battery may be supplied to the at least one supercapacitor, wherein the master controller ability to switch the at least one supercapacitor to a further at least one supercapacitor and wherein at least one battery and/or at least one supercapacitor of the plurality of supercapacitors supplies power to the electronic load.

Abstract: A method for providing an integrated circuit design is disclosed. The method includes receiving and synthesizing a behavioral description of an integrated circuit design. The method includes generating, based on the synthesized behavioral description, a layout by placing and routing a plurality of transistor-based cells. The method includes selectively accessing a cell library that includes a plurality of non-transistor-based cells, each of the plurality of non-transistor-based cells associated with a respective delay value. The method includes updating the layout by inserting one or more of the plurality of non-transistor-based cells.

Abstract: Systems and methods related to learning-based analyzers (both supervised and unsupervised) for mitigating latch-up in integrated circuits are provided. An example method includes obtaining latch-up data concerning at least one integrated circuit configured to operate under a range of temperature conditions, where the at least one integrated circuit comprises a core portion including at least a plurality of devices each having one or more structural features formed using a lithographic process, and an input/output portion. The method further includes training the learning-based system based on training data derived from the latch-up data and a first layout rule concerning a first spacing between the core portion and the input/output portion. The method further includes using the learning-based system generating a second layout rule concerning the first spacing between the core portion and the input/output portion, where the second layout rule is different from the first layout rule.

Abstract: Disclosed is a method of evaluating placement of semiconductor devices performed by a computing device according to an exemplary embodiment of the present disclosure. The method includes receiving connection information representing a connection relationship between semiconductor devices; clustering the semiconductor devices based on the connection information; and determining a reward to train a neural network model based on clustering.

Abstract: Embodiments herein describe a techniques for identifying a first combinational cell 210 in a design for an integrated circuit, identifying a plurality of candidate combinational cells 205 to combine with the first combinational cell using a first criterion. The techniques also include combining the first combinational cell with at least one of the plurality of candidate combinational cells to form a multi-bit (MB) combinational cell 100. Upon determining the MB combinational cell satisfies a performance threshold, the first combinational cell and the at least one of the plurality of candidate combinational cells are replaced with the MB combinational cell in the design.

Abstract: Apparatuses and methods for removing a defective energy storage cell from an energy storage array is described. An apparatus includes an energy storage array including a plurality of energy storage cells, and a cell removal circuit coupled to the energy storage array. The cell removal circuit is configured to prevent a defective energy storage cell of the plurality of energy storage cells from causing other energy storage cells of the plurality of energy storage cells to become defective. A method includes receiving power at a charging node of an energy storage array, the energy storage array including a plurality of energy storage cells. Responsive to failure of an energy storage cell of the plurality of energy storage cells, current is provided through the defective energy storage cell, and responsive to the defective energy storage cell becoming an open circuit, discontinuing provision of the current through the defective energy storage cell.

Abstract: A power receiving apparatus 200 wirelessly receives power from a power transmitting apparatus 100, mutually performs device authentications with the power transmitting apparatus 100, and determines content related to power reception on the basis of a result of a performed device authentication. The apparatus 200 is capable of performing control such that in response to success in an earlier performed device authentication among the authentications, another device authentication among the authentications is performed, and performing control such that in response to failure in the earlier performed device authentication, said another device authentication is not performed.

Abstract: A method for logic design partitioning includes: collecting an RTL design file used for describing a logic circuit; performing syntax analysis processing on the RTL design file; extracting an always object and an assign object from logic model objects, and encapsulating the always object and the assign object, respectively; constructing and generating a hypergraph-based data structure; performing attribute analysis, and obtaining operating frequency information by processing according to clock domain information; associating and storing the clock domain information and the operating frequency information with corresponding nodes; and performing partitioning processing to obtain corresponding partitioned data. By means of the solutions of the present invention, other processing at the back end of the flow is not affected, the partitioning time is reduced and the partitioning efficiency is improved. Meanwhile, the logic content in chip design is partitioned efficiently, reasonably and correctly.

Abstract: A hardware design for a component that evaluates a main algebraic expression comprising at least two variables is verified, the main algebraic expression being representable as a lossless combination of a plurality of sub-algebraic expressions, and one or more of the at least two variables can be constrained to cause an instantiation of the hardware design to evaluate each of the sub-algebraic expressions. An instantiation of the hardware design is verified as correctly evaluating each of the plurality of sub-algebraic expressions, and the instantiation of the hardware design is formally evaluated as correctly evaluating one or more combinations of sub-algebraic expressions, wherein the one or more combinations comprises a combination that is equivalent to the main algebraic expression.

Abstract: Methods and systems of routing a design layout include setting an inner region and an outer region for modification of structures in an original design layout, in accordance with a minimum spacing that is based on a fabrication process. Routing of trim positions and conductive wire extents is performed within the inner region, based on positions of shapes within the outer region, including node folding of a new constraint graph to minimize perturbations from a previous constraint graph, to generate an updated design layout that can be manufactured using the fabrication process.

Abstract: A computer-assisted method for determining a microfluidic circuit configured to reproduce a neuron circuit, and comprising including the following steps: —obtaining a description of the neuron circuit, the description of the neuron circuit comprising a plurality of neuron populations and at least one neuron connection; —determining at least one first parameter for each node of a plurality of nodes of the microfluidic circuit, each node being associated with and configured to receive one neuron population among the plurality of neuron populations of the neuron circuit; —determining at least one second parameter for at least one connection of the microfluidic circuit, each connection being associated with and configured to receive a neuron connection of the at least one neuron connection of the neuron circuit; —determining the positioning of each node of the plurality of nodes and of each connection of the at least one connection.

Abstract: A blender using different charging modes with wireless charging is disclosed. Exemplary implementations may include a base assembly, a container assembly, an electrical motor, a blending component, a control interface, blending control circuitry, charging control circuitry, and/or other components. The base component may include a rechargeable battery and a wireless charging interface. The charging control circuitry may be configured to make different types of detections related to the availability and/or usage of electrical power and related to the usage and alignment of the wireless charging interface with an external charging structure. The charging control circuitry may conduct electrical power to the rechargeable battery using at least two different charging modes, thus providing different amounts of electrical power to the rechargeable battery in different charging modes.

Abstract: This disclosure describes a method for finding equivalent classes of hard defects in a stacked MOSFET array. The method includes identifying the stacked MOSFET array in a circuit netlist. The stacked MOSFET array includes standard MOSFETs sharing gate and bulk terminals. The method further includes determining electrical defects for the standard MOSFETs, grouping the electrical defects into at least one intermediate equivalent defect class based on a topological equivalence of the electrical defects, grouping the electrical defects in the at least one intermediate equivalent defect class into at least one final equivalent defect class based on an electrical equivalence of the electrical defects, performing a defect simulation on an electrical defect in the at least one final equivalent defect class, and attributing a result of the defect simulation on the electrical defect to additional electrical defects in the final equivalent defect class.