Patents Examined by Mohammed Alam
  • Patent number: 11620425
    Abstract: Methods for iteratively optimizing a two-dimensioned tiled area such as a lithographic mask include determining a halo area around each tile in the tiled area. An extended tile is made of a tile and a halo area. Each extended tile in the tiled area is iterated until a criterion is satisfied or a maximum number of iterations is met. Optimizing the extended tile produces a pattern for the tile such that at a perimeter of the tile, the pattern matches adjacent patterns that are calculated at perimeters of adjacent tiles.
    Type: Grant
    Filed: February 28, 2022
    Date of Patent: April 4, 2023
    Assignee: D2S, Inc.
    Inventors: P. Jeffrey Ungar, Hironobu Matsumoto
  • Patent number: 11620417
    Abstract: Aspects of the present disclosure address systems, methods, and a user interface for providing interactive skew group visualizations for integrated circuit (IC) design. The method includes causing display of a user interface that includes a display of a grouped view of a clock-tree including a plurality of skew group indicators. The method further includes receiving a user selection of a skew group indicator and updating the user interface to display a detailed view of the skew group including a graphical representation of each clock sink in the skew group and corresponding timing information. The method further includes receiving a second user selection of a first clock sink and in response, the display is updated to display an indicator of a physical location of the first clock sink within the clock tree.
    Type: Grant
    Filed: March 31, 2021
    Date of Patent: April 4, 2023
    Assignee: Cadence Design Systems, Inc.
    Inventors: Ainsley Malcolm Pereira, Thomas Andrew Newton
  • Patent number: 11599172
    Abstract: An electronic device is provided. The electronic device includes a housing, a battery included within the housing, a connector electrically connected to an external power supply device including an integrated circuit (IC) and exposed to a part of the housing, and a power management unit included within the housing and electrically connected to the connector, wherein the power management unit is configured to communicate with the IC of the external power supply device, and wherein the connector is configured to receive a first current of a first current value during at least a part of the communication and to receive a second current of a second current value greater than the first current value during at least a part in which the communication is not performed.
    Type: Grant
    Filed: June 8, 2021
    Date of Patent: March 7, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kuchul Jung, Sunggeun Yoon, Kisun Lee, Hoyoung Lee, Seyoung Jang, Hyemi Yu
  • Patent number: 11593542
    Abstract: A soft error-mitigating semiconductor design system and associated methods that tailor circuit design steps to mitigate corruption of data in storage elements (e.g., flip flops) due to Single Events Effects (SEEs). Required storage elements are automatically mapped to triplicated redundant nodes controlled by a voting element that enforces majority-voting logic for fault-free output (i.e., Triple Modular Redundancy (TMR)). Storage elements are also optimally positioned for placement in keeping with SEE-tolerant spacing constraints. Additionally, clock delay insertion (employing either a single global clock or clock triplication) in the TMR specification may introduce useful skew that protects against glitch propagation through the designed device.
    Type: Grant
    Filed: February 26, 2021
    Date of Patent: February 28, 2023
    Assignee: Fermi Research Alliance, LLC
    Inventors: Sandeep Miryala, James Richard Hoff, Grzegorz W. Deptuch
  • Patent number: 11594528
    Abstract: A layout modification method for fabricating a semiconductor device is provided. The layout modification method includes calculating uniformity of critical dimensions of first and second portions in a patterned layer by using a layout for an exposure manufacturing process to produce the semiconductor device. A width of the first and second portions equals a penumbra size of the exposure manufacturing process. The penumbra size is utilized to indicate which area of the patterned layer is affected by light leakage exposure from another exposure manufacturing process. The layout modification method further includes compensating non-uniformity of the first and second portions of the patterned layer according to the uniformity of critical dimensions to generate a modified layout. The first portion is divided into a plurality of first sub-portions. The second portion is divided into a plurality of second sub-portions. Each second sub-portion is surrounded by two of the first sub-portions.
    Type: Grant
    Filed: May 26, 2021
    Date of Patent: February 28, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hung-Wen Cho, Fu-Jye Liang, Chun-Kuang Chen, Chih-Tsung Shih, Li-Jui Chen, Po-Chung Cheng, Chin-Hsiang Lin
  • Patent number: 11550978
    Abstract: A detection unit (231) detects, based on synthesis result data obtained by logic synthesis on design data of a target circuit, a predicted place where a glitch is predicted to occur in the target circuit. An insertion unit (232) inserts a glitch removal circuit in an output side of the predicted place by making a change to at least one of the synthesis result data and the design data.
    Type: Grant
    Filed: April 6, 2021
    Date of Patent: January 10, 2023
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventor: Susumu Hirano
  • Patent number: 11544441
    Abstract: Various examples are provided related to automated chip design, such as a pareto-optimization framework for automated network-on-chip design. In one example, a method for network-on-chip (NoC) design includes determining network performance for a defined NoC configuration comprising a plurality of n routers interconnected through a plurality of intermediate links; comparing the network performance of the defined NoC configuration to at least one performance objective; and determining, in response to the comparison, a revised NoC configuration based upon iterative optimization of the at least one performance objective through adjustment of link allocation between the plurality of n routers. In another example, a method comprises determining a revised NoC configuration based upon iterative optimization of at least one performance objective through adjustment of a first number of routers to obtain a second number of routers and through adjustment of link allocation between the second number of routers.
    Type: Grant
    Filed: February 12, 2019
    Date of Patent: January 3, 2023
    Assignee: ARIZONA BOARD OF REGENTS ON BEHALF OF THE UNIVERSITY OF ARIZONA
    Inventor: Wolfgang Fink
  • Patent number: 11544574
    Abstract: The present disclosure relates to a computer-implemented method for electronic design. Embodiments may include receiving, using at least one processor, an electronic design schematic and optionally an electronic design layout. Embodiments may further include analyzing the electronic design schematic to determine if one or more required features of a particular circuit structure are present. If the one or more required features are present, embodiments may include analyzing, using a machine learning model, the electronic design schematic to determine if one or more optional features of the particular circuit structure are present.
    Type: Grant
    Filed: July 25, 2019
    Date of Patent: January 3, 2023
    Assignee: Cadence Design Systems, Inc.
    Inventors: Wangyang Zhang, Elias Lee Fallon
  • Patent number: 11544438
    Abstract: A system and method for placing Josephson junction splitters on a superconducting circuit layout receives a specification of locations to be connected by a number of Josephson transmission lines. The system determines, based on the specification, a topology specifying connections between the locations, the topology including a plurality of 1-to-2 Josephson junction splitter nodes. The system determines splitter node locations based at least on ranges determined from distances between adjacent range endpoints of a previous level of the topology, and the system places each of the 1-to-2 Josephson junction splitter nodes at the determined splitter node locations.
    Type: Grant
    Filed: April 27, 2021
    Date of Patent: January 3, 2023
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Paul Accisano, Kenneth Reneris
  • Patent number: 11537773
    Abstract: A method for providing an integrated circuit design is disclosed. The method includes receiving and synthesizing a behavioral description of an integrated circuit design. The method includes generating, based on the synthesized behavioral description, a layout by placing and routing a plurality of transistor-based cells. The method includes selectively accessing a cell library that includes a plurality of non-transistor-based cells, each of the plurality of non-transistor-based cells associated with a respective delay value. The method includes updating the layout by inserting one or more of the plurality of non-transistor-based cells.
    Type: Grant
    Filed: March 9, 2021
    Date of Patent: December 27, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Kenan Yu, Qingwen Deng
  • Patent number: 11537043
    Abstract: Metrology methods and targets are provided for reducing or eliminating a difference between a device pattern position and a target pattern position while maintaining target printability, process compatibility and optical contrast—in both imaging and scatterometry metrology. Pattern placement discrepancies may be reduced by using sub-resolved assist features in the mask design which have a same periodicity (fine pitch) as the periodic structure and/or by calibrating the measurement results using PPE (pattern placement error) correction factors derived by applying learning procedures to specific calibration terms, in measurements and/or simulations. Metrology targets are disclosed with multiple periodic structures at the same layer (in addition to regular target structures), e.g., in one or two layers, which are used to calibrate and remove PPE, especially when related to asymmetric effects such as scanner aberrations, off-axis illumination and other error sources.
    Type: Grant
    Filed: January 28, 2021
    Date of Patent: December 27, 2022
    Assignee: KLA-TENCOR CORPORATION
    Inventors: Yoel Feler, Vladimir Levinski, Roel Gronheid, Sharon Aharon, Evgeni Gurevich, Anna Golotsvan, Mark Ghinovker
  • Patent number: 11537775
    Abstract: A system and method for providing timing and placement co-optimization for engineering change order (ECO) cells is described. According to one embodiment, an ECO for a current design of an integrated circuit is accessed. The ECO includes inserting an ECO cell among placed and routed current cells of the current design. A target region in the current design is identified for placement of the ECO cell, but the target region has insufficient open space to place the ECO cell. At least one current cell will have to be moved in order to place the ECO cell in the target region. Timing slacks for current cells in a neighborhood of the target region are determined. Based on the timing slacks of the current cells, at least one of the current cells is moved to a different location to create sufficient open space to place the ECO cell within the target region.
    Type: Grant
    Filed: February 16, 2021
    Date of Patent: December 27, 2022
    Assignee: Synopsys, Inc.
    Inventor: Nahmsuk Oh
  • Patent number: 11537157
    Abstract: A power supply is disclosed for an industrial control system or any system including a distributed power supply network. In embodiments, the power supply comprises: a battery module including a battery cell and a battery monitor configured to monitor the battery cell; and a self-hosted server operatively coupled with the battery module, the self-hosted server being configured to receive diagnostic information from the battery monitor and provide network access to the diagnostic information. In implementations, the diagnostics stored by the self-hosted server can be broadcast to or remotely accessed by enterprise control/monitoring systems, application control/monitoring systems, or other remote systems via a secured network (e.g., secured access cloud computing environment).
    Type: Grant
    Filed: April 7, 2020
    Date of Patent: December 27, 2022
    Assignee: Bedrock Automation Platforms, Inc.
    Inventors: Albert Rooyakkers, James G. Calvin
  • Patent number: 11537774
    Abstract: An optimized reconfiguration algorithm based on dynamic voltage and frequency scaling (DVFS) is provided, which mainly has the following contributions. The optimized reconfiguration algorithm based on DVFS proposes a DVFS-based reconfiguration method, which schedules user tasks according to a degree of parallelism (DOP) of the user tasks so as to reconfigure more parallel user tasks, thereby achieving higher reliability. The optimized reconfiguration algorithm based on DVFS proposes a K-means-based heuristic approximation algorithm, which minimizes the delay of the DVFS-based reconfiguration scheduling algorithm. The optimized reconfiguration algorithm based on DVFS proposes a K-means-based method, which reduces memory overhead caused by DVFS-based reconfiguration scheduling. The optimized reconfiguration algorithm based on DVFS improves the reliability of a field programmable gate array (FPGA) system and minimizes the area overhead of a hardware circuit.
    Type: Grant
    Filed: June 9, 2021
    Date of Patent: December 27, 2022
    Assignee: SHANGHAITECH UNIVERSITY
    Inventors: Rui Li, Yajun Ha
  • Patent number: 11531800
    Abstract: Methods and systems for verifying a hardware design for a component that evaluates a main algebraic expression comprising at least two variables wherein the main algebraic expression is representable as a lossless combination of a plurality of sub-algebraic expressions, and one or more of the at least two variables can be constrained to cause an instantiation of the hardware design to evaluate each of the sub-algebraic expressions.
    Type: Grant
    Filed: October 14, 2021
    Date of Patent: December 20, 2022
    Assignee: Imagination Technologies Limited
    Inventors: Sam Elliott, Rachel Edmonds
  • Patent number: 11531797
    Abstract: A system and method for performing operating state analysis of an integrated circuit (IC) design is disclosed. The method includes simulating a switching operation from a first operating state to a second operating state for one or more cells of the IC design using a plurality of vectors corresponding to one or more user-specified constraints. The method include generating a time-based waveform for each cell of the one or more cells changing an operating state from the first operating state to the second operating state, and based on the generated time-based waveform, identifying one or more operating state changes corresponding to the operating state analysis and associated timing window and cell information. The method includes verifying the one or more operating state changes by the each cell of the one or more cells of the IC design meet the one or more user-specified constraints for generating an analysis report.
    Type: Grant
    Filed: April 16, 2021
    Date of Patent: December 20, 2022
    Assignee: Synopsys, Inc.
    Inventors: Youxin Gao, Qing Su, Mayur Bubna
  • Patent number: 11526643
    Abstract: Formal verification methods are used to solve a valid model of a design-under-test (DUT) to enumerate valid coverage points based on an architectural specification of the DUT. A formal solver can be queried to solve for valid solutions by crossing one or more fields of a variable. After each valid solve, values of the variable fields can be recorded and a count for number of valid solutions can be incremented. A new rule can be added to the solving process after each valid solve to invalidate the recorded values of the variable fields for subsequent solves. The count for the number of valid solutions can provide a running total of the valid solutions found for the query. Results of the query can be processed to convert the recorded values to provide the enumerated coverage points. The enumerated coverage points can be converted to test cases for running simulations on the DUT.
    Type: Grant
    Filed: March 29, 2021
    Date of Patent: December 13, 2022
    Assignee: Amazon Technologies, Inc.
    Inventor: Todd Swanson
  • Patent number: 11527901
    Abstract: Provided is a method of controlling a battery pack, and a battery pack controlled by the method. A battery pack includes a plurality of slave battery modules, each of the slave battery modules including a battery that includes at least one battery cell and a slave controller that is configured to control charge and discharge of the battery, a master battery module including a master controller that is configured to control the slave controller, and a communication cable having formed thereon a first port to which the master controller is connected and a plurality of second ports to which the slave controller is connected. The first port includes an identification terminal configured to output an identification signal which is an electrical signal corresponding to the number of the second ports. A method of controlling the battery pack is provided.
    Type: Grant
    Filed: January 22, 2018
    Date of Patent: December 13, 2022
    Assignee: Samsung SDI Co., Ltd.
    Inventors: Youngjin Lee, Jaeseung Kim, Gilchoun Yeom, Kwanil Oh, Hyeoncheol Jeong, Seunglim Choi
  • Patent number: 11526642
    Abstract: An implementation-quality synthesis process begins with a logical design of an integrated circuit and, through a series of steps, generates a fully synthesized physical design of the integrated circuit. One of the steps is clock synthesis, which generates the clock network for the integrated circuit. In certain embodiments, a method includes the following steps. A reduced clock synthesis process is applied, rather than the implementation-quality clock synthesis process. This generates a clock network for the logical design, which will be referred to as a proxy clock network because it is used as a proxy to estimate power consumption of the fully synthesized clock network. Because the reduced clock synthesis process runs much faster than the implementation-quality clock synthesis process, the front end designer may use these power estimates in the front end design process, including to explore different design variations in the logical design.
    Type: Grant
    Filed: March 23, 2021
    Date of Patent: December 13, 2022
    Assignee: Synopsys, Inc.
    Inventors: Min Pan, Feng Sheng, Anand Kumar Rajaram
  • Patent number: 11522379
    Abstract: Disclosed is an electronic device. The electronic device may include a plurality of interfaces each of which is connected to one peripheral electronic device in a wired manner to deliver power to the connected peripheral electronic device, a power supply circuit connected to the plurality of interfaces, and a control circuit including a plurality of pins each connected to one interface to allow the power supply circuit to supply power to the plurality of interfaces. In addition, various embodiments understood from the disclosure are possible.
    Type: Grant
    Filed: February 12, 2018
    Date of Patent: December 6, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Min Young Lee, Cheol Ho Lee, Cheol Yoon Chung