Abstract: In one embodiment, the present invention includes an apparatus having an estimation logic to estimate a dynamic capacitance of a processor circuit of a processor during a plurality of processor cycles, a power gate calculator to calculate a control value for a power gate circuit coupled to a load line and between a voltage regulator and the processor circuit based on the dynamic capacitance estimate, and a controller to control an impedance of the power gate circuit based on the control value. Other embodiments are described and claimed.

Abstract: In one embodiment, a method includes receiving data corresponding to a set of sensor values and one or more indicators that each correspond to one of a number of physical states of a client device. The client device includes a first and second set of sensors. The method also includes generating a number of functions that each determine a probability that the client device is in a respective one of the physical states. The determination includes correlating the set of sensor values with a corresponding physical state of the client device. A first function of the number of functions is based on sensor values of the first set of sensors. A second function of the number of functions is based on sensor values of the second set of sensors. The method also includes sending the number of functions to the client device.

Abstract: A time manager controls one or more timing functions on a circuit. The time manager includes a data storage and a time calculator. The data storage device stores a first indication of a performance characteristic of a memory cell at a first time. The data storage device also stores a second indication of the performance characteristic of the memory cell at a second time. The time calculator is coupled to the data storage device. The time calculator calculates a time duration between the first time and the second time based on a change in the performance characteristic of the memory cell from the first indication to the second indication.

Abstract: A hop count between a management device and a management target device is calculated, and a notification destination range of an unspecified notification pertaining to a power supply mode is obtained from the management target device. On the basis of the obtained results, it is determined whether or not an unspecified notification pertaining to the power supply mode can be received from the management target device. Furthermore, on the basis of the result of the determination, the management device requests the management target device to register the management device as an individual notification destination.

Abstract: A model-based virtual power management driven multi-chip system simulator generates utilization data and performance data with a workload model that models one or more types of workloads based on parameters that characterize the one or more types of workloads. The simulator generates thermal data and power consumption data with a power model that models power consumption at a chip-level and a system-level. The simulator then generates performance counter information with a performance model that models change of performance counters over time and at least one of the generated utilization data and the generated performance data as input to the performance model. The simulator provides this generated data as input to a driver of the simulator.

Abstract: An electronic device comprising a connecting section; a first IF circuit that communicates through the connecting section with an external device connected via the connecting section, at a first communication speed; a second IF circuit that communicates through the connecting section with the external device, at a communication speed that is higher than the first communication speed; and a control section that, when one of the first IF circuit and the second IF circuit is selected as an IF circuit to be used for communication, limits a power supply to the other IF circuit.

Abstract: Various aspects of the present disclosure provide for a system that is able to boot from a variety of media that can be connected to the system, including SPI NOR and SPI NAND memory, universal serial bus (“USB”) devices, and devices attached via PCIe and Ethernet interfaces. When the system is powered on, the system processor is held in a reset mode, while a microcontroller in the system identifies an external device to be booted, and then copies a portion of boot code from the external device to an on-chip memory. The microcontroller can then direct the reset vector to the boot code in the on-chip memory and brings the system processor out of reset. The system processor can execute the boot code in-place on the on-chip memory, which initiates the system memory and the second stage boot loader.

Abstract: A method for controlling a sensor includes steps of: sensing an object for determining whether the object is within a sensing range of the sensor; if it is determined that the object is not within the sensing range, the sensor is turned into a non-active mode for a predicted non-active time, wherein the predicted non-active time is calculated based on a predetermined or a historical non-active time; sensing the object for determining whether the object is within the sensing range during the predicted non-active time; and if it is determined that the object is not within the sensing range during the predicted non-active time, the sensor is turned into a sleep mode for an predicted sleep time, wherein the predicted sleep time is calculated based on the predetermined non-active time and a predetermined sleep time, or is calculated based on the historical non-active time and a historical sleep time.

Abstract: In one embodiment, the present invention includes a processor having multiple cores to independently execute instructions, a first sensor to measure a first power consumption level of the processor based at least in part on events occurring on the cores, and a hybrid logic to combine the first power consumption level and a second power consumption level. Other embodiments are described and claimed.

Abstract: In one embodiment, a computer system provides a process for executing software that cannot be executed in a first configuration. The computer system determines source media for the software stored in a first data store, the source media being in the first configuration. The computer system retrieves metadata relating to executing the software from the source media. The computer system next transforms the retrieved metadata to generate a second configuration of the source media according to a transformation rule set, where the software can be executed in the second configuration, and stores the transformed metadata in a second data store. Next, the computer system presents the second configuration of the source media based on the transformed metadata. Thereafter, the computer system satisfies a request relating to executing the software using the transformed metadata in the second data store, wherein the request is satisfied based on the second configuration.

Abstract: An apparatus and method for reducing current consumption in a portable terminal are provided, in which upon generation of a task, a controller transitions to a Virtual Maximum Clock (VMC) level and changes a clock level from the VMC level according to a load state of the controller, to process the task. Moreover, the controller changes the clock level by at least one of transition from the VMC level to an RMC level, a stepwise increase from the VMC level, a stepwise decrease from the VMC level, and a hold at the VMC level, according to the load state of the controller.

Abstract: A communication terminal is described comprising a modem; a first memory configured to store configuration data for the modem; a second memory configured to store a system boot firmware; and a processor configured to execute the system boot firmware and to read the configuration data from the memory and provide it for the modem under the control of the system boot firmware.

Abstract: A method and apparatus for optimizing a configuration memory of a reconfigurable processor is provided. The method of optimizing the configuration memory of the reconfigurable processor includes analyzing parallelism of a loop of a program code based on an architecture of the reconfigurable processor and information regarding the configuration memory, scheduling groups of function units (FUs) to be activated in each cycle of the loop based on the analyzed parallelism, generating configuration data of each cycle, and determining a memory mapping to store the generated configuration data in the configuration memory.

Abstract: The present invention relates to methods and systems for providing reliable power to a storage device, such as a network attached storage. In one embodiment, the storage device employs a redundant power backplane design using a DC-to-DC converter per drive in the backplane. Each drive is thus provided its own independent power interface to the power backplane. One embodiment may employ DC-to-DC converters having integrated N-channel MOSFETs to provide overcurrent and thermal protection. In addition, an embodiment may employ a staggered startup procedure to manage peak power draw.

Abstract: In one embodiment, a method includes receiving data corresponding to a set of sensor values and one or more indicators that each correspond to one of a number of physical states of a client device. The client device includes a first and second set of sensors. The method also includes generating a number of functions that each determine a probability that the client device is in a respective one of the physical states. The determination includes correlating the set of sensor values with a corresponding physical state of the client device. A first function of the number of functions is based on sensor values of the first set of sensors. A second function of the number of functions is based on sensor values of the second set of sensors. The method also includes sending the number of functions to the client device.

Abstract: A step down unit steps down an external power supply voltage Vcc. A bias current control circuit controls the magnitude of bias current flowing through an auxiliary path connecting an output node and the ground. A system controller increases the magnitude of the bias current, prior to a change of the operation state of a load circuit by which a relatively large change occurs to the amount of current consumed by the load circuit including a central processing unit.

Abstract: An information handling system includes battery packs, loads, and a power management module operable to set an output voltage of a battery pack and direct power from the battery pack to one or more loads. The power management module can direct power from multiple batteries to a load simultaneously. A battery pack includes a converter circuit to convert the voltage provided by battery cells within the battery pack to a voltage set by a power management module.

Abstract: A scalability algorithm causes a processor to initialize a performance indicator counter, operate at an initial frequency of the first clock signal for a first duration, and determine, based on the performance indicator counter, an initial performance of the first processing core. The algorithm may then cause the processor to operate at a second frequency of the first clock signal for a second duration and determine, based on the performance indicator counter, a second performance of the first processing core. A performance scalability of the first processing core may be determined based on the initial performance and the second performance and an operational parameter, such as one or more clock frequencies and/or supply voltage(s), may be changed based on the determined scalability.

Abstract: A processor is described having a semiconductor chip having non volatile storage circuitry. The non volatile storage circuitry has information identifying a maximum operational frequency of the processor at which the processor's operation is guaranteed for an ambient temperature that corresponds to an extreme thermal event.

Abstract: Methods and apparatuses for re-instantiating a firmware environment that includes one or more firmware functions available at pre-boot time when transitioning the computing device from a wake state to a sleep state. A network event received by the computing device while in a sleep state may be handled by the firmware environment independent of the operating system and without returning the entire computing device to the wake state.