Patents Examined by Molly K Reida
  • Patent number: 10847669
    Abstract: A photodetection element includes: a photoelectric conversion structure that contains a first material having an absorption coefficient higher than an absorption coefficient of monocrystalline silicon for light of a first wavelength, for which monocrystalline silicon exhibits absorption, and generates positive and negative charges by absorbing a photon; and an avalanche structure that includes a monocrystalline silicon layer, in which avalanche multiplication occurs as a result of injection of at least one selected from the group consisting of the positive and negative charges from the photoelectric conversion structure. The first material includes at least one selected from the group consisting of an organic semiconductor, a semiconductor-type carbon nanotube, and a semiconductor quantum dot.
    Type: Grant
    Filed: August 7, 2020
    Date of Patent: November 24, 2020
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventor: Katsuya Nozawa
  • Patent number: 10847362
    Abstract: A method of fabricating a semiconductor device, the method including forming semiconductor patterns on a substrate such that the semiconductor patterns are vertically spaced apart from each other; and forming a metal work function pattern to fill a space between the semiconductor patterns, wherein forming the metal work function pattern includes performing an atomic layer deposition (ALD) process to form an alloy layer, and the ALD process includes providing a first precursor containing an organoaluminum compound on the substrate, and providing a second precursor containing a vanadium-halogen compound on the substrate.
    Type: Grant
    Filed: October 10, 2018
    Date of Patent: November 24, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Gyu-Hee Park, Yangsun Park, Jaesoon Lim, Younjoung Cho
  • Patent number: 10847603
    Abstract: In a capacitor of an integrated circuit, a crystallization induction film is obtained by oxidizing a surface of an electrode, and a dielectric structure is formed on the crystallization induction film, to reduce defect density generated in the dielectric film, improve leakage current, and reduce equivalent oxide thickness.
    Type: Grant
    Filed: March 22, 2019
    Date of Patent: November 24, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sun-min Moon, Su-hwan Kim, Hyun-jun Kim, Seong-yul Park, Young-lim Park, Jae-wan Chang
  • Patent number: 10840386
    Abstract: A semiconductor apparatus has a semiconductor substrate, a first trench provided in a front surface of the semiconductor substrate, an anode electrode provided inside the first trench, and a cathode electrode provided on a back surface of the semiconductor substrate. The semiconductor substrate has a first p-type region, a second p-type region, and a main n-type region which is in contact with the first p-type region and the second p-type region, and is in Schottky contact with the anode electrode in the side surface of the first trench. The semiconductor substrate satisfies the relationship that an area of the first trench, when the front surface is viewed in a plan view, is smaller than an area of a Schottky interface where the main n-type region is in contact with the anode electrode in the side surface of the first trench.
    Type: Grant
    Filed: November 28, 2017
    Date of Patent: November 17, 2020
    Assignees: TOYOTA JIDOSHA KABUSHIKI KAISHA, DENSO CORPORATION
    Inventors: Hiroki Miyake, Yasushi Urakami, Yusuke Yamashita
  • Patent number: 10840135
    Abstract: Advanced flat metals for microelectronics are provided. While conventional processes create large damascene features that have a dishing defect that causes failure in bonded devices, example systems and methods described herein create large damascene features that are planar. In an implementation, an annealing process creates large grains or large metallic crystals of copper in large damascene cavities, while a thinner layer of copper over the field of a substrate anneals into smaller grains of copper. The large grains of copper in the damascene cavities resist dishing defects during chemical-mechanical planarization (CMP), resulting in very flat damascene features. In an implementation, layers of resist and layers of a second coating material may be applied in various ways to resist dishing during chemical-mechanical planarization (CMP), resulting in very flat damascene features.
    Type: Grant
    Filed: September 6, 2019
    Date of Patent: November 17, 2020
    Assignee: Invensas Corporation
    Inventor: Cyprian Emeka Uzoh
  • Patent number: 10840153
    Abstract: A method includes providing a structure having a first region and a second region, the first region including a first channel region, the second region including a second channel region; forming a gate stack layer over the first and second regions; patterning the gate stack layer, thereby forming a first gate stack over the first channel region and a second gate stack over the second channel region; and laterally etching bottom portions of the first and second gate stacks by applying different etchant concentrations to the first and second regions simultaneously, thereby forming notches at the bottom portions of the first and second gate stacks.
    Type: Grant
    Filed: October 16, 2018
    Date of Patent: November 17, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chang-Yin Chen, Che-Cheng Chang, Chih-Han Lin
  • Patent number: 10833130
    Abstract: A display device according to an embodiment of the present invention includes first and second electroluminescent elements on a substrate. The first and second electroluminescent elements each include a lower electrode, a functional layer including a light-emitting layer, an upper electrode, and a first or second color filter. The display device includes an overlapping region where the first and second color filters overlap each other in a plan view. Light transmitted through the first color filter has a higher luminosity factor than light transmitted through the second color filter. L2>L1, wherein L2 is the distance between the light-emitting region of the second electroluminescent element and the second color filter, and L1 is the distance between the light-emitting region of the first electroluminescent element and the first color filter.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: November 10, 2020
    Assignee: Canon Kabushiki Kaisha
    Inventors: Koji Ishizuya, Tetsuo Takahashi
  • Patent number: 10832969
    Abstract: Semiconductor devices and methods of forming the same include forming a dummy gate over a fin, which has a lower semiconductor layer, an insulating intermediate layer, and an upper semiconductor layer, to establish a channel region and source/drain regions. Source/drain extensions are grown on the lower semiconductor layer. Source/drain extensions are grown on the upper semiconductor layer. The dummy gate is replaced with a gate stack.
    Type: Grant
    Filed: October 15, 2018
    Date of Patent: November 10, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Xin Miao, Choonghyun Lee, Shogo Mochizuki, Hemanth Jagannathan
  • Patent number: 10825726
    Abstract: A method and structure of forming an interconnect structure with a sidewall image transfer process such as self-aligned double patterning to reduce capacitance and resistance. In these methods and structures, the spacer is a metal.
    Type: Grant
    Filed: October 16, 2018
    Date of Patent: November 3, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Hsueh-Chung Chen, James J. Kelly, Yann Mignot, Cornelius Brown Peethala, Lawrence A. Clevenger
  • Patent number: 10818579
    Abstract: There is provided a lead frame. The lead frame includes: a die pad; a lead terminal that is separated from the die pad and disposed around the die pad; and a resin layer that is formed between the die pad and the lead terminal so as to fix the die pad and the lead terminal. The resin layer has an opening portion that exposes at least a lower surface of the lead terminal.
    Type: Grant
    Filed: October 15, 2018
    Date of Patent: October 27, 2020
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Shintaro Hayashi, Kentaro Kaneko, Tsukasa Nakanishi, Misaki Imai
  • Patent number: 10818681
    Abstract: In an example, a method of forming a stacked memory array includes, forming a termination structure passing through a stack of alternating first and second dielectrics in a first region of the stack; forming first and second sets of contacts through the stack of alternating first and second dielectrics in a second region of the stack concurrently with forming the termination structure; forming an opening through the stack of alternating first and second dielectrics between the first and second sets of contacts so that the opening terminates at the termination structure; and removing the first dielectrics from the second region by accessing the first dielectrics through the opening so that the first and second sets of contacts pass through the second dielectrics alternating with spaces corresponding to the removed first dielectrics.
    Type: Grant
    Filed: October 15, 2018
    Date of Patent: October 27, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Yi Hu, Jian Li, Lifang Xu, Xiaosong Zhang
  • Patent number: 10811257
    Abstract: A method may include depositing a carbon layer on a substrate using physical vapor deposition, wherein the carbon layer exhibits compressive stress, and is characterized by a first stress value; and directing a dose of low-mass species into the carbon layer, wherein, after the directing, the carbon layer exhibits a second stress value, less compressive than the first stress value.
    Type: Grant
    Filed: June 4, 2018
    Date of Patent: October 20, 2020
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Rajesh Prasad, Tzu-Yu Liu, Kyu-Ha Shim, Tom Ho Wing Yu, Zhong Qiang Hua, Adolph Miller Allen, Viabhav Soni, Ravi Rajagopalan, Nobuyuki Sasaki
  • Patent number: 10797207
    Abstract: Light emitting devices (LEDs) are described. An LED includes a light emitting semiconductor structure that includes a light emitting active layer disposed between an n-layer and a p-layer. A wavelength converting material may be disposed adjacent the light emitting semiconductor structure. The wavelength converting material includes multiple pores, at least one of which contains a second material. An absolute value of a ratio of a coefficient of thermal expansion of the second material to a coefficient of thermal expansion of the wavelength converting material is at least two in an embodiment, at least ten in another embodiment, at least 100 in another embodiment, and at least 1,000 in yet another embodiment.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: October 6, 2020
    Assignee: LUMILEDS LLC
    Inventors: Daniel Estrada, Marcel Rene Bohmer, Jacobus Johannes Francisus Gerardus Heuts, Kentaro Shimizu, Michael David Camras
  • Patent number: 10790339
    Abstract: Provided are an OLED array substrate and a manufacturing method thereof, and a display device. The OLED array substrate includes a substrate and a plurality of pixel units provided thereon. The plurality of pixel units are arranged into a plurality of rows extending in a first direction and a plurality of columns extending in a second direction. Each pixel unit includes a plurality of subpixels emitting light of different colors. At least two subpixels emitting light of the same color are adjacent to each other in at least one of the first direction and the second direction.
    Type: Grant
    Filed: February 24, 2018
    Date of Patent: September 29, 2020
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Zhongying Yang, Jianpeng Wu, Yinan Liang
  • Patent number: 10777699
    Abstract: A photodetection element includes: a photoelectric conversion structure that contains a first material having an absorption coefficient higher than an absorption coefficient of monocrystalline silicon for light of a first wavelength, for which monocrystalline silicon exhibits absorption, and generates positive and negative charges by absorbing a photon; and an avalanche structure that includes a monocrystalline silicon layer, in which avalanche multiplication occurs as a result of injection of at least one selected from the group consisting of the positive and negative charges from the photoelectric conversion structure. The first material includes at least one selected from the group consisting of an organic semiconductor, a semiconductor-type carbon nanotube, and a semiconductor quantum dot.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: September 15, 2020
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventor: Katsuya Nozawa
  • Patent number: 10777575
    Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory stack structures extending through the alternating stack, drain-select-level trenches that vertically extend through at least one drain-select-level electrically conductive layer and laterally extend along a first horizontal direction and divide each drain-select-level electrically conductive layer into multiple drain-select-level electrically conductive strips, and pairs of vertical conductive strips located within a respective one of the drain-select-level trenches. Each of the vertical conductive strips has a pair of vertical straight sidewalls that laterally extends along the first horizontal direction. Each drain-select-level electrode may have at least one drain-select-level electrically conductive layer and at least one vertical conductive strip.
    Type: Grant
    Filed: March 22, 2019
    Date of Patent: September 15, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Zhixin Cui, Kiyohiko Sakakibara, Yanli Zhang
  • Patent number: 10777559
    Abstract: A semiconductor memory device includes a semiconductor substrate, bit line structures, storage node contacts, isolation structures, a first spacer, a second spacer, and a third spacer. Each bit line structure is elongated in a first direction. The bit line structures are repeatedly arranged in a second direction. Each storage node contact and each isolation structure are disposed between two adjacent bit line structures. The first spacer is partly disposed between each isolation structure and the bit line structure adjacent to the isolation structure and partly disposed between each storage node contact and the bit line structure adjacent to the storage node contact. The second spacer is disposed between each storage node contact and the first spacer. The third spacer is disposed between each storage node contact and the second spacer. A thickness of the third spacer is less than a thickness of the second spacer in the second direction.
    Type: Grant
    Filed: March 22, 2019
    Date of Patent: September 15, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Po-Han Wu, Feng-Yi Chang, Fu-Che Lee, Wen-Chieh Lu
  • Patent number: 10763355
    Abstract: A semiconductor device may include: a semiconductor layer; and a trench gate. The semiconductor layer may include: a first semiconductor region of a first conductive type; a second semiconductor region of a second conductive type provided above the first semiconductor region and facing a side surface of the trench gate; and a third semiconductor region of the first conductive type provided above the second semiconductor region, separated from the first semiconductor region by the second semiconductor region, and facing the side surface of the trench gate. The first semiconductor region may include: a lower semiconductor region; and an upper semiconductor region disposed between the lower semiconductor region and the second semiconductor region and having a lower impurity concentration than the lower semiconductor region. The upper semiconductor region may be disposed at a shallower position than the trench gate and face the side surface of the trench gate.
    Type: Grant
    Filed: March 22, 2019
    Date of Patent: September 1, 2020
    Assignee: KABUSHIKI KAISHA TOYOTA CHUO KENKYUSHO
    Inventors: Tsutomu Uesugi, Masakazu Kanechika
  • Patent number: 10763429
    Abstract: Embodiments of the present invention are directed to a method for fabricating a magnetoresistive random access memory (MRAM) device. A non-limiting example of the method includes depositing a dielectric layer on a contact arranged on a substrate including a magnetic tunnel junction (MTJ) pillar. The method includes reducing a width of the MTJ pillar. The method further includes depositing an encapsulation layer on the dielectric layer and the MTJ pillar.
    Type: Grant
    Filed: October 12, 2018
    Date of Patent: September 1, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Steve Holmes, Bruce B. Doris, Hyun K. Lee
  • Patent number: 10763107
    Abstract: Methods and apparatuses suitable for encapsulation layers for memory devices at temperatures less than about 300° C. are provided herein. Methods involve introducing a reactive species by pulsing plasma while exposing a substrate to deposition reactants, and post-treating deposited encapsulation films to densify and reduce hydrogen content. Post-treatment methods include periodic exposure to inert plasma without reactants and exposure to ultraviolet radiation at a substrate temperature less than about 300° C.
    Type: Grant
    Filed: January 10, 2020
    Date of Patent: September 1, 2020
    Assignee: Lam Research Corporation
    Inventors: Bart J. van Schravendijk, Akhil Singhal, Joseph Hung-chi Wei, Bhadri N. Varadarajan, Kevin M. McLaughlin, Casey Holder, Ananda K. Banerji