Patents Examined by Molly K Reida
  • Patent number: 10644129
    Abstract: A method is presented for performing a gate cut in a field effect transistor (FET) structure. The method includes forming a plurality of fins and at least one insulating pillar over a semiconductor substrate, depositing a first work function metal layer, removing the first work function metal layer from a first set of fins, depositing a second work function metal layer, depositing a conductive material over the second work function metal layer, forming at least one gate trench through the conductive material and adjacent the first set of fins to separate active gate regions, and filling the at least one gate trench with an insulating material.
    Type: Grant
    Filed: October 11, 2019
    Date of Patent: May 5, 2020
    Assignee: International Business Machines Corporation
    Inventors: Ruqiang Bao, Siva Kanakasabapathy, Andrew M. Greene
  • Patent number: 10643944
    Abstract: A first conductive routing structure is electrically connected to a first electronic component. A second conductive routing structure is electrically connected to a second electronic component. An additive deposition process deposits a material over a surface of a processed wafer to form a conductive or resistive structure, which extends from a portion of the first conductive routing structure to a portion of the second conductive routing structure, to configure a circuit including the first and second electronic components.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: May 5, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Paul Merle Emerson, Benjamin Stassen Cook
  • Patent number: 10636750
    Abstract: A semiconductor device which includes a substrate having integrated circuits; and metallization layers on the substrate, the metallization layers having a peripheral region adjacent to a kerf region of the semiconductor device and containing a crack stop structure. The crack stop structure includes a bottom portion containing a plurality of the metallization layers connected by vias with each metallization layer decreasing in width in a step pyramid structure from a bottom of the bottom portion to a top of the bottom portion; and a top portion containing a top metallization layer of the metallization layers connected to the bottom portion, the top metallization layer being wider than a top-most metallization layer of the bottom portion and having a segment that extends toward the kerf region so as to create an overhang with respect to the bottom portion.
    Type: Grant
    Filed: October 15, 2018
    Date of Patent: April 28, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Shidong Li, Kirk D. Peterson, Nicolas Pizzuti, Thomas M. Shaw, Thomas A. Wassick
  • Patent number: 10629612
    Abstract: A memory device includes first to third electrode layers and first to third columnar bodies. The first electrode layers are stacked above a foundation layer. The second and third electrode layers are arranged above the first electrode layers in a direction crossing a stacking direction of the first electrode layers. The first columnar body extends through the first and second electrode layers. The second columnar body extends through the first and third electrode layers. The third columnar body extends through the first electrode layers, and is positioned between the second electrode layer and the third electrode layer. The first to third columnar bodies include first to third semiconductor layers, respectively. The first and second semiconductor layers are electrically connected to the foundation layer, and the third semiconductor layer is electrically insulated from the foundation layer by an insulating film provided between the foundation layer and the third semiconductor layer.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: April 21, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Takamasa Okawa, Tetsuji Kunitake, Takuji Kanebishi, Yusuke Takagi
  • Patent number: 10629700
    Abstract: An embodiment is a method of semiconductor processing. The method includes depositing a high-k gate dielectric layer over a semiconductor fin. A barrier layer is deposited over the high-k gate dielectric layer. A silicon passivation layer is deposited over the barrier layer. A nitrogen treatment is performed on the silicon passivation layer. A capping layer is deposited over the silicon passivation layer. The capping layer is annealed.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: April 21, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chien-Shun Liao, Huai-Tei Yang, Wang Chun-Chieh, Yueh-Ching Pai, Chun-I Wu
  • Patent number: 10573683
    Abstract: A light-emitting diode (LED) chip includes a substrate, a conductive layer, a first insulator layer, a light-emitting component, and an ESD protection component. The conductive layer is disposed on the substrate. The first insulator layer is disposed on the conductive layer and has a first opening and a second opening. The light-emitting component is disposed on the first insulator layer and includes a first semiconductor layer, a first quantum well layer, and a second semiconductor layer. The ESD protection component is disposed on the first insulator layer and separated from the light-emitting component. The ESD protection component includes a third semiconductor layer, a second quantum well layer, and a fourth semiconductor layer. The second quantum well layer is disposed between the third and fourth semiconductor layers. The first and fourth semiconductor layers are electrically isolated from each other before packaging the LED chip.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: February 25, 2020
    Assignee: LEXTAR ELECTRONICS CORPORATION
    Inventor: Shiou-Yi Kuo
  • Patent number: 10566386
    Abstract: A method of manufacturing a variable memory device includes forming a switching layer on a first conductive layer, forming a heating layer on the switching layer, the heating layer extending in a first direction, performing a first patterning process on the first conductive layer, the switching layer, and the heating layer to form a first trench extending in a second direction intersecting the first direction, forming variable resistance patterns on the heating layer, forming a second conductive layer on the variable resistance patterns, and performing a second patterning process on the switching layer, the heating layer, and the second conductive layer to form a second trench extending in the first direction and being between the variable resistance patterns.
    Type: Grant
    Filed: May 29, 2018
    Date of Patent: February 18, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Ji-Hyun Jeong
  • Patent number: 10566186
    Abstract: Methods and apparatuses suitable for depositing low hydrogen content, hermetic, thin encapsulation layers at temperatures less than about 300° C. are provided herein. Methods involve pulsing plasma while exposing a substrate to deposition reactants, and post-treating deposited encapsulation films to densify and reduce hydrogen content. Post-treatment methods include periodic exposure to inert plasma without reactants and exposure to ultraviolet radiation at a substrate temperature less than about 300° C.
    Type: Grant
    Filed: November 2, 2018
    Date of Patent: February 18, 2020
    Assignee: Lam Research Corporation
    Inventors: Bart J. van Schravendijk, Akhil Singhal, Joseph Hung-chi Wei, Bhadri N. Varadarajan, Kevin McLaughlin, Casey Holder, Ananda Banerji
  • Patent number: 10566296
    Abstract: In the invention described, magnetic field characteristics of randomly placed magnetized particles are exploited by using the magnetic field fluctuations produced by the particles as measured by a sensor. The magnetized particles generate a complex magnetic field near the surface of an integrated circuit chip on a bank card or identification card that can be used as a “fingerprint.” The positioning and orientation of the magnetized particles is an uncontrolled process, and thus the interaction between the sensor and the particles is complex. The randomness of the magnetic field magnitude and direction near the surface of the material containing the magnetic particles can be used to obtain a unique identifier for an item such as an integrated circuit chip on a bank card or identification card carrying the PUF.
    Type: Grant
    Filed: November 10, 2017
    Date of Patent: February 18, 2020
    Assignee: Lexmark International, Inc.
    Inventors: Roger Steven Cannon, William Corbett, Gary A. Denton, James Paul Drummond, Kelly Ann Killeen, Carl E. Sullivan
  • Patent number: 10553700
    Abstract: A method is presented for performing a gate cut in a field effect transistor (FET) structure. The method includes forming a plurality of fins and at least one insulating pillar over a semiconductor substrate, depositing a first work function metal layer, removing the first work function metal layer from a first set of fins, depositing a second work function metal layer, depositing a conductive material over the second work function metal layer, forming at least one gate trench through the conductive material and adjacent the first set of fins to separate active gate regions, and filling the at least one gate trench with an insulating material.
    Type: Grant
    Filed: May 29, 2018
    Date of Patent: February 4, 2020
    Assignee: International Business Machines Corporation
    Inventors: Ruqiang Bao, Siva Kanakasabapathy, Andrew M. Greene
  • Patent number: 10541178
    Abstract: A method of evaluating the quality of a thin film layer may include: forming the thin film layer on a substrate; applying a stress to the thin film layer; and evaluating the quality of the thin film layer. A device for evaluating the quality of the thin film layer may include a stress chamber for applying a stress to the thin film layer and a refractive index measuring unit for evaluating the quality of the thin film layer based on a rate of change of a refractive index.
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: January 21, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Xianyu Wenxu, Yongyoung Park, Kideok Bae, Wooyoung Yang, Changseung Lee
  • Patent number: 10541137
    Abstract: A method of doping a substrate. The method may include providing a substrate in a process chamber. The substrate may include a semiconductor structure, and a dopant layer disposed on a surface of the semiconductor structure. The method may include maintaining the substrate at a first temperature for a first interval, the first temperature corresponding to a vaporization temperature of the dopant layer. The method may further include rapidly cooling the substrate to a second temperature, less than the first temperature, and heating the substrate from the second temperature to a third temperature, greater than the first temperature.
    Type: Grant
    Filed: June 1, 2018
    Date of Patent: January 21, 2020
    Assignee: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.
    Inventors: Christopher R. Hatem, Piero Sferlazzo, Roger Fish, Dale K. Stone
  • Patent number: 10535751
    Abstract: Embodiments disclosed herein relate generally to forming a gate layer in high aspect ratio trenches using a cyclic deposition-treatment process. In an embodiment, a method includes subjecting a substrate surface having at least one feature to a film deposition process to form a conformal film over a bottom surface and along sidewall surfaces of the feature, subjecting the substrate surface to a treatment process to form respective halogen surface layers or respective halogen-terminated layers on the conformal film formed at respective upper portions of the sidewall surfaces, and performing sequentially and repeatedly the film deposition process and the treatment process to fill the feature with the film.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: January 14, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: De-Wei Yu, Chien-Hao Chen, Pin-Ju Liang, I-chen Yang
  • Patent number: 10522652
    Abstract: A semiconductor device and a method for fabricating the same are provided. A structure of the semiconductor device includes a substrate having a device region and an edge region. A plurality of device structures is formed on the substrate. An etching stop layer is disposed in the edge region of the substrate. The etching stop layer is converted from P-type dopants from an exposed surface layer of the substrate.
    Type: Grant
    Filed: September 12, 2018
    Date of Patent: December 31, 2019
    Assignee: United Microelectronics Corp.
    Inventors: Po-Wen Su, Chih-Wei Lin, Wei-Chih Lai, Tai-Yen Lin
  • Patent number: 10497826
    Abstract: A method of manufacturing a light emitting device that includes a plurality of light emitting parts is provided. The method includes providing a base member having a plurality of recesses; mounting at least one light-emitting element in each of the plurality of recesses; disposing a light-transmissive layer continuously covering the plurality of recesses; and removing portions of the light-transmissive layer on the lateral wall between adjacent recesses to expose corresponding portions of the lateral wall, to obtain a plurality of light-transmissive members.
    Type: Grant
    Filed: September 25, 2018
    Date of Patent: December 3, 2019
    Assignee: NICHIA CORPORATION
    Inventor: Takeo Kurimoto
  • Patent number: 10497716
    Abstract: Provided herein is a semiconductor device including: a channel layer; a data storage layer surrounding the channel layer and extending along the channel layer; interlayer insulating layers surrounding the data storage layer and stacked along the channel layer, wherein the interlayer insulating layers are spaced apart from each other, wherein a conductive area is disposed between the interlayer insulating layers; a conductive pattern disposed in the conductive area and surrounding the data storage layer; buffer patterns disposed between the interlayer insulating layers and the data storage layer and surrounding the data storage layer, wherein each of the buffer patterns includes a densified area, wherein the buffer patterns are separated from each other by the conductive area; and a blocking insulating pattern disposed between the conductive pattern and the data storage layer and surrounding the data storage layer.
    Type: Grant
    Filed: July 10, 2018
    Date of Patent: December 3, 2019
    Assignee: SK hynix Inc.
    Inventors: In Su Park, Ki Hong Lee, Hye Jeong Cheon
  • Patent number: 10490626
    Abstract: A semiconductor device with super junction and process for the same is disclosed. The semiconductor device includes a silicon substrate and a first conductive type epitaxial layer thereon, a plurality of second conductive type conductive pillars formed below an upper face of the first conductive type epitaxial layer, where the second conductive type conductive pillars are implanted with neutral element having predetermined amount. When the semiconductor device operates in a predetermined temperature, the releasing amount of the neutral element can completely or partially compensate the releasing amount of carrier of opposite polarity from the epitaxial layer for the second conductive type conductive pillars due to the predetermined temperature, thus prevent the degrade of endurance ability for the surge voltage.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: November 26, 2019
    Assignee: PFC DEVICE HOLDINGS LIMITED
    Inventor: Kuan-Yu Chen
  • Patent number: 10490621
    Abstract: Apparatus implementing various structures to decrease the distance between two inductive elements for tuning an inductance with greater variability (a wider tuning range). One example integrated circuit (IC) package generally includes a laminate, a solder resist layer disposed on an upper surface of the laminate, and a semiconductor die disposed above the laminate and comprising a first inductor. At least a portion of a second inductor is disposed above a section of the solder resist layer, the first inductor at least partially overlaps the second inductor, and there is a gap between the first inductor and the second inductor.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: November 26, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Paragkumar Ajaybhai Thadesar, Mario Francisco Velez, Changhan Hobie Yun, Francesco Carrara, Jonghae Kim, Xiaoju Yu, Niranjan Sunil Mudakatte
  • Patent number: 10490471
    Abstract: The present disclosure relates to a wafer-level packaging process. According to an exemplary process, a precursor wafer that includes a device layer with a number of input/output (I/O) contacts, a number of bump structures over the device layer, the stop layer underneath the device layer, and a silicon handle layer underneath the stop layer is provided. Herein, each bump structure is electronically coupled to a corresponding I/O contact. A first mold compound is then applied over the device layer to encapsulate each bump structure. Next, the silicon handle layer is removed substantially. A second mold compound is applied to an exposed surface from which the silicon handle layer was removed. Finally, the first mold compound is thinned down to expose a portion of each bump structure.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: November 26, 2019
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, Merrill Albert Hatcher, Jr., Peter V. Wright, Jon Chadwick
  • Patent number: 10483186
    Abstract: A first inner heat conductor may include a plurality of first graphite layers. A second inner heat conductor may include a plurality of second graphite layers. The plurality of first graphite layers may be stacked in a first direction which is orthogonal to a direction in which a semiconductor element and a first heat radiator are arranged. The plurality of second graphite layers may be stacked in the direction in which the semiconductor element and the first heat radiator are arranged, or may be stacked in a second direction which is orthogonal to the direction in which the semiconductor element and the first heat radiator are arranged and orthogonal to the first direction.
    Type: Grant
    Filed: October 15, 2018
    Date of Patent: November 19, 2019
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventor: Masataka Deguchi