Abstract: The present technology relates to a semiconductor memory device. The semiconductor memory device includes a plurality of channel plugs disposed in a cell region of a semiconductor substrate, a first dummy region and a second dummy region disposed at both end portions of the cell region, and first dummy plugs disposed in the first dummy region and second dummy plugs disposed in the second dummy region. A critical value of the first dummy plugs arranged in the first dummy region is different from a critical value of the second dummy plugs disposed in the second dummy region.

Abstract: According to one embodiment, a semiconductor memory device includes a first stacked body in which a plurality of first conductive layers are stacked at intervals in a first direction above a semiconductor substrate; a second stacked body in which a plurality of second conductive layers are stacked at intervals in the first direction above the semiconductor substrate; and a first slit extending in a second direction perpendicular to the first direction, the first slit isolating the first stacked body and the second stacked body in a third direction perpendicular to the first and second directions.

Abstract: A lift-off method includes a dividing step of dividing a buffer layer and an optical device layer stacked on a front side of a substrate to thereby form separate buffer layers and separate optical device layers, a transfer member bonding step of bonding a transfer member to a front side of the separate optical device layers, a buffer layer breaking step of applying a pulsed laser beam to the separate buffer layers to thereby break the separate buffer layers, and an optical device layer transferring step of transferring the separate optical device layers from the substrate to the transfer member. An energy density of each pulse of the pulsed laser beam is set to 1.0 to 5.0 mJ/mm2.

Abstract: An imaging device includes a semiconductor substrate including a first surface receiving light from outside, and a second surface opposite to the first surface, a first transistor on the second surface, and a photoelectric converter facing the second surface and receiving light through the semiconductor substrate. The semiconductor substrate is a silicon or silicon compound substrate. The photoelectric converter includes a first electrode electrically connected to the first transistor, a second electrode, and a photoelectric conversion layer located between the first and second electrodes and containing a material absorbing light having a wavelength 1.1 ?m or longer. The first electrode is located between the second surface and the photoelectric conversion layer. A spectral sensitivity of the material in a region of 1.0 ?m or longer and shorter than 1.1 ?m is 0% to 5% of the maximum value of a spectral sensitivity of the material in 1.1 ?m or longer.

Abstract: A method includes transferring a layer onto a flexible substrate, the layer being located in a stack on the front face of the substrate. The substrate includes at least one supplementary stack interposed between the stack and the bulk layer of the substrate. This supplementary stack includes at least two layers with thicknesses decreasing in the direction of the front face. The method makes provision, after bonding the flexible substrate on the front face, for successively and gradually removing the various layers of the substrate. Such gradualness makes it possible to transfer a thin layer of silicon, with a thickness of less than 50 nm, onto a flexible substrate.

Abstract: An image sensor includes a substrate including a first surface and a second surface, a first transmission gate electrode on the first surface of the substrate, a storage node on the first surface of the substrate and including a first storage gate electrode isolated from direct contact with the first transmission gate electrode, a dielectric layer on the first storage gate electrode, and a semiconductor layer on the dielectric layer. The image sensor may include a first cover insulating layer on the semiconductor layer and vertically overlapping the first transmission gate electrode, and an organic photoelectric conversion layer on an upper surface of the semiconductor layer and an upper surface of the first cover insulating layer.

Abstract: A method for increasing an oxide thickness at trench corner of an UMOSFET is provided, comprising providing an N-type substrate, and forming an N-type drift region, N-type and P-type heavily doped regions and P-type body therein. A trench is defined through lithography, and a pad oxide is formed along the trench through oxidation or deposition process. An oxidation barrier is formed upon the pad oxide. A thermal oxidation process is employed, so a corner oxide is effectively formed at the trench corner. After removing the pad oxide and oxidation barrier, various back-end processes are carried out to complete the transistor structure. The invention is aimed to increase oxide thickness near the trench bottom, and can be applied to high voltage devices, such as SiC. The conventional electric field crowding effect occurring at the trench corner is greatly solved, thus increasing breakdown voltages thereof.

Abstract: A display device may include a substrate in which an opening is defined, a first disconnected line disposed on the substrate, the first disconnected line extending along a first direction and including a first disconnected portion and a second disconnected portion, and the first disconnected portion and the second disconnected portion being disconnected from each other by the opening, and a first bypass line disposed on the substrate in a different layer from the first disconnected line, the first bypass line bypassing the opening and connecting the first disconnected portion and the second disconnected portion to each other.

Abstract: This application describes a light emitting device or an assembly of light emitting devices, each with a small footprint. The light emitting device comprises two transistors, a capacitor, and an LED. The transistors comprise single crystal semiconductor. The capacitor is vertically-oriented. The LED overlies the transistors and capacitor. Methods to form the light emitting device or assembly are discussed.

Abstract: The present disclosure relates to an array substrate and a method for manufacturing the array substrate. The array substrate includes a substrate having a display region and a peripheral region surrounding the display region, the display region including sub-pixels arranged in an array, and a plurality of thin film transistors located on the substrate, including a plurality of first thin film transistors located within the peripheral region and a second thin film transistor located within each sub-pixel of the display region, wherein there is a first distance in a row and/or column direction between first active layers of the first thin film transistors and second active layers of nearest neighbor second thin film transistors, and there is a second distance in a row and/or column direction between adjacent second active layers, wherein the first distance is substantially equal to the second distance.

Abstract: A semiconductor device and a method of manufacturing the semiconductor device are provided. The semiconductor device includes a source structure formed on a base, an etch prevention layer formed on the source structure, bit lines, a stack structure located between the etch prevention layer and the bit lines and including conductive layers and insulating layers that are alternately stacked on each other, and a channel structure passing through the stack structure and the etch prevention layer, wherein a lower portion of the channel structure is located in the source structure and a sidewall of the lower portion of the channel structure is in direct contact with the source structure.

Abstract: Implementations of semiconductor packages may include a metallic baseplate, a first insulative layer coupled to the metallic baseplate, a first plurality of metallic traces, each metallic trace of the first plurality of metallic traces coupled to the electrically insulative, one or more semiconductor devices coupled to each one of the first plurality of metallic traces, a second plurality of metallic traces coupled to the one or more semiconductor devices, and a second insulative layer coupled to the metallic traces of the second plurality of metallic traces.

Abstract: The present disclosure describes a method includes forming a fin structure including a fin base portion and a stacked fin portion on a substrate. The stacked fin portion includes a first semiconductor layer on the fin base portion, a second semiconductor layer above the first semiconductor layer, and a sacrificial semiconductor layer between the first and second semiconductor layers. The method further includes replacing the sacrificial semiconductor layer with a negative capacitance (NC) layer and forming gate electrodes around the NC layer, the first semiconductor layer, and the second semiconductor layer. The NC layer includes an NC dielectric material.

Abstract: A light emitting device includes a substrate, a plurality of light sources, a light reflecting member and a resin member. The substrate defines a through hole. The light reflecting member includes a wall part having a first surface and a second surface. The first surface defines a plurality of surrounding parts respectively surrounding each of the light sources individually or two or more of the light sources in groups. The second surface defines a hollow part. The resin member is disposed inside the hollow part. The hollow part defines a first opening on a substrate side of the wall part. The through hole defines a second opening positioned inner than the first opening. The resin member is continuously in contact with the second surface and the upper surface of the substrate in a region between a peripheral edge of the second opening and a peripheral edge of the first opening.

Abstract: A method includes forming a fin on a substrate, forming an insulating material over the fin, recessing the insulating material to form an isolation region surrounding the fin, wherein an upper portion of the fin protrudes above the isolation region, performing a trimming process to reduce a width of the upper portion of the fin, and forming a gate structure extending over the isolation region and the upper portion of the fin.

Abstract: In an example of forming a stacked memory array, a stack of alternating first and second dielectrics is formed. A dielectric extension is formed through the stack such that a first portion of the dielectric extension is in a first region of the stack between a first group of semiconductor structures and a second group of semiconductor structures in a second region of the stack and a second portion of the dielectric extension extends into a third region of the stack that does not include the first and second semiconductor structures. An opening is formed through the first region, while the dielectric extension couples the alternating first and second dielectrics in the third region to the alternating first and second dielectrics in the second region.

Abstract: An electronic integrated circuit chip includes a semiconductor substrate with a front side and a back side. A first reflective shield is positioned adjacent the front side of the semiconductor substrate and a second reflective shield is positioned adjacent the back side of the semiconductor substrate. Photons are emitted by a photon source to pass through the semiconductor substrate and bounce off the first and second reflective shields to reach a photon detector at the front side of the semiconductor substrate. The detected photons are processed in order to determine whether to issue an alert indicating the existence of an attack on the electronic integrated circuit chip.

Abstract: A thin film transistor, an array substrate, a display device and a method for manufacturing a thin film transistor are provided. The thin film transistor is formed on a base substrate and includes a source; a drain; and a semiconductor active layer having an amorphous silicon layer and one polysilicon portion or a plurality of polysilicon portions, the amorphous silicon layer being contacted with the one polysilicon portion or the plurality of polysilicon portions. The method includes a process of forming a source, a drain, and a semiconductor active layer: wherein forming a semiconductor active layer comprises: forming a first amorphous silicon thin film on a base substrate; and performing a crystallization treatment to the first amorphous silicon thin film to convert a part of the amorphous silicon in the first amorphous silicon thin film into polysilicon, such that a semiconductor active layer comprising one polysilicon portion or a plurality of polysilicon portions are formed.

Abstract: An electronic semiconductor component with a housing structure and a cavity introduced into the housing structure is specified. The cavity comprises a base surface. Furthermore, the electronic semiconductor component comprises an auxiliary layer arranged on the base surface of the cavity and a marking penetrating the auxiliary layer at least as far as the base surface of the cavity. The marking comprises an optical contrast that depends on both an optical property of the housing structure and an optical property of the auxiliary layer. Furthermore, a method for producing an electronic semiconductor component is given.

Abstract: An LED light-source substrate includes a first bonding sheet covering the LED, a second bonding sheet formed on the first bonding sheet, and a reflective layer formed on the second bonding sheet to suppress light from the LED. The second bonding sheet is bonded peelably from the first bonding sheet.