Patents Examined by Molly K Reida
  • Patent number: 10461219
    Abstract: A light emitting element includes an n-pad electrode, a light-transmissive electrically conductive film on an upper surface of the p-side semiconductor layer, and a p-pad electrode on an upper surface of the light-transmissive electrically conductive film. When viewed from above, the semiconductor layered structure has a pentagonal outer peripheral shape having a first side, a second side adjacent to the first side at a right angle, a third side adjacent to the first side at a right angle, a fourth side adjacent to the second side at an obtuse angle, and a fifth side adjacent to the third side and the fourth side at an obtuse angle to the third side. The n-pad electrode is disposed near the first side, and the p-pad electrode is disposed closer to a first vertex where the fourth side and the fifth side meet, than the n-pad electrode is disposed to the first vertex.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: October 29, 2019
    Assignee: NICHIA CORPORATION
    Inventor: Keiji Emura
  • Patent number: 10453765
    Abstract: The present disclosure relates to a wafer-level packaging process. According to an exemplary process, a precursor wafer that includes a device layer with a number of input/output (I/O) contacts, a number of bump structures over the device layer, the stop layer underneath the device layer, and a silicon handle layer underneath the stop layer is provided. Herein, each bump structure is electronically coupled to a corresponding I/O contact. A first mold compound is then applied over the device layer to encapsulate each bump structure. Next, the silicon handle layer is removed substantially. A second mold compound is applied to an exposed surface from which the silicon handle layer was removed. Finally, the first mold compound is thinned down to expose a portion of each bump structure.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: October 22, 2019
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, Merrill Albert Hatcher, Jr., Peter V. Wright, Jon Chadwick
  • Patent number: 10454005
    Abstract: Embodiments of the invention include a light emitting diode (UVLED), the UVLED including a semiconductor structure with an active layer disposed between an n-type region and a p-type region. The active layer emits UV radiation. The UVLED is disposed on a mount. A transparent encapsulant is disposed over the UVLED. The transparent encapsulant has an angled sidewall.
    Type: Grant
    Filed: August 22, 2018
    Date of Patent: October 22, 2019
    Assignee: RayVio Corporation
    Inventors: Faisal Sudradjat, Saijin Liu, Douglas A. Collins
  • Patent number: 10446441
    Abstract: Advanced flat metals for microelectronics are provided. While conventional processes create large damascene features that have a dishing defect that causes failure in bonded devices, example systems and methods described herein create large damascene features that are planar. In an implementation, an annealing process creates large grains or large metallic crystals of copper in large damascene cavities, while a thinner layer of copper over the field of a substrate anneals into smaller grains of copper. The large grains of copper in the damascene cavities resist dishing defects during chemical-mechanical planarization (CMP), resulting in very flat damascene features. In an implementation, layers of resist and layers of a second coating material may be applied in various ways to resist dishing during chemical-mechanical planarization (CMP), resulting in very flat damascene features.
    Type: Grant
    Filed: May 31, 2018
    Date of Patent: October 15, 2019
    Assignee: Invensas Corporation
    Inventor: Cyprian Emeka Uzoh
  • Patent number: 10439027
    Abstract: Provided is a silicon carbide semiconductor device that is further reduced in resistance. Silicon carbide semiconductor device includes silicon carbide semiconductor layer disposed on a first main surface of substrate, electrode layer containing polysilicon disposed on the silicon carbide semiconductor layer with first insulating layer interposed between the electrode layer and the silicon carbide semiconductor layer, second insulating layer that covers the silicon carbide semiconductor layer and the electrode layer, first silicide electrode that is located in first opening part formed in the first insulating layer and the second insulating layer and forms ohmic contact with a part of the silicon carbide semiconductor layer, and second silicide electrode that is located in second opening part formed in the second insulating layer and is in contact with a part of the electrode layer.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: October 8, 2019
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventor: Chiaki Kudou
  • Patent number: 10418297
    Abstract: The present disclosure relates to a wafer-level packaging process. According to an exemplary process, a precursor wafer that includes a device layer with a number of input/output (I/O) contacts, a number of bump structures over the device layer, the stop layer underneath the device layer, and a silicon handle layer underneath the stop layer is provided. Herein, each bump structure is electronically coupled to a corresponding I/O contact. A first mold compound is then applied over the device layer to encapsulate each bump structure. Next, the silicon handle layer is removed substantially. A second mold compound is applied to an exposed surface from which the silicon handle layer was removed. Finally, the first mold compound is thinned down to expose a portion of each bump structure.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: September 17, 2019
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, Merrill Albert Hatcher, Jr., Peter V. Wright, Jon Chadwick
  • Patent number: 10410869
    Abstract: Implementations described herein generally relate to a method for forming a metal layer and to a method for forming an oxide layer on the metal layer. In one implementation, the metal layer is formed on a seed layer, and the seed layer helps the metal in the metal layer nucleate with small grain size without affecting the conductivity of the metal layer. The metal layer may be formed using plasma enhanced chemical vapor deposition (PECVD) and nitrogen gas may be flowed into the processing chamber along with the precursor gases. In another implementation, a barrier layer is formed on the metal layer in order to prevent the metal layer from being oxidized during subsequent oxide layer deposition process. In another implementation, the metal layer is treated prior to the deposition of the oxide layer in order to prevent the metal layer from being oxidized.
    Type: Grant
    Filed: June 26, 2017
    Date of Patent: September 10, 2019
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Susmit Singha Roy, Kelvin Chan, Hien Minh Le, Sanjay Kamath, Abhijit Basu Mallick, Srinivas Gandikota, Karthik Janakiraman
  • Patent number: 10403588
    Abstract: A fan-out semiconductor package includes a semiconductor chip having an active surface on which a connection pad is disposed and an inactive surface opposing the active surface, an encapsulant sealing at least a portion of the inactive surface, a first connection member disposed on the active surface and including a redistribution layer and a first via electrically connecting the connection pad to the redistribution layer, a passivation layer disposed on the first connection member, and an under-bump metal layer including an external connection pad disposed on the passivation layer and a second via connecting the external connection pad to the redistribution layer. In a vertical direction, the first and second vias are disposed within the external connection pad and do not overlap each other.
    Type: Grant
    Filed: January 10, 2017
    Date of Patent: September 3, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Han Kim, Kyung Moon Jung, Seok Hwan Kim, Kyung Ho Lee, Kang Heon Hur
  • Patent number: 10403802
    Abstract: It is an object of the present invention to provide an LED panel and an LED display that enhance orientation properties of LEDs and the efficiency of light use with a simple configuration. It is a different object of the present invention to provide a method for manufacturing the LED display panel, the method reducing an increase in process step. An LED display panel according to an aspect of the present invention includes the following: a plurality of chip-on-board LEDs mounted on a substrate, the LEDs each having a light-emitting surface on a surface opposite a substrate side; and a plurality of light-transmissive members. Each light-transmissive member is disposed on the substrate to cover the light-emitting surface of at least one of the LEDs. Each light-transmissive member is configured to enhance the directionality of outgoing light emitted from the LEDs.
    Type: Grant
    Filed: September 23, 2016
    Date of Patent: September 3, 2019
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Yuzo Nakano, Shigenori Shibue, Naoki Haze
  • Patent number: 10388807
    Abstract: An example device in accordance with an aspect of the present disclosure includes a photodetector disposed on a substrate, and a mirror disposed on the photodetector. The mirror is to reflect light back into the photodetector. The mirror includes a reflective layer and a second layer. The second layer is disposed between the reflective layer and the photodetector.
    Type: Grant
    Filed: April 30, 2014
    Date of Patent: August 20, 2019
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Sagi Varghese Mathai, Michael Renne Ty Tan
  • Patent number: 10373823
    Abstract: In an embodiment, a method includes depositing a silicon matrix on a substrate; exposing the silicon matrix to a first wavelength or wavelength range of ultraviolet radiation in an ultraviolet processing chamber; exposing the silicon matrix to a second wavelength or wavelength range of ultraviolet radiation in an ultraviolet processing chamber, wherein the second wavelength or wavelength range includes a wavelength lower than any wavelength in the first wavelength or wavelength range; exposing the silicon matrix to a third wavelength or wavelength range of ultraviolet radiation in an ultraviolet processing chamber, wherein the third wavelength or wavelength range includes a wavelength lower than any wavelength in the first wavelength or wavelength range and second wavelength or wavelength range; and a repeat exposure of any wavelength range. In some embodiments, a healing operation comprising a deposition operation, a reactive cure, a thermal cure, or a combination thereof may be performed.
    Type: Grant
    Filed: May 31, 2018
    Date of Patent: August 6, 2019
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Swaminathan T. Srinivasan, Atashi Basu, Pramit Manna, Khokan C. Paul, Diwakar N. Kedlaya
  • Patent number: 10361279
    Abstract: Methods for forming semiconductor structures are provided. The method includes forming a fin structure over a substrate and forming a gate structure across the fin structure. The method further includes forming a fin spacer on a sidewall of the fin structure and partially removing the fin spacer. The method further includes recessing the fin structure to form a recess and implanting dopants from the recess to form a doped region. The method further includes diffusing the dopants in the doped region to form an expanded doped region and forming a source/drain structure over the expanded doped region.
    Type: Grant
    Filed: May 31, 2018
    Date of Patent: July 23, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shahaji B. More, Chun-Hsiung Tsai, Cheng-Yi Peng, Shih-Chieh Chang, Kuo-Feng Yu
  • Patent number: 10361229
    Abstract: The invention allows formation of LTPS TFTs and TAOS TFTs on the same substrate. The invention provides a display device including a substrate having a display area in which pixels are formed. The pixels include a first TFT made of a TAOS. The drain of the first TFT is formed of first LTPS 112. The source of the first TFT is formed of second LTPS 113. The first LTPS 112 is connected to a first electrode 106 via a first through-hole 108 formed in an insulating film 105 covering the first TFT. The second LTPS 113 is connected to a second electrode 107 via a second through-hole 108 formed in the insulating film 105 covering the first TFT.
    Type: Grant
    Filed: June 11, 2018
    Date of Patent: July 23, 2019
    Assignee: Japan Display Inc.
    Inventors: Yohei Yamaguchi, Isao Suzumura, Hidekazu Miyake
  • Patent number: 10347653
    Abstract: Provided herein a semiconductor device including a stack including conductive layers and insulating layers that are alternately stacked, and a slit insulating layer passing through the stack in a stacking direction, the slit 5 insulating layer including a first main pattern extending in a first direction, and a first protruding pattern protruding in a second direction crossing the first direction at an end of the first main pattern.
    Type: Grant
    Filed: April 13, 2018
    Date of Patent: July 9, 2019
    Assignee: SK hynix Inc.
    Inventors: Ki Hong Lee, Seung Ho Pyi, Seok Min Jeon
  • Patent number: 10347741
    Abstract: Embodiments disclosed herein relate generally to forming a gate layer in high aspect ratio trenches using a cyclic deposition-etch process. In an embodiment, a method for semiconductor processing is provided. The method includes performing a cyclic deposition-etch process to form a conformal film over a bottom surface and along sidewall surfaces of a feature on a substrate. The method includes reflowing the conformal film. The method includes forming a cap layer on the reflowed film. The method includes depositing a crystalline film on the cap layer. The method includes crystallizing the reflowed film and the cap layer after depositing the crystalline film.
    Type: Grant
    Filed: May 29, 2018
    Date of Patent: July 9, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Pin-Ju Liang, De-Wei Yu, Yi-Cheng Li, Chien-Hao Chen
  • Patent number: 10325984
    Abstract: In a semiconductor switch with a monolithically integrated field effect transistor, the source or emitter region of the field effect transistor is connected via a semiconductor region and an n-doped contact region to a first electrical terminal. In the semiconductor region, a semiconductor structure with n-doped channels is formed between the n-doped contact region and the source or emitter region of the field effect transistor; the n-doped channels electrically connect the n-doped contact region with the source or emitter region of the field effect transistor and run between p-doped regions that are connected to the n-doped contact region. The semiconductor switch is suitable as a self-switching load disconnector and has low losses in the switched-on state.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: June 18, 2019
    Assignee: FRAUNHOFER-GESELLSCHAFT ZUR FOERDERUNG DER ANGEWANDTEN FORSCHUNG E.V.
    Inventors: Andreas Huerner, Tobias Erlbacher
  • Patent number: 10319637
    Abstract: A formed back-end-of-line (BEOL) metal line layer may include a plurality of metal lines with dielectric oxide caps that are disposed in between each metal lines. To overlay an interconnecting layer of metal lines on a selected metal line of the BEOL metal line layer, a block copolymer (BCP) may be formed on a patterning layer. Thereafter, a selective etching of the formed BCP creates a recess above the selected metal line. The created recess facilitates the overlaying of the interconnecting layer of metal lines.
    Type: Grant
    Filed: November 9, 2017
    Date of Patent: June 11, 2019
    Assignee: Tokyo Electron Limited
    Inventors: Nihar Mohanty, Elliott Franke, Richard Farrell
  • Patent number: 10312163
    Abstract: The present disclosure relates to the field of semiconductor technologies, and discloses a method for manufacturing a semiconductor apparatus. An implementation of the method may include: providing a substrate structure; depositing a dummy gate material layer on the substrate structure; performing planarization processing on the dummy gate material layer; after the planarization processing, performing, according to surface roughness of the dummy gate material layer, first etching on the dummy gate material layer by using a fluorine-containing gas; after the first etching, forming a fluorine-containing polymer layer on the dummy gate material layer; and performing second etching on the substrate structure on which the fluorine-containing polymer layer is formed, to remove the fluorine-containing polymer layer, where the second etching includes etching a surface of the dummy gate material layer.
    Type: Grant
    Filed: June 1, 2018
    Date of Patent: June 4, 2019
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventors: Hai Yang Zhang, Yan Wang