Abstract: The present disclosure, in some embodiments, relates to an integrated circuit structure. The integrated circuit structure includes a substrate and a hard mask over the substrate. The hard mask has sidewalls that form a first opening and a second opening exposing an upper surface of the substrate. A block mask is arranged on the hard mask and is set back from the sidewalls of the hard mask. Spacers are disposed over the block mask and have sidewalls that define a spacer opening exposing an upper surface of the block mask. The block mask extends from directly below the spacers to laterally past the sidewalls of the spacers.

Abstract: A method for forming a redistribution structure in a semiconductor package and a semiconductor package including the redistribution structure are disclosed. In an embodiment, the method may include encapsulating an integrated circuit die and a through via in a molding compound, the integrated circuit die having a die connector; depositing a first dielectric layer over the molding compound; patterning a first opening through the first dielectric layer exposing the die connector of the integrated circuit die; planarizing the first dielectric layer; depositing a first seed layer over the first dielectric layer and in the first opening; and plating a first conductive via extending through the first dielectric layer on the first seed layer.

Abstract: A method of manufacturing a semiconductor device, including: forming a plurality of first metal strips extending in a first direction on a first plane; and forming a plurality of second metal strips extending in the first direction on a second plane over the first plane by executing a photolithography operation with a single mask, wherein a first second metal strip (FIG. 1, 131) is disposed over a first first metal strip; wherein the first first metal strip and the first second metal strip are directed to a first voltage source; wherein a distance between the first second metal strip and a second second metal strip immediate adjacent to the first second metal strip is greater than a distance between the second second metal strip and a third second metal strip immediate adjacent to the second second metal strip.

Abstract: A self-healing field-effect transistor (FET) device is disclosed in this application, the self-healing FET has a self-healing substrate, a self-healing dielectric layer, a gate electrode, at least one source electrode, at least one drain electrode, and at least one channel. The self-healing substrate and the self-healing dielectric layer have a disulfide-containing poly(urea-urethane) (PUU) polymer. The self-healing dielectric layer has a thickness of less than about 10 ?m. The electrodes have electrically conductive elongated nanostructures. The at least one channel has semi-conducting elongated nanostructures.

Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device has a semiconductor layer and a gate structure located on the semiconductor layer. The semiconductor device has source and drain terminals disposed on the semiconductor layer, and a binary oxide layer located between the semiconductor layer and the source and drain terminals.

Abstract: Semiconductor devices and methods of forming the same are provided. In one embodiment, a semiconductor device includes a gate structure sandwiched between and in contact with a first spacer feature and a second spacer feature, a top surface of the first spacer feature and a top surface of the second spacer feature extending above a top surface of the gate structure, a gate self-aligned contact (SAC) dielectric feature over the first spacer feature and the second spacer feature, a contact etch stop layer (CESL) over the gate SAC dielectric feature, a dielectric layer over the CESL, a gate contact feature extending through the dielectric layer, the CESL, the gate SAC dielectric feature, and between the first spacer feature and the second spacer feature to be in contact with the gate structure, and a liner disposed between the first spacer feature and the gate contact feature.

Abstract: A memory circuit includes: (i) a semiconductor substrate having a planar surface, the semiconductor substrate having formed therein circuitry for memory operations; (ii) a memory array formed above the planar surface, the memory array having one or more electrodes to memory circuits in the memory array, the conductors each extending along a direction substantially parallel to the planar surface; and (iii) one or more transistors each formed above, alongside or below a corresponding one of the electrodes but above the planar surface of the semiconductor substrate, each transistor (a) having first and second drain/source region and a gate region each formed out of a semiconductor material, wherein the first drain/source region, the second drain/source region or the gate region has formed thereon a metal silicide layer; and (b) selectively connecting the corresponding electrode to the circuitry for memory operations.

Abstract: Provided is a semiconductor device comprising a semiconductor substrate having a transistor section and a diode section, wherein both the transistor section and the diode section each have a drift region of a first conductivity-type provided inside the semiconductor substrate, and a base region of a second conductivity-type provided above the drift region inside the semiconductor substrate, inside the semiconductor substrate, a lifetime control region including lifetime killers is provided below the base region from at least a part of the transistor section to the diode section, and in the transistor section, a threshold value adjusting section for adjusting a threshold value of the transistor section is provided overlapping the lifetime control region as seen from an upper surface of the semiconductor substrate.

Abstract: A method comprises forming first and second fins each comprising alternately stacking first and second semiconductor layers; forming dummy gate structures over the first and second fins, and gate spacers on either side of the dummy gate structures; removing the dummy gate structures to form first and second gate trenches; removing the first semiconductor layers such that the second semiconductor layers are suspended in the first and second gate trenches; depositing a first dielectric layer around the second semiconductor layers and a second dielectric layer around the first dielectric layer; performing an ALD process to form a hard mask layer around the second dielectric layer, the ALD process comprising pulsing a first precursor for a first pulse time longer than about one second; patterning the hard mask layer; and etching a portion of the second gate dielectric layer in the second gate trench.

Abstract: Methods of cutting gate structures and fins, and structures formed thereby, are described. In an embodiment, a substrate includes first and second fins and an isolation region. The first and second fins extend longitudinally parallel, with the isolation region disposed therebetween. A gate structure includes a conformal gate dielectric over the first fin and a gate electrode over the conformal gate dielectric. A first insulating fill structure abuts the gate structure and extends vertically from a level of an upper surface of the gate structure to at least a surface of the isolation region. No portion of the conformal gate dielectric extends vertically between the first insulating fill structure and the gate electrode. A second insulating fill structure abuts the first insulating fill structure and an end sidewall of the second fin. The first insulating fill structure is disposed laterally between the gate structure and the second insulating fill structure.

Abstract: A photodetector, includes a photosensitive layer, a thin film transistor, and a sensing electrode, the sensing electrode connected to one of source/drain electrodes of the thin film transistor to transmit a signal generated by the photosensitive layer to the thin film transistor; wherein the photodetector further is a hydrogen barrier layer which is disposed between the photosensitive layer and the thin film transistor and is configured to inhibit hydrogen of the photosensitive layer from entering the thin film transistor. A method of manufacturing a photodetector is further provided.

Abstract: Embodiments include an interconnect structure and methods of forming such an interconnect structure. In an embodiment, the interconnect structure comprises a first interlayer dielectric (ILD) and a first interconnect layer with a plurality of first conductive traces partially embedded in the first ILD. In an embodiment, an etch stop layer is formed over surfaces of the first ILD and sidewall surfaces of the first conductive traces. In an embodiment, the interconnect structure further comprises a second interconnect layer that includes a plurality of second conductive traces. In an embodiment, a via between the first interconnect layer and the second interconnect layer may be self-aligned with the first interconnect layer.

Abstract: A display panel is provided and includes a substrate and a plurality of pixel units. Each of the pixel units includes a color resist block, a light transmission area, and a non-light transmission area. An opening is defined at an edge of the color resist block in the non-light transmission area, and a through-hole area is defined in the opening. The opening includes a first sidewall near the light transmission area, a compensation member is disposed at an end of the first sidewall near a gap area, and a block angle structure is formed between the compensation member and the first sidewall.

Abstract: A semiconductor structure includes semiconductor layers disposed over a substrate and oriented lengthwise in a first direction, a metal gate stack disposed over the semiconductor layers and oriented lengthwise in a second direction perpendicular to the first direction, where the metal gate stack includes a top portion and a bottom portion that is interleaved with the semiconductor layers, source/drain features disposed in the semiconductor layers and adjacent to the metal gate stack, and an isolation structure protruding from the substrate, where the isolation structure is oriented lengthwise along the second direction and spaced from the metal gate stack along the first direction, and where the isolation structure includes a dielectric layer and an air gap.

Abstract: Systems, methods, circuits, and devices for providing and using transistors in a physically unclonable function (PUF) circuit. The transistors comprise a split source drain configuration including one or more inflection segments that increase process variations between the transistors such that each transistor generates a unique output signal.

Abstract: A semiconductor device including an interlayer insulating layer on a substrate; a conductive line on the interlayer insulating layer; and a contact plug penetrating the interlayer insulating layer, the contact plug being connected to the conductive line, wherein the contact plug includes an upper pattern penetrating an upper region of the interlayer insulating layer, the upper pattern protruding upwardly from a top surface of the interlayer insulating layer, the upper pattern includes a first portion penetrating the upper region of the interlayer insulating layer; and a second portion protruding upwardly from the top surface of the interlayer insulating layer, and a width of a lower region of the second portion in a direction parallel to a top surface of the substrate is greater than a width of an upper region of the second portion in the direction parallel to the top surface of the substrate.

Abstract: Merged-PiN-Schottky, MPS, device comprising: a substrate of SiC with a first conductivity; a drift layer of SiC with the first conductivity, on the substrate; an implanted region with a second conductivity, extending at a top surface of the drift layer to form a junction-barrier, JB, diode with the substrate; and a first electrical terminal in ohmic contact with the implanted region and in direct contact with the top surface to form a Schottky diode with the drift layer. The JB diode and the Schottky diode are alternated to each other along an axis: the JB diode has a minimum width parallel to the axis with a first value, and the Schottky diode has a maximum width parallel to the axis with a second value smaller than, or equal to, the first value. A breakdown voltage of the MPS device is greater than, or equal to, 115% of a maximum working voltage of the MPS device in an inhibition state.

Abstract: Non-planar integrated circuit structures having mitigated source or drain etch from replacement gate process are described. For example, an integrated circuit structure includes a fin or nanowire. A gate stack is over the fin or nanowire. The gate stack includes a gate dielectric and a gate electrode. A first dielectric spacer is along a first side of the gate stack, and a second dielectric spacer is along a second side of the gate stack. The first and second dielectric spacers are over at least a portion of the fin or nanowire. An insulating material is vertically between and in contact with the portion of the fin or nanowire and the first and second dielectric spacers. A first epitaxial source or drain structure is at the first side of the gate stack, and a second epitaxial source or drain structure is at the second side of the gate stack.

Abstract: A stacked device structure includes a first device structure including a first body that includes a semiconductor material, and a plurality of terminals coupled with the first body. The stacked device structure further includes an insulator between the first device structure and a second device structure. The second device structure includes a second body such as a fin structure directly above the insulator. The second device structure further includes a gate coupled to the fin structure, a spacer including a dielectric material adjacent to the gate, and an epitaxial structure adjacent to a sidewall of the fin structure and between the spacer and the insulator. A metallization structure is coupled to a sidewall surface of the epitaxial structure, and further coupled with one of the terminals of the first device.

Abstract: Methods of forming carbon polymer films are disclosed. Some methods are advantageously performed at lower temperatures. The substrate is exposed to a first carbon precursor to form a substrate surface with terminations based on the reactive functional groups of the first carbon precursor and exposed to a second carbon precursor to react with the surface terminations and form a carbon polymer film. Processing tools and non-transitory memories to perform the process are also disclosed.