Patents Examined by Monica D. Harrison
  • Patent number: 10861901
    Abstract: A resistive random access memory including a stacked structure, at least one vertical electrode, a selector element, and a plurality of resistance changeable structures is provided. The stacked structure is formed by a plurality of horizontal electrodes and a plurality of first dielectric layers stacked alternately, wherein the stacked structure has at least one channel hole extending through the horizontal electrodes and the first dielectric layers. The vertical electrode is formed in the at least one channel hole. The selector element is formed in the channel hole between the vertical electrode and the stacked structure. The resistance changeable structures are disposed on the surface of each of the horizontal electrodes and are in contact with the selector element in the channel hole.
    Type: Grant
    Filed: April 26, 2019
    Date of Patent: December 8, 2020
    Assignee: Powerchip Semiconductor Manufacturing Corporation
    Inventor: Zih-Song Wang
  • Patent number: 10861966
    Abstract: A semiconductor device includes: a gate trench extending into a Si substrate; a body region in the Si substrate adjacent the gate trench; a source region in the Si substrate above the body region; a diffusion barrier structure adjacent a sidewall of the gate trench, the diffusion barrier structure including alternating layers of Si and oxygen-doped Si and a Si capping layer on the alternating layers of Si and oxygen-doped Si; and a channel region formed in the Si capping layer and which vertically extends along the sidewall of the gate trench. Corresponding methods of manufacture are also described.
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: December 8, 2020
    Assignee: Infineon Technologies Austria AG
    Inventors: Thomas Feil, Robert Haase, Martin Poelzl, Maximilian Roesch, Sylvain Leomant, Bernhard Goller, Ravi Keshav Joshi
  • Patent number: 10854595
    Abstract: An Electro-Static Discharge (ESD) includes a first well having a first conductivity type on a substrate. The device further includes a second well within the first well. The second well has a second conductivity type. The device further includes a third well within the first well. The third well has the second conductivity type. The device further includes a first gate device disposed over the first well, a plurality of active regions between the first gate device and the dummy gate, and a dummy gate disposed within a space between the active regions. The dummy gate is positioned over a space between the second and third wells.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: December 1, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wun-Jie Lin, Han-Jen Yang, Yu-Ti Su
  • Patent number: 10851454
    Abstract: A method of forming conformal amorphous metal films is disclosed. A method of forming crystalline metal films with a predetermined orientation is also disclosed. An amorphous nucleation layer is formed on a substrate surface. An amorphous metal layer is formed from the nucleation layer by atomic substitution. A crystalline metal layer is deposited on the amorphous metal layer by atomic layer deposition.
    Type: Grant
    Filed: October 9, 2019
    Date of Patent: December 1, 2020
    Assignee: Applied Materials, Inc.
    Inventors: Yong Wu, Srinivas Gandikota, Abhijit Basu Mallick
  • Patent number: 10854461
    Abstract: Methods for depositing a metal film without the use of a barrier layer are disclosed. Some embodiments comprise forming an amorphous nucleation layer comprising one or more of silicon or boron and forming a metal layer on the nucleation layer.
    Type: Grant
    Filed: September 30, 2019
    Date of Patent: December 1, 2020
    Assignee: Applied Materials, Inc.
    Inventors: Yihong Chen, Yong Wu, Chia Cheng Chin, Srinivas Gandikota, Kelvin Chan
  • Patent number: 10847660
    Abstract: A method of forming a semiconductor device includes providing a region of semiconductor material comprising a major surface. A termination trench is provided extending from a first portion of the major surface into the region of semiconductor material to a first depth and has a first width. A first active trench is provided extending from a second portion of the major surface into the region of semiconductor material to a second depth and has a second width less than the first width. A second active trench is provided extending from a third portion of the major surface into the region of semiconductor material to a third depth and has a third width less than the first width. A first conductive material is provided adjoining a fourth portion of the major surface, which is configured as a Schottky barrier. The selected trench depth difference alone or in combination with other features provides a semiconductor device having improved performance characteristics.
    Type: Grant
    Filed: August 20, 2019
    Date of Patent: November 24, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Mohammed Tanvir Quddus, Mihir Mudholkar, Michael Thomason
  • Patent number: 10840466
    Abstract: Disclosed herein is an electronic device including a first electrode, a second electrode, and a photoelectric conversion layer held between the first electrode and the second electrode. The first electrode is formed from a transparent conductive material having a work function ranging from 5.2 to 5.9 eV, preferably from 5.5 to 5.9 eV, more preferably 5.8 to 5.9 eV.
    Type: Grant
    Filed: October 24, 2019
    Date of Patent: November 17, 2020
    Assignee: SONY CORPORATION
    Inventor: Toshiki Moriwaki
  • Patent number: 10833272
    Abstract: Provided are a laminate which includes an organic semiconductor film, a water-soluble resin layer, and a photosensitive resin layer and in which cracks are unlikely to occur; and a kit. The laminate includes a water-soluble resin layer containing a water-soluble resin and a photosensitive resin layer containing a photosensitive resin, which are provided in this order on an organic semiconductor film. The water-soluble resin layer and the photosensitive resin layer are adjacent to each other, the water-soluble resin is at least one of polyvinylpyrrolidone having a weight-average molecular weight of 300,000 or greater or polyvinyl alcohol having a weight-average molecular weight of 15,000 or greater, and the photosensitive resin has a weight-average molecular weight of 30,000 or greater.
    Type: Grant
    Filed: October 19, 2017
    Date of Patent: November 10, 2020
    Assignee: FUJIFILM Corporation
    Inventors: Seiya Masuda, Yoshitaka Kamochi, Atsushi Nakamura
  • Patent number: 10818746
    Abstract: A display device includes a substrate including a bending area located between a first area and a second area. The substrate is bent in relation to a bending axis. A first wiring unit including a plurality of first wirings is arranged on the substrate to sequentially extend over the first area, the bending area, and the second area. First central axes included in each of the plurality of first wirings are spaced apart from each other by a first pitch in the bending area. A second wiring unit including a plurality of second wirings is arranged on the substrate to sequentially extend over the first area, the bending area, and the second area. Second central axes included in each of the plurality of second wirings are spaced apart from each other by a second pitch greater than the first pitch in the bending area.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: October 27, 2020
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Yangwan Kim, Sunja Kwon, Byungsun Kim, Hyunae Park, Sujin Lee, Jaeyong Lee
  • Patent number: 10811387
    Abstract: Semiconductor device packages include a stack of semiconductor memory devices positioned over an interposer substrate, a controller element, and a redistribution substrate positioned laterally adjacent to the controller element. At least a portion of the controller element is positioned directly between the stack and the interposer substrate. The controller element is operatively connected to the semiconductor memory devices of the stack through the redistribution substrate and the interposer substrate. Methods of manufacturing a semiconductor device package include positioning a redistribution substrate laterally adjacent to a controller element and attaching the redistribution substrate and the controller element to an interposer substrate. A stack of semiconductor memory devices is positioned over the controller element and the redistribution substrate.
    Type: Grant
    Filed: November 19, 2018
    Date of Patent: October 20, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Seng Kim Dalson Ye, Hong Wan Ng
  • Patent number: 10811404
    Abstract: Provided are a package structure and a method of manufacturing the same. The package structure includes a die, a passive device, and a package. The die has a front side and a backside opposite to each other. The package is disposed on the backside of the die. The passive device is disposed between the backside of the die and the package.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: October 20, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Ya Huang, Chung-Hao Tsai, Chen-Hua Yu, Chuei-Tang Wang
  • Patent number: 10811360
    Abstract: According to one embodiment, a semiconductor device includes a semiconductor layer, an insulating film, a first interconnect, a conductor, and a frame-shaped portion. The insulating film is provided on the semiconductor layer. The first interconnect is provided on the insulating film. The conductor extends through the insulating film and electrically connects the semiconductor layer and the first interconnect. The frame-shaped portion extends through the insulating film and is provided in a second region different from a first region, the conductor being provided in the first region. The frame-shaped portion protrudes from a surface of the insulating film on which the first interconnect is provided.
    Type: Grant
    Filed: March 4, 2016
    Date of Patent: October 20, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Masayoshi Tagami
  • Patent number: 10804319
    Abstract: A top pinned magnetic tunnel junction (MTJ) stack for use in spin-transfer torque magnetoresistive random access memory (STT MRAM) is provided. The top pinned MTJ stack contains a synthetic anti-ferromagnetic magnetic free layer stack that is formed on an insulating aluminum nitride (AlN) seed layer having hexagonal symmetry. For such a top pinned MTJ stack, the symmetry requirements for the tunnel barrier layer do not conflict anymore with the symmetry requirements for strong anti-ferromagnetic exchange. Further, and compared to using only a metallic seed, the insulating AlN seed layer limits spin pumping from the magnetic free layer into the metallic seed layer and therefore lowers the switching current, while only making a small contribution to the resistance of a STT MRAM.
    Type: Grant
    Filed: February 15, 2019
    Date of Patent: October 13, 2020
    Assignee: International Business Machines Corporation
    Inventor: Matthias G. Gottwald
  • Patent number: 10790290
    Abstract: A 3D NAND storage device includes a plurality of layers containing doped semiconductor material interleaved with a plurality of layers of dielectric material. Each of the pillars forming the 3D NAND storage device includes a plurality of memory cells and a drain-end select gate (SGD). The pillars are separated by a hollow channel in which a plurality of film layers, including at least a lower film layer and an upper film layer have been deposited. The systems and methods described herein remove at least the upper film layer proximate the SGD while maintaining the film layers proximate the memory cells. Such an arrangement beneficially permits tailoring the film layers proximate the SGD prior to depositing the channel film layer in the hollow channel. The systems and methods described herein permit the deposition of a continuous channel film layer proximate both the memory cells and the SGD.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: September 29, 2020
    Assignee: Intel Corporation
    Inventors: David A. Daycock, Purnima Narayanan, John Hopkins, Guoxing Duan, Barbara L. Casey, Christopher J. Larsen, Meng-Wei Kuo, Qian Tao
  • Patent number: 10790372
    Abstract: A method of fabricating a semiconductor device includes forming an intermediate semiconductor device having dummy gate material and an oxide layer. The intermediate semiconductor device includes a substrate, fins, a shallow trench isolation layer, an oxide layer, and an interlayer dielectric. The dummy gate material and the oxide layer are removed. A high k dielectric material is deposited on a top surface of the shallow trench isolation layer. A replacement metal gate stack is deposited. Gate cut lithographing patterning is performed to open portions of the gate. The replacement metal gate stack and the interlayer dielectric are etched. A cap layer is deposited on exposed ends of at least two replacement metal gate. Trenches are filled with the interlayer dielectric and the semiconductor device is formed. Selective deposition of the insulating material on the ends of the replacement metal gates prevents gate end shorts.
    Type: Grant
    Filed: January 10, 2019
    Date of Patent: September 29, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Andrew Greene, Ekmini Anuja De Silva
  • Patent number: 10784361
    Abstract: A semiconductor device according to an embodiment includes a first GaN-based semiconductor layer, a second GaN-based semiconductor layer provided on the first GaN-based semiconductor layer and having a wider band gap than the first GaN-based semiconductor layer, a source electrode electrically connected to the second GaN-based semiconductor layer, a drain electrode electrically connected to the second GaN-based semiconductor layer, a gate electrode provided between the source electrode and the drain electrode, and a passivation film provided on the second GaN-based semiconductor layer between the source electrode and the gate electrode and between the gate electrode and the drain electrode, the passivation film including a first insulating film and a second insulating film, the first insulating film including nitrogen, the first insulating film having a thickness equal to or greater than 0.2 nm and less than 2 nm, the second insulating film including oxygen and provided on the first insulating film.
    Type: Grant
    Filed: January 12, 2016
    Date of Patent: September 22, 2020
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hisashi Saito, Miki Yumoto
  • Patent number: 10773953
    Abstract: A method of fabricating a MEMS structure includes providing a substrate comprising a logic element region and a MEMS region. Next, a logic element is formed within the logic element region. A nitrogen-containing material layer is formed to cover the logic element region and the MEMS region conformally. Then, part of the nitrogen-containing material layer within the MEMS region is removed to form at least one shrinking region. Subsequently, a dielectric layer is formed to cover the logic element region and MEMS region, and the dielectric layer fills in the shrinking region. After that, the dielectric layer is etched to form at least one releasing hole, wherein the shrinking region surrounds the releasing hole. Finally, the substrate is etched to form a chamber.
    Type: Grant
    Filed: September 7, 2017
    Date of Patent: September 15, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Meng-Jia Lin, Yung-Hsiao Lee, Weng-Yi Chen, Shih-Wei Li, Chung-Hsien Liu
  • Patent number: 10770344
    Abstract: A method of fabricating interconnects in a semiconductor device is provided, which includes forming an interconnect layer having a conductive line and depositing a first aluminum-containing layer over the interconnect layer. A dielectric layer is deposited over the first aluminum-containing layer, followed by a second aluminum-containing layer deposited over the dielectric layer. A via opening is formed in the second aluminum-containing layer through to the conductive line, wherein the via opening has chamferless sidewalls.
    Type: Grant
    Filed: January 9, 2019
    Date of Patent: September 8, 2020
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Yuping Ren, Haigou Huang, Ravi Prakash Srivastava, Zhiguo Sun, Qiang Fang, Cheng Xu, Guoxiang Ning
  • Patent number: 10770548
    Abstract: A silicon nitride film having a thickness in a range from 1 [nm] to 3 [nm] is deposited on a front surface of a silicon carbide semiconductor base, by an ALD method. Next, on the silicon nitride film, for example, a silicon oxide film having a thickness in a range from 20 [nm] to 100 [nm] is deposited. After deposition of the silicon oxide film, for example, heat treatment is performed at a temperature in a range from 1100 degrees C. to 1350 degrees C., in a gas atmosphere that includes oxygen. By this heat treatment, nitrogen surface density of an interface of the silicon carbide semiconductor base and the silicon oxide film (gate insulating film) is increased, reducing interface state density of the interface of the silicon carbide semiconductor base and the silicon nitride film.
    Type: Grant
    Filed: February 15, 2019
    Date of Patent: September 8, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Tsuyoshi Araoka, Mitsuo Okamoto, Yohei Iwahashi
  • Patent number: 10770010
    Abstract: An information terminal capable of switching display and non-display of images by strain. The information terminal includes a display portion and a strain sensor. The display portion includes a liquid crystal element, a light-emitting element, and a first and a second transistors. The strain sensor includes a strain sensor element and a resistor. The first transistor has a function of controlling current flowing into the light-emitting element. The strain sensor element has a function as a variable resistor. A first terminal of the strain sensor element is electrically connected to a first terminal of the resistor. A gate of the first transistor is electrically connected to a first terminal of the strain sensor element via the second transistor.
    Type: Grant
    Filed: July 18, 2019
    Date of Patent: September 8, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Yuki Okamoto