Patents Examined by Monica D. Harrison
  • Patent number: 10763335
    Abstract: A semiconductor device includes a substrate having an active pattern therein, a gate electrode extending across the active pattern and a source/drain region on the active pattern laterally adjacent the gate electrode. The device further includes a contact structure including a first contact on the source/drain region, a second contact on the first contact and a spacer on sidewalls of the first and second contacts.
    Type: Grant
    Filed: November 28, 2018
    Date of Patent: September 1, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Wonkeun Chung, Heonbok Lee, Chunghwan Shin, Youngsuk Chai, Sangjin Hyun
  • Patent number: 10756059
    Abstract: A semiconductor chip including a plurality of input/output units includes: a plurality of additional pads disposed on a surface of the semiconductor chip, wherein the plurality of additional pads include at least one of a first additional pad to which a ground voltage is applied and a second additional pad to which a power supply voltage is applied; and a plurality of pads disposed on the surface of the semiconductor chip, wherein the plurality of pads include at least one of a first pad to which the ground voltage is applied and a second pad to which the power supply voltage is applied, and further include a third pad through which a signal is input and/or output. The at least one of the first additional pad and the second additional pad is disposed on an input/output unit where the third pad is disposed, among the plurality of input/output units.
    Type: Grant
    Filed: October 11, 2018
    Date of Patent: August 25, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kwanyeob Chae, Sanghoon Joo, Jong-Ryun Choi, Jin-Ho Choi
  • Patent number: 10756128
    Abstract: An integrated circuit device includes a complementary metal oxide semiconductor (CMOS) image sensor. The complementary metal oxide semiconductor (CMOS) image sensor includes a P-N junction photodiode, a transistor gate, a polysilicon plug and a stacked metal layer. The P-N junction photodiode is disposed in a substrate. The transistor gate and the polysilicon plug are disposed on the substrate, wherein the polysilicon plug is directly connected to the P-N junction photodiode. The stacked metal layer connects the polysilicon plug to the transistor gate, wherein the stacked metal layer includes a lower metal layer and an upper metal layer, and the lower metal layer includes a first metal silicide part contacting to the polysilicon plug. The present invention also provides a method of fabricating said integrated circuit device.
    Type: Grant
    Filed: January 10, 2019
    Date of Patent: August 25, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Kuo-Chih Lai, Shih-Min Chou, Ko-Wei Lin, Chin-Fu Lin, Wei-Chuan Tsai, Chun-Yao Yang, Chia-Fu Cheng, Yi-Syun Chou, Wei Chen
  • Patent number: 10756152
    Abstract: An exemplary embodiment of the present inventive concept provides a display device including: a substrate; a semiconductor layer; a first inorganic insulating film disposed on the semiconductor layer and including a first opening; a first conductive film disposed on the first inorganic insulating film; a second inorganic insulating film disposed on the first inorganic insulating film to fill a concave portion on the first conductive film; a second conductive film disposed on the second inorganic insulating film; a third inorganic insulating film disposed on the second conductive film and including a second opening; and a third conductive film disposed on the third inorganic insulating film, and connected to the second conductive film, wherein the first opening and the second opening may overlap each other.
    Type: Grant
    Filed: May 28, 2019
    Date of Patent: August 25, 2020
    Assignee: Samsung Display Co., Ltd.
    Inventors: Jun Hong Park, Ji-Hyun Kim, Jun Chun, Eui Suk Jung, Jeong Min Park
  • Patent number: 10748993
    Abstract: Transistor structures having channel regions comprising alternating layers of compressively and tensilely strained epitaxial materials are provided. The alternating epitaxial layers can form channel regions in single and multigate transistor structures. In alternate embodiments, one of the two alternating layers is selectively etched away to form nanoribbons or nanowires of the remaining material. The resulting strained nanoribbons or nanowires form the channel regions of transistor structures. Also provided are computing devices comprising transistors comprising channel regions comprised of alternating compressively and tensilely strained epitaxial layers and computing devices comprising transistors comprising channel regions comprised of strained nanoribbons or nanowires.
    Type: Grant
    Filed: July 29, 2019
    Date of Patent: August 18, 2020
    Assignee: Intel Corporation
    Inventors: Van H. Le, Benjamin Chu-Kung, Harold Hal W. Kennel, Willy Rachmady, Ravi Pillarisetty, Jack T. Kavalieros
  • Patent number: 10748950
    Abstract: There is provided a light receiving element including; an on-chip lens; a wiring layer; and a semiconductor layer disposed between the on-chip lens and the wiring layer. The semiconductor layer includes a first voltage applying unit to which a first voltage is applied, a second voltage applying unit to which a second voltage different from the first voltage is applied, a first charge detection unit disposed in a vicinity of the first voltage applying unit, and a second charge detection unit disposed in a vicinity of the second voltage applying unit, and the wiring layer includes a reflection suppressing structure that suppresses reflection of light in a plane region corresponding to the first charge detection unit and the second charge detection unit.
    Type: Grant
    Filed: March 1, 2019
    Date of Patent: August 18, 2020
    Assignee: Sony Semiconductor Solutions Corporation
    Inventor: Ryota Watanabe
  • Patent number: 10741739
    Abstract: A Micro LED transferring method, a Micro LED display panel and a Micro LED display device are provided. The Micro LED display panel includes a substrate, a pixel defining layer including multiple openings, first conducting layer located in the multiple openings, photosensitive conductive bonding layers and Micro LED structures. The photosensitive conductive bonding layer is solidified after receiving light, such that elements adhered on two opposite surfaces of the photosensitive conductive bonding layer are bonded together. Due to the photosensitive conductive bonding layer, a Micro LED is detected during a transferring process rather than after a bonding process, thereby eliminating a step of removing a bonded abnormal Micro LED, thus simplifying the detecting and repairing processes of Micro LEDs.
    Type: Grant
    Filed: January 10, 2019
    Date of Patent: August 11, 2020
    Inventors: Zeshang He, Liang Xing, Jujian Fu, Gang Liu
  • Patent number: 10727377
    Abstract: Disclosed are a full-spectrum light emitting diode (LED) and applications thereof. A fluorescent powder composition is mixed with silica gel. In the mixture of the fluorescent powder composition and the silica gel, the mixture of the fluorescent powder composition and the silica gel is applied on blue LED chips. The blue LED chips are blue light emitting diode chips, and at least two blue LED chips are provided. The fluorescent powder composition includes fluorescent powder of at least two different colors. An excited spectrum is close to a plant photosynthesis curve, a meat irradiation curve, a biological growth curve, a seafood irradiation curve, a vegetable and fruit irradiation curve, and a pastry irradiation curve. A full-spectrum LED light source can be adjusted to simulate natural light irradiation. The excited spectrum is close to the plant photosynthesis curve, thereby causing photosynthesis in plants, achieving an optimal plant growth effect.
    Type: Grant
    Filed: May 24, 2016
    Date of Patent: July 28, 2020
    Assignee: HIT INTERNATIONAL CONSULTING LLC
    Inventors: Tzuhsin Wang, Shirong Wen, Haifeng Zheng, Daoguang Liu, Hongbo Yan, Jingjun Gu
  • Patent number: 10727197
    Abstract: An embedded-bridge substrate connector apparatus includes a patterned reference layer to which a first module and a subsequent module are aligned and the two modules are mated at the patterned reference layer. At least one module includes a silicon bridge connector that bridges to two devices, through the patterned reference layer, to the mated module.
    Type: Grant
    Filed: March 21, 2017
    Date of Patent: July 28, 2020
    Assignee: Intel IP Corporation
    Inventors: Bernd Waidhas, Georg Seidemann, Andreas Wolter, Thomas Wagner, Stephan Stoeckl, Laurent Millou
  • Patent number: 10727288
    Abstract: A display device includes a driving transistor and an organic EL element. The driving transistor includes an oxide semiconductor layer; a first gate electrode that includes a region overlapping the oxide semiconductor layer; a first insulating layer between the first gate electrode and the oxide semiconductor layer; a second gate electrode that includes a region overlapping the oxide semiconductor layer and the first gate electrode; a second insulating layer between the second gate electrode and the oxide semiconductor layer; and a first and a second transparent conductive layer that are provided between the oxide semiconductor layer and the first insulating layer and each include a region contacting the oxide semiconductor layer. The organic EL element includes a first electrode; a second electrode; a light emitting layer between the first electrode and the second electrode; and an electron transfer layer between the light emitting layer and the first electrode.
    Type: Grant
    Filed: July 19, 2019
    Date of Patent: July 28, 2020
    Assignee: MIKUNI ELECTRON CORPORATION
    Inventor: Sakae Tanaka
  • Patent number: 10727385
    Abstract: According to one embodiment, a light emitting device includes a first lead, a light emitting element, and a first bonding member. The light emitting element includes a semiconductor stacked body and a first electrode. The semiconductor stacked body includes a light emitting layer. The first electrode is below the semiconductor stacked body. The first bonding member electrically connects the first lead and the first electrode. A lower surface of the first electrode includes a first protrusion, a second protrusion, and a first depression. The first depression is located between the first and second protrusions. The first protrusion has a first side surface. The second protrusion has a second side surface facing the first side surface. The first bonding member contacts at least a part of the first side surface. At least a part of the second side surface is separated from the first bonding member.
    Type: Grant
    Filed: February 26, 2019
    Date of Patent: July 28, 2020
    Assignee: NICHIA CORPORATION
    Inventor: Ryosuke Wakaki
  • Patent number: 10720530
    Abstract: A device includes a fin extending from a substrate, a gate stack over and along sidewalls of the fin, a gate spacer along a sidewall of the gate stack, and an epitaxial source/drain region in the fin and adjacent the gate spacer. The epitaxial source/drain region includes a first epitaxial layer on the fin, the first epitaxial layer including silicon, germanium, and arsenic, and a second epitaxial layer on the first epitaxial layer, the second epitaxial layer including silicon and phosphorus, the first epitaxial layer separating the second epitaxial layer from the fin. The epitaxial source/drain region further includes a third epitaxial layer on the second epitaxial layer, the third epitaxial layer including silicon, germanium, and phosphorus.
    Type: Grant
    Filed: November 20, 2018
    Date of Patent: July 21, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Yu Ma, Shahaji B. More, Yi-Min Huang, Shih-Chieh Chang
  • Patent number: 10720368
    Abstract: A semiconductor device includes: an insulating substrate having an upper surface on which a semiconductor element is mounted; a base plate joined to a lower surface of the insulating substrate; a case member that surrounds the insulating substrate and that is in contact with a surface of the base plate to which the insulating substrate is joined; a sealing resin provided in a region surrounded by the base plate and the case member; a cover member facing a surface of the sealing resin and fixed to the case member; and a holding plate, a lower surface of the holding plate and a portion of a side surface of the holding plate being in close contact with the surface of the sealing resin, an upper surface of the holding plate being fixed to and protruding from a surface of the cover member facing the surface of the sealing resin.
    Type: Grant
    Filed: December 14, 2016
    Date of Patent: July 21, 2020
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Hiroyuki Harada, Kozo Harada, Yasumichi Hatanaka, Takashi Nishimura, Masaki Taya
  • Patent number: 10720466
    Abstract: An image sensor is disclosed. The image sensor may include a photosensing region in a substrate and configured to generate photoelectrons in response to incident light on the photosensing region; bias patterns arranged to surround the photosensing region and including a conductive material; a floating diffusion region at a center of the photosensing region to store photoelectrons generated by the photosensing region; and transfer gates that partially overlap with the floating diffusion region and are operable to transfer photoelectrons generated by the photosensing region to the floating diffusion region. The photosensing region and the bias patterns are electrically isolated from one another.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: July 21, 2020
    Assignee: SK hynix Inc.
    Inventor: Sun-Ho Oh
  • Patent number: 10712456
    Abstract: Disclosed herein is a method comprising: obtaining a substrate comprising an electronic system in or on the substrate, and a plurality of electric contacts on a first surface of the substrate, the electronic system being electrically connected to the electric contacts; obtaining a chip comprising an X-ray absorption layer, the X-ray absorption layer comprising an electrode; electrically connecting the electrode to at least one of the electric contacts by bonding the chip to the substrate; and thinning the substrate at a surface opposite the first surface.
    Type: Grant
    Filed: January 22, 2019
    Date of Patent: July 14, 2020
    Assignee: SHENZHEN XPECTVISION TECHNOLOGY CO., LTD.
    Inventors: Peiyan Cao, Yurun Liu
  • Patent number: 10714667
    Abstract: A method of manufacturing a light emitting device includes forming light emitting devices on a support portion, each of the light emitting devices including first to third light emitting cells respectively emitting light of different colors; supplying test power to at least a portion of the light emitting devices using a multi-probe; acquiring an image from the light emitted from the portion of the light emitting devices to which the test power is supplied using an image sensor; identifying normal light emitting devices of the portion of the light emitting devices by determining whether a defect is present in each of the light emitting devices of the portion of the light emitting devices by comparing the image acquired by the image sensor with a reference image; and based on the identifying step, measuring optical characteristics of each of the light emitting devices identified as normal of the portion of the light emitting devices.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: July 14, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hye Seok Noh, Young Jin Choi, Yong Il Kim, Han Kyu Seong, Dong Gun Lee, Jin Sub Lee
  • Patent number: 10714500
    Abstract: Provided are an electronic device and a method of manufacturing the same. The electronic device may include a first device provided on a first region of a substrate; and a second device provided on a second region of the substrate, wherein the first device may include a first domain layer including a ferroelectric domain and a first gate electrode on the first domain layer, and the second device may include a second domain layer including a ferroelectric domain and a second gate electrode on the second domain layer. The first domain layer and the second domain layer may have different characteristics from each other at a polarization change according to an electric field. At the polarization change according to the electric field, the first domain layer may have substantially a non-hysteretic behavior characteristic and the second domain layer may have a hysteretic behavior characteristic.
    Type: Grant
    Filed: January 10, 2019
    Date of Patent: July 14, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jinseong Heo, Yunseong Lee, Sanghyun Jo
  • Patent number: 10714395
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate having adjacent first and second fins protruding from the substrate, an isolation feature between and adjacent to the first fin and the second fin, and a fin isolation structure between the first fin and the second fin. The fin isolation structure includes a first insulating layer partially embedded in the isolation feature, a second insulating layer having sidewall surfaces and a bottom surface that are covered by the first insulating layer, a first capping layer covering the second insulating layer and having sidewall surfaces that are covered by the first insulating layer, and a second capping layer having sidewall surfaces and a bottom surface that are covered by the first capping layer.
    Type: Grant
    Filed: February 15, 2019
    Date of Patent: July 14, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chu-An Lee, Chen-Hao Wu, Peng-Chung Jangjian, Chun-Wen Hsiao, Teng-Chun Tsai, Huang-Lin Chao
  • Patent number: 10714518
    Abstract: An imaging device includes: a container including a bottom plate and a side wall provided on an outer circumferential portion of the bottom plate; a step portion which is formed in a top outer circumferential portion of the side wall and includes: a horizontal surface that is located at a lower position than a top surface of the side wall; and a side surface that connects the top surface of the side wall to the horizontal surface; an imaging element mounted on the bottom plate; a glass lid which is bonded to the top surface of the side wall with a first adhesive layer; and a cover frame which is disposed on the step portion and bonded to the side surface of the step portion and an outer circumferential surface of the glass lid with a second adhesive layer.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: July 14, 2020
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventor: Satoshi Matsuzawa
  • Patent number: 10707197
    Abstract: A three-dimensional stacked integrated circuit (3D SIC) that can have at least a first 3D XPoint (3DXP) die and, in some examples, can have at least a second 3DXP die too. In such examples, the first 3DXP die and the second 3DXP die can be stacked. The 3D SIC can be partitioned into a plurality of columns that are perpendicular to each of the stacked dies. In such examples, when a first column of the plurality of columns is determined as failing, data stored in the first column can be replicated to a second column of the plurality of columns. Also, for example, when a part of a first column of the plurality of columns is determined as failing, data stored in the part of the first column can be replicated to a corresponding part of a second column of the plurality of columns.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: July 7, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Tony M. Brewer