Patents Examined by Monica D. Harrison
  • Patent number: 10658587
    Abstract: Subject matter herein disclosed relates to a method for the manufacture of a CEM switching device providing that the CEM layer comprises a doped metal compound substantially free from metal wherein ions of the same metal element are present in different oxidation states. The method may provide a CEM layer which is born on and capable of switching with operating voltages below 2.0V.
    Type: Grant
    Filed: October 24, 2018
    Date of Patent: May 19, 2020
    Assignee: Arm Limited
    Inventors: Kimberly Gay Reid, Lucian Shifren, Carlos Alberto Paz de Araujo, Jolanta Bozena Celinska
  • Patent number: 10643950
    Abstract: A die has a positional location in a wafer defined by first and second coordinates, the first and second coordinates identifying a respective horizontal and vertical location where the die was formed. An index formed on the die has a first comb structure of a first contiguous arrangement of first dots, and a second comb structure of a second contiguous arrangement of second dots. A first marker at a selected one of the first dots indicates a first digit of the first coordinate, and a first additional marker at a selected one of the first dots indicates a second digit of the first coordinate. A second marker at a selected one of the second dots indicates a first digit of the second coordinate, and a second additional marker at a selected one of the second dots indicates a second digit of the second coordinate.
    Type: Grant
    Filed: April 20, 2015
    Date of Patent: May 5, 2020
    Assignee: STMicroelectronics S.r.l.
    Inventors: Emanuele Brenna, Antonio Di Franco
  • Patent number: 10644654
    Abstract: Structures for a cascode integrated circuit and methods of forming such structures. A field-effect transistor of the structure includes a gate electrode finger, a first source/drain region, and a second source/drain region. A bipolar junction transistor of the structure includes a first terminal, a base layer with an intrinsic base portion arranged on the first terminal, and a second terminal that includes one or more fingers arranged on the intrinsic base portion of the base layer. The intrinsic base portion of the base layer is arranged in a vertical direction between the first terminal and the second terminal. The first source/drain region is coupled with the first terminal, and the first source/drain region at least partially surrounds the bipolar junction transistor.
    Type: Grant
    Filed: September 12, 2017
    Date of Patent: May 5, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Vibhor Jain, Anthony K. Stamper, Alvin J. Joseph, John J. Pekarik
  • Patent number: 10636973
    Abstract: A polymer material includes a structural unit represented by Chemical Formula 1 X—Y ??Chemical Formula 1 wherein, in Chemical Formula 1, X and Y are as defined herein.
    Type: Grant
    Filed: January 10, 2019
    Date of Patent: April 28, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Fujiyama Takahiro, Fumiaki Kato, Takao Motoyama, Yusaku Konishi, Mitsunori Ito, Furuta Keigo
  • Patent number: 10629797
    Abstract: A structure has a first substrate bonded to a first under-bump metallization (UBM) structure, the first UBM structure comprising a first bonding region laterally surrounded by a first superconducting region. A second substrate is bonded to a second under-bump metallization (UBM) structure, the second UBM structure comprising a second bonding region laterally surrounded by a second superconducting region; and a superconducting solder material joins the first UBM structure to the second UBM structure.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: April 21, 2020
    Assignee: International Business Machines Corporation
    Inventors: David W. Abraham, John M. Cotte, Eric P. Lewandowski
  • Patent number: 10622222
    Abstract: An integrated fan-out package having a multi-band antenna and a method of forming the same are disclosed. An integrated fan-out package includes a semiconductor die, a molding layer and a plurality of through integrated fan-out vias. The molding layer is aside the semiconductor die. The through integrated fan-out vias are through the molding layer and arranged to form a plurality of dipole antennas. At least one of the plurality of dipole antennas includes two dipole arms each having a transmitting strip and a radiating strip connected to the transmitting part, and the radiating strip has a first part, a second part and a filter part between and in contact with the first part and the second part. The cross-sectional area of the filter part is less than the cross-sectional area of the first part or the second part of the radiating strip.
    Type: Grant
    Filed: June 3, 2019
    Date of Patent: April 14, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Nan-Chin Chuang, Ching-Feng Yang, Kai-Chiang Wu
  • Patent number: 10622429
    Abstract: A micro display device and a display integrated circuit are provided. Embodiments of the micro display device includes: a silicon substrate; a pixel array including a plurality of sub-pixels arranged in a pixel array zone of the silicon substrate; and driver circuits positioned in a circuit zone disposed around the pixel array zone of the silicon substrate, in which all or some of transistors in the pixel array zone and transistors in the circuit zone have different current-voltage transmission characteristics, thereby having excellent driving performance and display performance.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: April 14, 2020
    Assignee: LG Display Co., Ltd.
    Inventors: UnSang Yu, Ho-Jin Kim, Gyungmin Kim
  • Patent number: 10615255
    Abstract: A method of fabricating a semiconductor structure includes forming a plurality of semiconductor fins disposed on a semiconductor substrate, wherein at least one of the fins is an unwanted fin including a semiconductor material; providing a conformal protective layer over the plurality of semiconductor fins; forming a mask having an opening over the unwanted fin; removing a portion of the unwanted fin to expose a fin spike; oxidizing the fin spike to form an oxidized semiconductor material; and removing the oxidized semiconductor material to expose a fin base.
    Type: Grant
    Filed: February 12, 2016
    Date of Patent: April 7, 2020
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, STMICROELECTRONICS, INC., SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Susan S. Fan, Dongseok Lee, David Moreau, Tenko Yamashita
  • Patent number: 10615317
    Abstract: A material for an electronic device includes a substance arranged to emit light in a predetermined range of wavelength upon receiving an excitation energy, wherein the substance includes a plurality of carbon nitride particles and a siloxane material. A method of producing the material and a light emitting device including the material are also described.
    Type: Grant
    Filed: June 22, 2018
    Date of Patent: April 7, 2020
    Assignee: CITY UNIVERSITY OF HONG KONG
    Inventors: Aiwu Wang, Yang Yang Li, Jian Lu
  • Patent number: 10615113
    Abstract: A capacitor includes a first set of conductive fingers having a first conductive pitch at a first interconnect layer and arranged in a first unidirectional routing. The capacitor further includes a second set of conductive fingers having a second conductive pitch at a second interconnect layer and arranged in a second unidirectional routing that is orthogonal to the first unidirectional routing. The first conductive pitch is different from the second conductive pitch. A first set of through finger vias electrically couples the first set of conductive fingers of the first interconnect layer to the second set of conductive fingers of the second interconnect layer. A third set of conductive fingers at a third conductive layer are parallel to, but offset from, the first set of conductive fingers. A second set of through finger vias electrically couples the third set of conductive fingers to the second set of conductive fingers.
    Type: Grant
    Filed: June 13, 2018
    Date of Patent: April 7, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Xia Li, Junjing Bao, Bin Yang, Gengming Tao
  • Patent number: 10608158
    Abstract: A technique relates to a structure. An under-bump-metallization (UBM) structure includes a first region and a second region. The first and second regions are laterally positioned in the UBM structure. The first region includes a superconducting material. A substrate opposes the UBM structure. A superconducting solder material joins the first region to the substrate and the second region to the substrate.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: March 31, 2020
    Assignee: International Business Machines Corporation
    Inventors: David W. Abraham, John M. Cotte, Eric P. Lewandowski
  • Patent number: 10600823
    Abstract: A method for manufacturing a display element comprising a plurality of pixels, each comprising a plurality of subpixels. The method comprises undertaking, using a pick up tool, a first placement cycle (1908) comprising picking up a plurality of first, untested LED dies and placing them on a display substrate at locations corresponding to the plurality of pixels, testing (1912) the first LED emitters on the display substrate to determine one or more locations of non-functional first LED emitters, selecting one or more second tested LED dies based on a result of the test, configuring the selected one or more second LED dies to enable their pick up and placement on the display substrate and undertaking, using the PUT, a second placement cycle (2008) comprising picking up the selected one or more second LED dies and placing them on the display substrate at the determined locations of the nonfunctional first LED emitters.
    Type: Grant
    Filed: March 12, 2018
    Date of Patent: March 24, 2020
    Assignee: Facebook Technologies, LLC
    Inventors: Padraig Hughes, Joseph O'Keeffe, Celine Oyer, William Henry, David Massoubre, Pooya Saketi
  • Patent number: 10580888
    Abstract: A semiconductor device includes a gate trench extending into a Si substrate, a body region in the Si substrate, the body region including a channel region which extends along a sidewall of the gate trench, a source region in the Si substrate above the body region, a contact trench extending into the Si substrate and separated from the gate trench by a portion of the source region and a portion of the body region, the contact trench being filled with an electrically conductive material which contacts the source region at a sidewall of the contact trench and a highly doped body contact region at a bottom of the contact trench, and a diffusion barrier structure formed along the sidewall of the contact trench and disposed between the highly doped body contact region and the channel region, the diffusion barrier structure including alternating layers of Si and oxygen-doped Si.
    Type: Grant
    Filed: August 8, 2018
    Date of Patent: March 3, 2020
    Assignee: Infineon Technologies Austria AG
    Inventors: Oliver Blank, Thomas Feil, Maximilian Roesch, Martin Poelzl, Robert Haase, Sylvain Leomant, Bernhard Goller, Andreas Meiser
  • Patent number: 10573650
    Abstract: A semiconductor structure for a DRAM is described having multiple layers of arrays of thyristor memory cells and associated peripheral circuitry. Memory cells in a vertical string extending through the layers have an electrical connection to one terminal of the memory cells in that string. Word lines couple the strings together. Each layer of the array also includes bit line connections to memory cells on that layer. Methods of fabricating the array are described.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: February 25, 2020
    Assignee: TC Lab, Inc.
    Inventor: Harry Luan
  • Patent number: 10570529
    Abstract: A SiC epitaxial wafer includes: a substrate having an off angle of less than 4 degrees; and a SiC epitaxial growth layer disposed on the substrate having the off angle of less than 4 degrees, wherein an Si compound is used for a supply source of Si, and a C compound is used as a supply source of C, for the SiC epitaxial growth layer, wherein the uniformity of carrier density is less than 10%, and the defect density is less than 1 count/cm2; and a C/Si ratio of the Si compound and the C (carbon) compound is within a range of 0.7 to 0.95. There is provide a high-quality SiC epitaxial wafer excellent in film thickness uniformity and uniformity of carrier density, having the small number of surface defects, and capable of reducing costs, also in low-off angle SiC substrates on SiC epitaxial growth.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: February 25, 2020
    Assignee: ROHM CO., LTD.
    Inventor: Hirokuni Asamizu
  • Patent number: 10573742
    Abstract: A semiconductor device includes a gate trench extending into a Si substrate, a body region in the Si substrate adjacent the gate trench, a source region in the Si substrate above the body region, a contact trench extending into the Si substrate and filled with an electrically conductive material which contacts the source region at a sidewall of the contact trench and a highly doped body contact region at a bottom of the contact trench, a diffusion barrier structure formed along the sidewall of the gate trench, the diffusion barrier structure comprising alternating layers of Si and oxygen-doped Si and a Si capping layer on the alternating layers of Si and oxygen-doped Si, and a channel region formed in the Si capping layer and which vertically extends along the sidewall of the gate trench. Corresponding methods of manufacture are also described.
    Type: Grant
    Filed: August 8, 2018
    Date of Patent: February 25, 2020
    Assignee: Infineon Technologies Austria AG
    Inventors: Thomas Feil, Robert Haase, Martin Poelzl, Maximilian Roesch, Sylvain Leomant, Bernhard Goller, Ravi Keshav Joshi
  • Patent number: 10564498
    Abstract: Display systems and related methods involving bus lines with low capacitance cross-over structures are provided. A representative display system includes: a first structure comprising: a plurality of scan lines extending in a first direction; and a plurality of data lines extending in a second direction and crossing over the scan lines at respective cross-over locations, each of the plurality of data lines having a pair of side walls spaced apart from each other at each of the cross-over locations, with each of the side walls exhibiting a height higher than portions of the data lines not located at the cross-over locations.
    Type: Grant
    Filed: July 19, 2016
    Date of Patent: February 18, 2020
    Assignee: A.U. VISTA INC.
    Inventor: Lee Seok Lyul
  • Patent number: 10566463
    Abstract: In a power semiconductor device of the application a total number n of floating field rings (10_1 to 10_n) formed in a termination area is at least 10. For any integer i in a range from i=2 to i=n, a ring-to-ring separation di,i?i between an i-th floating field ring and a directly adjacent (i?1)-th floating field ring, when counting the floating field rings (10_1 to 10_n) along a straight line starting from a main pn-junction and extending in a lateral direction away from the main pn-junction, is given by the following formula: di,i?1=d1,0+?j=1j=i?1 ?j for i=2 to n, wherein d1,0 is a distance between the innermost floating field ring (10_1) closest to the main pn-junction and the main pn-junction, and wherein: ?zone1?0.05·?zone2<?j<?zone1+0.05·?zone2 for j=1 to I?2, 2·?zone2<|?j|<10·?zone2. for j=I?1, 0.95·?zone2<?j<1.05·?zone2 for j=I to n?1, ?zone2>0.1 ?m, and ??zone2/2<?zone1<?zone2/2, wherein I is an integer, for which 3?l?n/2.
    Type: Grant
    Filed: May 23, 2019
    Date of Patent: February 18, 2020
    Assignee: ABB Schweiz
    Inventors: Friedhelm Bauer, Umamaheswara Vemulapati, Marco Bellini
  • Patent number: 10566277
    Abstract: Methods for designing semiconductor components, for fabricating semiconductor components, and corresponding semiconductor components are provided. In this case, capacitance structures are either coupled to a supply network or used for rectifying design violations.
    Type: Grant
    Filed: May 11, 2017
    Date of Patent: February 18, 2020
    Assignee: Infineon Technologies AG
    Inventor: Andreas Kuesel
  • Patent number: 10566601
    Abstract: An imaging element has a laminated structure including a first electrode, a light-receiving layer formed on the first electrode, and a second electrode formed on the light-receiving layer. The second electrode is made of a transparent amorphous oxide having a conductive property.
    Type: Grant
    Filed: December 26, 2017
    Date of Patent: February 18, 2020
    Assignee: Sony Corporation
    Inventor: Toshiki Moriwaki